CN113050384A

CN113050384A - Semiconductor wafer processing method and cleaning brush head

Info

Publication number: CN113050384A
Application number: CN202010326540.4A
Authority: CN
Inventors: 苏倍毅; 洪蔡豪; 陈振杰
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2020-04-23
Filing date: 2020-04-23
Publication date: 2021-06-29

Abstract

Some embodiments of the present disclosure provide a method of processing a semiconductor wafer and a cleaning brush head. The method includes performing a cleaning process on a supporting surface of a wafer pedestal using a cleaning brush head having a plurality of microstructures. The microstructures are spaced apart from each other by a distance and have a tapered width. The method further includes placing a semiconductor wafer on the support surface of the wafer pedestal. The method further includes performing a photolithography process on the semiconductor wafer.

Description

Semiconductor wafer processing method and cleaning brush head

Technical Field

Some embodiments of the present disclosure relate to a method and tool for processing semiconductor wafers, and more particularly, to a method and tool for photolithography processing of semiconductor wafers and a cleaning brush head for cleaning a photolithography tool.

Background

The semiconductor integrated circuit industry has experienced a vigorous growth. Advances in integrated circuit materials and design have made each generation of integrated circuits smaller and more complex than previously produced. In the development of integrated circuits, the functional density (e.g., the number of devices connected within each chip area) has generally increased, while the geometry (e.g., the smallest component (or line) that can be created during the fabrication process) has generally decreased. This process of miniaturization can often provide a number of benefits by increasing production efficiency and reducing associated costs.

However, such scaling also increases the complexity of integrated circuit processing and fabrication. To achieve such advances, the same advances in integrated circuit processing and fabrication are needed.

Photolithography is a process of transferring a pattern to a photosensitive material overlying a semiconductor substrate by irradiating a reticle having the pattern with light. Historically in the semiconductor industry, the minimum feature size of smaller integrated wafers has been achieved by improving the photolithographic resolution by reducing the exposure wavelength of the photolithographic radiation source. Among higher resolution photolithography techniques, Extreme Ultraviolet (EUV) lithography, which uses EUV light having an exposure wavelength between 10nm and 130nm, is a promising next-generation photolithography solution for emerging technology nodes (e.g., 32nm, 22nm, 14nm, etc.).

While existing photolithographic techniques have been generally adequate for their intended purposes, they have not been fully satisfactory in all respects.

Disclosure of Invention

Some embodiments of the present disclosure provide a method for processing a semiconductor wafer. The method includes performing a cleaning process on a supporting surface of a wafer pedestal using a cleaning brush head having a plurality of microstructures. The microstructures are spaced apart from each other by a distance and have a tapered width. The method further includes placing a semiconductor wafer on the support surface of the wafer pedestal. The method further includes performing a photolithography process on the semiconductor wafer.

Some embodiments of the present disclosure provide a method for processing a semiconductor wafer. The method includes performing a cleaning process on a supporting surface of a wafer pedestal using a cleaning brush head having a plurality of tapered microstructures. The method further includes placing a semiconductor wafer on the support surface of the wafer pedestal. The method further includes performing a photolithography process on the semiconductor wafer.

Some embodiments of the present disclosure provide a cleaning brush head. The cleaning brush head is suitable for cleaning a supporting surface of a wafer seat for supporting a semiconductor wafer, and the supporting surface comprises a plurality of grooves with a given width. The cleaning brush head comprises an upper surface and a plurality of microstructures. The microstructures are spaced apart from each other by a distance, and the microstructures are gradually reduced from a first width to a second width in a direction away from the upper surface, wherein the second width is smaller than the predetermined width of the groove.

Drawings

Aspects of the present disclosure are better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that in accordance with industry standard practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a schematic diagram of a processing system in accordance with some embodiments of the present disclosure;

FIG. 2 is a schematic diagram of an exposure module according to some embodiments of the present disclosure;

FIG. 3 shows an enlarged view of the structure of the area M1 of FIG. 2;

FIG. 4 shows a schematic view of a cleaning head according to some embodiments of the present disclosure;

FIG. 5 shows an enlarged view of the structure of the region M2 of FIG. 4;

FIG. 6 illustrates a side view of a microstructure according to some embodiments of the present disclosure;

FIG. 7 is a schematic view of a bottom surface of a microstructure according to some embodiments of the present disclosure;

FIG. 8 is a schematic view of a bottom surface of a microstructure according to various embodiments of the present disclosure;

FIG. 9 illustrates a plurality of microstructures according to some embodiments of the present disclosure;

FIG. 10 illustrates a top view of a plurality of microstructures according to some embodiments of the present disclosure;

FIG. 11 is a schematic cross-sectional view of a plurality of microstructures according to some embodiments of the present disclosure;

FIG. 12 is a flowchart illustrating a method of performing a semiconductor wafer processing in accordance with some embodiments of the present disclosure;

FIG. 13 is a schematic diagram illustrating a step of performing a method of processing a semiconductor wafer according to some embodiments of the present disclosure;

FIG. 14 is a schematic diagram of a microstructure according to some embodiments of the present disclosure after a predetermined period of time.

[ notation ] to show

1: processing system

3: bearing box

5: semiconductor wafer

7: load port

9: load port

10 photoresist coating module

20 grinding module

30 exposure module

31 light source

32 lighting device

321 adjusting mirror

33 mask

331 transparent base material

332 patterned absorber layer

333 absorbent region

34 objective lens module

341 objective lens

342 objective lens

35 wafer seat

350 support surface

351 wafer adsorption plate

352 moving mechanism

353 upper surface

354: a protrusion

355 top surface

356 lattice structure

357 trench

358 particles of pollutants

36 fluid retaining device

37 driving member

38 impregnating solution

39 light beam

40 cleaning brush head

41 upper surface

411 annular region

412 annular region

42 microstructure

420 bottom surface

421 bottom edge

422 side surface

423 edge

424 vertex

425 flat surface

426 protruding feature

43 chip removal channel

42a microstructure

421a bottom edge

424a vertex

43a debris removal channel

42b microstructure

43b chip removal channel

42c microstructure

421c bottom edge

423c edge

51 base material

52 photoresist layer

511 back side

A1 included angle

A2 included angle

D1 width

D2 distance

D3 first Width

D4 second Width

D6 distance

D7 width

D8 width

L is the major axis direction

M1 region

M2 region

S10 method

Operation S11

Operation S12

Operation S13

Detailed Description

The following disclosure provides many different embodiments or examples for implementing different features of the disclosure and the description below describes specific examples of components and arrangements thereof in order to simplify the description of the disclosure. Of course, these specific examples are not intended to limit the disclosure. For example, if the following disclosure describes forming a first feature over or on a second feature, that reference includes forming the first feature in direct contact with the second feature, and may also include forming additional features between the first and second features that may not be in direct contact. In addition, various examples of the present disclosure may use repeated reference characters and/or words. These repeated symbols or words are provided for simplicity and clarity and are not intended to limit the relationship between the various embodiments and/or the appearance structure.

Furthermore, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, may be used herein for convenience in describing the relationship of an element or feature to another element(s) or feature(s) in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be appreciated that additional operational steps may be provided before, during and after the method, and that in certain method embodiments, certain operational steps may be substituted or omitted.

It should be noted that the embodiments discussed herein may not necessarily recite every component or feature that may be present within the structure. For example, one or more components may be omitted from the figures, for example, where a discussion of a component may be sufficient to convey various aspects of the embodiments. Further, the method embodiments discussed herein may be discussed in a particular order of performance, while in other method embodiments, they may be performed in any reasonable order.

The fabrication of integrated circuits has progressed from large scale integrated circuit design to ultra large scale integrated circuit design, with the process of the entire integrated circuit changing with the design, resulting in a reduction in the size of a single semiconductor device due to the upsizing, while the line width of the integrated circuit continues to shrink, from the sub-micron level down to the deep sub-micron level. Thus, the fabrication of integrated circuits has difficulties in the fabrication of the devices, in addition to overcoming the difficulties in the design of the devices. For example, in the integrated circuit manufacturing process, the integrated circuit utilizes the photolithography process to project a fine pattern on the surface of the semiconductor wafer, and the smaller the line width of the pattern, the more difficult the photolithography process is, or the more advanced photolithography tool is required to achieve the purpose of successfully transferring the pattern.

In the photolithography process of integrated circuits, the pattern on the mask is transferred to the surface of the semiconductor wafer by light projection. In preparation for light projection, projected light is accurately focused on the surface of a semiconductor wafer so that patterns can be accurately formed on the surface of the semiconductor wafer, and thus, various focusing methods are applied in the photolithography process of integrated circuits. It should be noted that the exposure method of the semiconductor wafer is to divide the semiconductor wafer into a plurality of exposure regions, then perform a plurality of exposure processes, perform one exposure process on one exposure region, and perform one focusing process every time the exposure process is performed, so that the pattern can be accurately formed on the surface of the semiconductor wafer.

During the focusing process of the semiconductor wafer, the position of the semiconductor wafer is adjusted to achieve the purpose of accurate focusing, and the mode of adjusting the semiconductor wafer not only rotates and moves the semiconductor wafer, so that the surface of the semiconductor wafer can be parallel to the projection lens of the micro-image machine, but also the height position of the semiconductor wafer is properly adjusted, so that the surface of the semiconductor wafer can be positioned in the focusing range of the micro-image machine. In the process of focusing the semiconductor wafer, the rotation angle and the height of the semiconductor wafer relative to the horizontal plane, which are the parameters for focusing the semiconductor wafer, are used. The manager of the factory knows whether the semiconductor wafer is parallel to the projection lens of the photolithography tool through these parameters to determine that the projection light is actually focused on the surface of the semiconductor wafer. In a production line of a semiconductor factory, a plurality of silicon wafers are used as a batch of production units, and after a batch of silicon wafers is subjected to a photolithography process, focusing parameters of the batch of silicon wafers are counted to determine whether the silicon wafers are qualified.

However, in the process of adjusting the position of the silicon wafer, there are exceptions, for example, the bottom of the silicon wafer has contamination particles, which causes a protrusion to be formed on a surface of the silicon wafer, and the surface is smaller than the range of an exposure area, so that in the focusing process of the photolithography process, the photolithography tool scans most of the area of the exposure area by using a laser beam to obtain an average parameter as a basis for adjusting the position of the semiconductor wafer, but after the semiconductor wafer is adjusted according to the average parameter, the projected light of the photolithography tool still cannot be focused accurately on the protrusion area, so that some areas on the silicon wafer are misaligned.

The alignment error of the micro-image process caused by the pollution particles or the pollution on the back of the silicon wafer is difficult to be corrected by the common micro-image process, and after the micro-image process of a batch of silicon wafers is finished, the whole silicon wafer is inspected by a microscope to find whether the situation occurs or not, so that the process condition of the whole batch of semiconductor wafers is known to judge whether the abnormal focusing phenomenon exists or not, the factors causing the abnormal focusing phenomenon are removed in time, the out-of-focus alignment phenomenon cannot be caused in the micro-image process of the next batch of silicon wafers, and the production cost of the integrated circuit is effectively reduced.

In order to solve the above-mentioned problems, some embodiments of the present disclosure provide a wafer seat cleaning method, which utilizes a plurality of microstructures having specific geometric shapes to clean the wafer seat, so as to effectively remove the contamination particles above the wafer seat and avoid the occurrence of abnormal focusing in the photolithography process.

FIG. 1 illustrates a schematic view of a processing system 1 according to some embodiments of the present disclosure. According to the disclosed embodiment, the processing system 1 includes a photoresist coating module 10, a polishing module 20, an exposure module 30, and one or more load ports, such as two load ports 7, 9. The configuration and number of modules of the processing system 1 may be increased or decreased according to the requirement, and is not limited to this embodiment.

The load ports 7, 9 are configured to receive a carrier 3 that can be used to load a plurality of semiconductor wafers 5, and the processing system 1 has an opening relative to the load ports 7, 9 for passage of the semiconductor wafers 5. In some embodiments, the carrier 3 located on the load port 7 is used for placing semiconductor wafers 5 to be processed, and the carrier 3 located on the load port 9 is used for placing semiconductor wafers 5 that have been processed in the processing system 1. It should be understood that the number of load ports of the processing system 1 may be increased or decreased as desired, and is not limited to the embodiment shown in fig. 1. In addition, the installation positions of the load ports 7 and 9 of the processing system 1 may be changed. For example, the load port 7 and the load port 9 of the processing system 1 are disposed adjacent to each other.

In some embodiments, the semiconductor wafer 5 enters the processing system 1 and is processed by the photoresist coating module 10, the polishing module 20, and the exposure module 30. The semiconductor wafer 5 supplied to the cassette 3 on the load port 7 is subjected to a photoresist coating process in the photoresist coating module 10 and is sent to the polishing module 20 for planarization. Then, the semiconductor wafer 5 is sent from the polishing module 20 to the exposure module 30, so that the photoresist on the surface of the semiconductor wafer 5 is exposed by the exposure module 30. Finally, the semiconductor wafer 5 is transferred from the exposure module 30 to the cassette 3 located on the load port 9. Thereafter, the wafer is transferred to another semiconductor apparatus, such as an etching apparatus or a Chemical Vapor Deposition (CVD) apparatus. The movement of the semiconductor wafer 5 may be performed by one or more robots (not shown in fig. 1) disposed within the processing system 1.

In some embodiments, the processing parameters of the photoresist coating module 10, the polishing module 20, the exposure module 30, and the transit time of the semiconductor wafer 5 through the robot may be manipulated by a pre-implantation process in a computer or microprocessor (not shown in FIG. 1).

According to some embodiments of the present disclosure, the exposure module 30 is characterized as follows:

FIG. 2 is a schematic diagram of an exposure module 30 according to some embodiments of the present disclosure. According to the embodiment of the present disclosure, the exposure module 30 is used to perform a photolithography process to form a pattern on the photoresist. In some embodiments, the exposure module 30 includes a light source 31, an illumination device 32, a mask 33, an objective module 34, a wafer stage 35, and a fluid retaining device 36. The light source 31 is located above the illumination device 32. The light source 31 is used for emitting a light beam 39 to the illumination device 32.

In some embodiments, the light source 31 is a mercury lamp having a wavelength in a range between about 436nm (G-line) and 365nm (I-line), a Krypton Fluoride (KrF) excimer laser having a wavelength of about 248nm, an Argon Fluoride (ArF) excimer laser having a wavelength of about 193nm, a fluorine (F2) excimer laser having a wavelength of about 157nm, or other light source having a desired wavelength (e.g., less than about 100 nm).

The above description of light sources makes it clear that each light source may have an approximate wavelength distribution, or line width, rather than an exact single wavelength. For example, an I-line (e.g., 365nm) wavelength mercury lamp need not be the exact 365nm, but may be a range of multiple wavelengths that are centered primarily around 365nm, and the wavelengths may be above or below 365 nm. This range can be used to determine a minimum possible line width in a lithographic process, and it has some small variation for the desired 365nm wavelength resulting in a narrower line width.

The illumination device 32 is located between the light source 31 and the mask 33. In some embodiments, the illumination device 32 is a condensing device (condensing device). The illumination device 32 is used for focusing the light beam 39 to the mask 33.

The illumination device 32 may comprise a single lens or a lens assembly having multiple lenses and/or other lens elements. For example, the illumination device 32 may include a microlens array, a shadow mask, and/or other structures designed to directly assist light from the light source 31 to the mask 33. In some embodiments, the illumination device 32 includes a plurality of adjustment mirrors 321 arranged in an array. In addition, the lighting device 32 includes a driving member 37. The driving member 37 is configured to move the position of the adjusting mirror 321 in the vertical direction. Alternatively, the driving member 37 is configured to move the position of the adjustment mirror 321 in the horizontal direction. Alternatively, the driver 37 is configured to rotate the adjustment mirror 321 to tilt the adjustment mirror 321 with respect to the horizontal plane.

The mask 33 is located between the illumination device 32 and the wafer stage 35. In some embodiments, the mask 33 is located between the illumination device 32 and the objective lens module 34. The mask 33 is used to partially shield the beam 39 and form a pattern on the semiconductor wafer 5. Different patterns can be formed on different wafers by replacing the mask 33 in the exposure module 30.

The mask 33 may be referred to as a mask or a reticle. The mask 33 includes a transparent substrate 331 and a patterned absorption layer 332 disposed on the transparent substrate 331. The light beam 39 is partially or completely blocked when the light beam passes through the absorption region 333 of the patterned absorption layer 332.

The objective lens module 34 is located between the wafer stage 35 and the mask 33. The objective lens module 34 is used for focusing the light beam 39 to the semiconductor wafer 5. In some embodiments, the objective lens module 34 includes a single objective lens or a plurality of

objective lenses

341 and 342.

The wafer seat 35 is located under the mask 33 and the objective lens module 34. The wafer holder 35 holds the semiconductor wafer 5. The wafer stage 35 includes a wafer chuck 351 and a moving mechanism 352. The wafer chuck 351 holds the semiconductor wafer 5. In some embodiments, the wafer chuck 351 is an electrostatic chuck. The moving mechanism 352 is used to move the wafer chuck 351 laterally or rotate the wafer chuck 351. Thus, the semiconductor wafer 5 has the ability to move in a lateral or rotational mode so that the semiconductor wafer 5 can be aligned with the mask 33. The fluid retaining device 36 is located between the mask 33 and the wafer pedestal 35 (or semiconductor wafer 5). The fluid retaining device 36 is used to retain the immersion fluid 38.

In some embodiments, the semiconductor wafer 5 includes a substrate 51 and a photoresist layer 52. The photoresist layer 52 is coated on the substrate 51 by a coating process. The photoresist layer 52 is patterned by an exposure process. The photoresist layer 52 includes a positive photoresist or a negative photoresist.

According to some embodiments, the substrate 51 is made of silicon, germanium, or other semiconductor materials. According to some embodiments, the substrate 51 is made of a composite semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). According to some embodiments, the substrate 51 is made of an alloy semiconductor, such as silicon germanium (SiGe), silicon germanium carbon (SiGeC), gallium arsenide phosphide (GaAsP), or indium gallium phosphide (GaInP). According to some embodiments, the substrate 51 includes an epitaxial layer. For example, the substrate 51 has an epitaxial layer overlying a bulk semiconductor (bulk semiconductor). According to some embodiments, the substrate 51 may be a silicon-on-insulator (SOI) or germanium-on-insulator (GOI) substrate.

The substrate 51 may include a plurality of device elements thereon. For example, the device elements formed on the substrate 51 may include a transistor, such as: metal Oxide Semiconductor Field Effect Transistors (MOSFETs), complementary metal oxide semiconductor transistors (CMOS), Bipolar Junction Transistors (BJTs), high voltage transistors, high frequency transistors, P-type field effect transistors (P-channel and/or n-channel field-effect transistors (PFETs)), P-type field effect transistors (n-channel field-effect transistors (NFETs), etc., and/or other devices, the device elements on the substrate 51 have been subjected to various processing processes such as deposition, etching, ion implantation, photolithography, annealing, and/or other processes.

Fig. 3 shows an enlarged view of the structure of the region M1 of fig. 2. In some embodiments, the upper surface 353 of the substrate 351 of the susceptor 35 has a plurality of protrusions (Burl)354 formed thereon. Also, the top surface 355 of each protrusion 354 has a plurality of lattice structures 356. The substrate 351 supports the semiconductor wafer 51 by the top surfaces 355 of the protrusions 354, wherein the top surfaces 355 of the plurality of protrusions 354 form the support surface 350 of the wafer pedestal 35. In one embodiment, the lattice structure 356 comprises a silicon carbide (SiC) lattice with trenches 357 formed between the lattice structures 356. The trench 357 has a given width between about 5 microns and 10 microns.

In some embodiments, as shown in FIG. 3, contamination particles 358 may adhere to the support surface 350 of the wafer chuck 35. Contaminant particles 358 may be caused by residual photoresist on the backside 511 of the semiconductor wafer 5 previously processed or by wear of wires of a handling tool used to handle the semiconductor wafer. These contaminant particles will become stuck to the trenches 357 between the lattice structures 356 and to the surface of the lattice structures 356. When the next processed semiconductor wafer 5 is placed on the supporting surface 350 of the susceptor 35, the back surface 511 of the semiconductor wafer 5 cannot be tightly attached to the supporting surface 350 of the susceptor 35, thereby causing a reduction in the flatness of a partial region of the semiconductor wafer 5.

To improve the above problem, some embodiments of the present disclosure provide a cleaning head 40 for cleaning the supporting surface 350 of the wafer seat 35.

Fig. 4 shows a schematic view of a cleaning head 40 according to some embodiments of the present disclosure, and fig. 5 shows an enlarged view of the area M2 of fig. 4. In one embodiment, the cleaning head 40 is a cylinder, but the disclosure is not limited thereto. The shape of the cleaning head 40 can be changed as desired or a suitable holding structure can be formed to facilitate grasping by a maintenance person. In one embodiment, the cleaning head 40 has an upper surface 41. The upper surface 41 may be a flat surface or a rounded surface.

As shown in fig. 5, a plurality of microstructures 42 are formed on top surface 41. Microstructures 42 are arranged in rows parallel to long axis direction L, and microstructures 42 have a pitch D2 (the distance between vertices 424). In addition, each row of microstructures 42 is separated from each other by a distance, so as to form a chip discharging channel 43 (i.e. the chip discharging channel 43 extends parallel to the long axis direction L). Furthermore, in each row of microstructures 42, chip evacuation channels 43 are formed between each microstructure 43. The debris ejection channel 43 has a width D1. The distance D2 is about 4-6 times the width D1. In an exemplary embodiment, the pitch D2 of the microstructures 42 is about 330 microns and the width D1 of the chip evacuation channels 43 is about 58 microns. Thus, the contaminant particles removed from the supporting surface 350 of the wafer seat 35 can be discharged through the chip discharge channel 43, thereby improving the cleaning effect.

In some embodiments, microstructures 42 have equal height H. Specifically, as shown in fig. 5, microstructures 42 extend outwardly from upper surface 41 and terminate at an apex 424. The peaks of microstructures 424 are separated from top surface 41 by a height H.

It is to be understood that the disclosed embodiments are capable of numerous variations and that they are not limited thereto. In other embodiments, as shown in fig. 4, the upper surface 41 of the cleaning head 40 has a plurality of

annular regions

411, 412 arranged concentrically. Each of the

annular regions

411, 412 has microstructures 42 formed thereon. The height of the microstructures 42 in the ring-shaped area 411 away from the center of the upper surface 41 of the cleaning brush head 40 is lower than the height of the microstructures 42 in the ring-shaped area 412 near the center of the upper surface 41 of the cleaning brush head 40. Since the force may be concentrated on the central region of the cleaning head 40 during manual holding, the force pressing the supporting surface 350 of the wafer seat 35 can be dispersed by the configuration of the central region with a lower microstructure, thereby preventing the supporting surface 350 of the wafer seat 35 from being scratched.

In some embodiments, microstructures 42 are tapered so that they have a decreasing width in a direction away from top surface 41. Specifically, as shown in fig. 6, the side 422 of the microstructure 42 is triangular, the base 42 thereof has a first width D3, and the apex 424 thereof has a second width D4. The first width D3 is greater than the second width D4. In an exemplary embodiment, the first width D3 is approximately 350 microns, and the second width D4 is equal to 0 microns or slightly greater than 0 microns. In one embodiment, the second width D4 is less than the width of the trenches 357 between the cells 356.

In one embodiment, side 422 of microstructure 42 has a symmetrical structure (e.g., side 422 of microstructure 42 is an isosceles triangle) with a base angle a1 (the angle between edge 423 and base 421) of between about 20 degrees and 70 degrees. In another embodiment, side 422 of microstructure 42 has an asymmetric structure. In one embodiment, as shown in FIG. 7, the bottom surface 420 of the microstructure 42 is triangular.

In one embodiment, microstructures 42 have a hardness similar to contaminant particles 358 or a higher hardness than contaminant particles 358 to increase lifetime. In an exemplary embodiment, contaminant particles 358 are TiN with a Vickers hardness of about 2000. to effectively remove contaminant particles from a cleaning process, microstructure 42 has a Vickers hardness of between about 1200 and about 10000. In one embodiment, the hardness of microstructures 42 has a vickers hardness of between about 1500 and about 3500.

The microstructure 42 can be made of any material with suitable hardness, such as zirconium dioxide (ZrO)₂Vickers hardness of about 1200), silicon nitride (Si)₃N₄Vickers hardness of about 1500 to about 1600, AlN (Vickers hardness of about 1350 to about 1700), and a composite material of alumina and titanium carbide (Al)₂O₃-TiC having a vickers hardness of about 2100), silicon carbide (SiC having a vickers hardness of about 2500), diamond (having a vickers hardness of about 10000), or combinations thereof.

It is understood that the shape and size of the microstructures 42 are not limited thereto, and for example, microstructures that can be used for wafer seat cleaning purposes can be formed on the cleaning brush head 40 of the present disclosure. Various embodiments of the microstructure variations are provided below.

Fig. 8 shows a bottom view of a microstructure 42 according to various embodiments of the present disclosure. In some embodiments, the bottom surface of the microstructure 42 may have a shape other than the triangular shape shown in fig. 7, such as a rectangular shape, a circular shape, a trapezoidal shape, a polygonal shape, or a combination thereof. In some embodiments, microstructures 42 having different base shapes are arranged adjacent to the upper surface 41 (FIG. 4) of the cleaning head 40. The plurality of microstructures 42 having different base shapes may have the same uniform height (i.e., the distance of the apex compared to the upper surface 41 of the cleaning head 40), but different base shapes.

Fig. 9 shows a schematic view of a microstructure 42a according to some embodiments of the present disclosure. In some embodiments, the microstructures 42a are a plurality of triangular prisms parallel to each other and sequentially arranged in the long axis direction L. The microstructures 42a have a gradually decreasing width from the direction away from the upper surface 41. In the long axis direction L, the adjacent microstructures 42a have a distance D6 (distance between the apexes 424a of the microstructures 42 a), each microstructure 42a is separated by a chip evacuation channel 43a, the chip evacuation channel 43a has a width D7, and the bottom 421a of the microstructure 42a has a width D8. The spacing D6 is about 4-6 times the width D7. In an exemplary embodiment, the width of the separation distance D6 is 54 microns, the width D7 is 8.3 microns, and the width D8 is 52 microns.

Fig. 10 is a top view of a microstructure 42b according to some embodiments of the present disclosure. In some embodiments, the microstructures 42b are dot-shaped structures and have a circular or elliptical transverse cross-section. In some embodiments, the plurality of rows of microstructures 42b are arranged in sequence along the long axis L to form a matrix array. In some embodiments, chip evacuation channels 43b are provided between adjacent microstructures 42b

Are not immediately adjacent to each other at a distance.

Fig. 11 shows a cross-sectional view of a microstructure 42 and a microstructure 42c according to some embodiments of the present disclosure. In some embodiments, microstructures with different included angles are staggered to generate different cleaning effects. For example, in the embodiment shown in fig. 11,

microstructures

42 and 42c are arranged in a staggered manner in the long axis direction L, wherein the included angle a1 between edge 423 and bottom 421 of microstructure 42 is different from the included angle a2 between edge 423c and bottom 421c of microstructure 42 c. In one embodiment, the included bottom angle a1 is between about 45 degrees and about 70 degrees, and the included bottom angle a2 is between about 20 degrees and about 45 degrees. Thus, the peaks of the

microstructures

42 and 42c have different degrees of sharpness, and deep cleaning can be performed for different lattice surfaces.

Fig. 12 is a flowchart illustrating a method S10 for performing a semiconductor wafer processing according to some embodiments of the present disclosure. It will be appreciated that additional operations may be provided before, during, and after the operations shown in fig. 12. For other embodiments of the method, some of the operations described below may be replaced or reduced. The order of operations/processes may be interchangeable. The following embodiments may employ materials, configurations, and dimensions described with respect to the above embodiments, and detailed descriptions thereof may be omitted.

The method S10 includes an operation S11 of cleaning the supporting surface 350 of the wafer pedestal 35 with a cleaning brush head 40 having a plurality of microstructures (e.g., microstructures 42) arranged in sequence along the longitudinal direction L. In some embodiments, operation S11 is performed manually and is performed after the previous semiconductor wafers are removed from the wafer seat 5 after the photolithography process is completed. During the cleaning process, the upper surface 41 of the cleaning head 40 faces the supporting surface 350 of the wafer holder 35, so that the microstructure 42 contacts the supporting surface 350 of the wafer holder 35. In some embodiments, as shown in FIG. 13, since microstructures 42 can extend into trench 357 to clean contaminant particles 358, contaminant particles 358 can be effectively removed from support surface 350, and no contaminant particles 358 remain in cleaned trench 357.

In some embodiments, as shown in fig. 14, after performing operation S11 for a predetermined period of time, the microstructure 42 may be worn, such that the top of the microstructure 42 has a flat surface 425. At this point, the flat surface 425 and the edge of the microstructure 42 still have the protruding feature 426 thereon, so that the support surface 350 of the wafer pedestal 35 can still be cleaned and the contaminant particles in the trench 357 can be effectively removed. According to an experimental result, before the microstructures 42 wear to the bottom edge 420, the microstructures 42 always have a better cleaning effect on the supporting surface 350 of the wafer seat 35 than the conventional marble having an irregular shape.

The method S10 includes an operation S12 of placing the semiconductor wafer 5 on the support surface 350 of the wafer pedestal 35. In some embodiments, the semiconductor wafer 5 may be placed flat on the support surface 350 of the wafer pedestal 35 because the support surface 350 of the wafer pedestal 35 has been cleaned and no contamination particles remain on the support surface 350 of the wafer pedestal 35.

The method S10 includes an operation S13 of performing a photolithography process on the semiconductor wafer 5. In some embodiments, as shown in FIG. 2, during the photolithography process, the light source 31 emits a light beam 39 to the illumination device 32, and the illumination device 32 focuses the light beam 39 onto the mask 33. The mask 33 partially shields the beam 39, and the patterned beam is projected onto the semiconductor wafer 5 through the objective lens module 34 to expose the photoresist layer 52 on the semiconductor wafer 5. Thereafter, the wafer is transferred to another semiconductor apparatus, such as an etching apparatus or a Chemical Vapor Deposition (CVD) apparatus. The movement of the semiconductor wafer 5 may be performed by one or more robots disposed within the processing system 1.

In various embodiments of the present disclosure, a wafer pedestal for carrying a semiconductor wafer is cleaned by a cleaning brush head having a microstructure with a specific geometry. The micro-structure of the cleaning brush head can extend into the groove on the surface of the wafer seat to remove the pollution particles remained in the groove, so that the pollution particles on the surface of the wafer seat can be effectively removed. Therefore, when the subsequent photolithography process of the semiconductor wafer is performed by using the wafer seat, the semiconductor wafer can be flatly placed on the wafer seat, and the process yield of semiconductor wafer processing can be improved. On the other hand, the cleaning brush head has a better cleaning function, so that the machine halt time caused by maintaining the wafer seat can be shortened, and the production cost is further reduced.

Some embodiments of the present disclosure provide a method for processing a semiconductor wafer. The method includes performing a cleaning process on a supporting surface of a wafer pedestal using a cleaning brush head having a plurality of microstructures. The microstructures are spaced apart from each other by a distance and have a tapered width. The method further includes placing a semiconductor wafer on the support surface of the wafer pedestal. The method further includes performing a photolithography process on the semiconductor wafer. In the above embodiments, the cleaning process is performed by cleaning the support surface with a microstructure having a tapered profile. In the above embodiments, the cleaning process is performed by cleaning the support surface using a staggered arrangement of microstructures having different bottom included angles. In the above embodiments, the cleaning process is performed by cleaning the support surface with microstructures having a base angle of about 20 degrees to about 70 degrees. In the above embodiments, the cleaning process is performed by cleaning the plurality of grooves on the supporting surface with the microstructures, and portions of the microstructures extend into the grooves to remove the contaminant particles in the grooves.

Some embodiments of the present disclosure provide a method for processing a semiconductor wafer. The method includes performing a cleaning process on a supporting surface of a wafer pedestal using a cleaning brush head having a plurality of tapered microstructures. The method further includes placing a semiconductor wafer on the support surface of the wafer pedestal. The method further includes performing a photolithography process on the semiconductor wafer. In the above embodiments, the cleaning process is performed by cleaning the support surface with the plurality of microstructures having a base angle in a range from about 20 degrees to about 70 degrees.

Some embodiments of the present disclosure provide a cleaning brush head. The cleaning brush head is suitable for cleaning a supporting surface of a wafer seat for supporting a semiconductor wafer, and the supporting surface comprises a plurality of grooves with a given width. The cleaning brush head comprises an upper surface and a plurality of microstructures. The microstructures are spaced apart from each other by a distance, and the microstructures are gradually reduced from a first width to a second width in a direction away from the upper surface, wherein the second width is smaller than the predetermined width of the groove. In the above embodiments, the microstructure has a tapered cross section. In the above embodiments, the microstructures having different bottom angles are staggered along the long axis direction.

The foregoing outlines features or examples of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of processing a semiconductor wafer, comprising:

performing a cleaning process on a supporting surface of a wafer seat by using a cleaning brush head with a plurality of microstructures, wherein the microstructures are separated from each other by a distance and have gradually reduced widths;

placing a semiconductor wafer on the support surface of the wafer seat; and

performing a photolithography process on the semiconductor wafer.

2. The method of claim 1, wherein the cleaning is performed by cleaning the support surface with the plurality of microstructures having a tapered profile.

3. The method as claimed in claim 2, wherein the cleaning is performed by cleaning the support surface using a staggered arrangement of the plurality of microstructures having different included bottom angles.

4. The method of claim 2, wherein the cleaning is performed by cleaning the support surface with the plurality of microstructures having a bottom included angle in a range of 20 degrees to 70 degrees.

5. The method as claimed in claim 1, wherein the cleaning process is performed by cleaning a plurality of grooves on the supporting surface with the plurality of microstructures, and portions of the plurality of microstructures protrude into the plurality of grooves to remove contaminant particles in the plurality of grooves.

6. A method of processing a semiconductor wafer, comprising:

a cleaning brush head with a plurality of conical microstructures is used for cleaning a supporting surface of a wafer seat;

placing a semiconductor wafer on the support surface of the wafer seat; and

performing a photolithography process on the semiconductor wafer.

7. The method of claim 6, wherein the cleaning is performed by cleaning the support surface with the plurality of microstructures having a bottom included angle in a range of 20 degrees to 70 degrees.

8. A cleaning brush head adapted for cleaning a support surface of a wafer chuck supporting a semiconductor wafer, the support surface including a plurality of grooves having a predetermined width, the cleaning brush head comprising:

an upper surface; and

the microstructures are spaced apart from each other by a distance, and taper from a first width to a second width in a direction away from the upper surface, wherein the second width is smaller than the predetermined width of the trench.

9. The cleaning head of claim 8 wherein the plurality of microstructures has a tapered cross-section.

10. The cleaning head of claim 9 wherein the plurality of microstructures having different base angles are staggered.