CN113036739A - Direct-current fault current suppression method based on submodule two-stage active control - Google Patents

Abstract

A direct current fault current suppression method based on submodule two-stage active control belongs to the technical field of high-voltage flexible direct current transmission. The invention aims to provide a direct current fault current suppression method based on submodule two-stage active control, which realizes efficient suppression of direct current grid fault current through submodule two-stage active control. The invention designs the STAC controller based on the basic structure of the MMC and an equivalent circuit after the fault, and starts current-limiting control according to two sections of fault detection criteria and preset maximum short-circuit current by setting current limiter control parameters suitable for converter stations under different operating conditions, so that the MMC valve controller reduces the proportion of a switching sub-module to limit the fault current. The invention is scientific and reasonable, has strong applicability, high reliability and good effect, and provides the working principle of the STAC and the design method of the controller of the STAC.

Description

Direct-current fault current suppression method based on submodule two-stage active control

Technical Field

The invention belongs to the technical field of high-voltage flexible direct-current transmission.

Background

With the continuous change of the world energy supply structure and the continuous promotion of the upgrade of the whole industry in China, the guarantee of energy supply and the promotion of interconnection and intercommunication are important guarantees for the nation to realize high-quality development. Due to the distribution characteristics of traditional energy, renewable energy and the like in China, a flexible direct-current power grid based on a Modular Multilevel Converter (MMC) is an inevitable trend for future development because the MMC is suitable for long-distance transmission and large-scale grid connection, and meanwhile, the Modular structure of the MMC has the characteristics of being suitable for different voltage levels, reducing filter equipment and the like.

However, due to the characteristics of low damping and low inertia of the flexible direct-current power grid, after a direct-current fault occurs, the short-circuit current rises very fast and has a high peak value, and the reliability of the flexible direct-current power grid is seriously threatened. At present, a method for processing fault current of a flexible direct current power grid mainly adopts a cooperative coordination of a control and protection system and a Direct Current Circuit Breaker (DCCB) to isolate short-circuit faults on a line, but the circuit breaker which has the capabilities of clearing fault current, dissipating energy and rapidly interrupting has high technical difficulty, and the construction investment of the whole power grid is increased certainly.

Many current limiting schemes also focus on suppressing short circuit currents by the modular nature of MMCs and the impact of modulated reference signals on dc voltages, with high controllability of MMCs. The current active current limiting method mostly uses dead zone and closed loop control, can cause delay in current limiting, and does not consider the problems of bridge arm current overload and guarantee of power transmission limitation of an alternating current side and a direct current side. However, the active current limiting scheme based on the MMC self-control does not generate extra cost, avoids conduction loss and maintenance requirements, and meanwhile, an accurate and reliable starting strategy ensures that the current limiting control only acts after a fault, and the normal operation of the system is not influenced.

Disclosure of Invention

The invention aims to provide a direct current fault current suppression method based on submodule two-stage active control, which realizes efficient suppression of direct current grid fault current through submodule two-stage active control.

The method comprises the following steps:

s1, MMC basic structure

The three-phase main circuit consists of six bridge arms, and each bridge arm consists of N series submodules SM_n(n ═ 1, 2.) and a bridge arm inductance L_armAnd (4) forming. The sub-modules may be configured as half-bridge, full-bridge, or hybrid;

s2 MMC equivalent circuit after fault

If a fault occurs when t is equal to 0, assume a pre-fault operating state U_c＝U₀，i_dc＝I₀The method comprises the following steps:

wherein tau, omega, I₀Depending on the original parameters of the circuit and the running state of the converter station, the method cannot predict and quantitatively analyze, but the capacitor discharge stage can be regarded as almost unchanged in capacitor voltage within a few ms after the fault, and the method comprises the following steps:

performing first-order Taylor expansion on the obtained solution to obtain:

fault current i_dcIs determined by U at fault₀And equivalent inductance L_eqWherein U is₀Controlling the input quantity of the sub-module by the transient process of the MMC after the fault, and defining the input quantity of the MMC relative to i_dcThe function K of the bridge arm unit is combined with the number of the sub-modules input by the bridge arm unit given by the valve controller to reduce U₀Thereby enabling the MMC to actively restrain short-circuit current;

s3 designing STAC controller

The control loop in the control strategy of the half-bridge type MMC adopts closed-loop control, the outer ring controller maintains the active power or alternating current and direct current voltage of the MMC at a set value, and the outer ring outputs a direct current reference value I_dcrefProviding input for inner loop control, and outputting DC voltage reference value U via proportional-integral control link_dcnCombined with a circulating current suppression controller to output a differential mode voltage V_diffParticipating in switching control and modulation order of sub-modulesThe segment adopts nearest level approximation modulation;

defined with respect to i_dcIs a piecewise function, t₀Time of occurrence of DC side fault, t_CGenerally setting 1-2 ms delay for the signal output time of fault detection 2, and also setting the mode selection switching time, t, of the current limiting controller_BFor the DC breaker DCCB breaking time, the formula is expressed as follows

When short-circuit fault occurs on the DC side, the DC current i_dcRapidly rises, the voltage of the fault line immediately falls, and at fault detection t₀＜t＜t_CStage when the current variation exceeds a set threshold di_thDt, fault detection 1 output current rate of change di_dc/dt, where λ (0)<λ<1) According to the requirements of the alternating-current side outlets of different converter stations and different operation condition settings, the output of the current limiting controller is switched from a steady-state value K-1 to K-1 (1-alpha i)_dc)×λdi_dcThe/dt is used for reducing the input proportion of the submodules to limit the short-circuit current;

after a short-circuit fault at the DC outlet i_dcRising substantially linearly for i obtained during the sampling period_dcThe current change rate di obtained by data set derivation_dcThe/dt meets the requirement of a current limiting controller to realize primary current limiting;

the 2 nd stage of current limiting is added, the voltage of the current limiting reactor can rise in a short time after the system has direct current fault, the system does not change in normal operation, and the voltage change dU of the current limiting inductor of the detection circuit is detected_LdcWhen the/dt exceeds a set threshold value, the STAC second-stage control is activated, the output of the switching current-limiting controller is K-1-beta (i)_max,set-i_dc) The submodule further reduces the throw ratio to further reduce and limit the fault current;

in order to take detection speed and anti-interference capability into consideration, the detection threshold value of the voltage change rate of the current-limiting inductor is 0.25, i_max,setFor a set maximum short-circuit current i to ensure that the MMC is not operated locked_max,setSelecting rated current I of 2 times_NNamely:

i_max,set＝2I_N (7)

s4, setting current limiter control parameters suitable for the converter stations under different operating conditions, and starting current limiting control according to the two sections of fault detection criteria and the preset maximum short-circuit current, so that the MMC valve controller reduces the proportion of the sub-modules to limit the fault current.

The invention is scientific and reasonable, has strong applicability, high reliability and good effect, and provides the working principle of the STAC and the design method of the controller of the STAC.

Drawings

FIG. 1 is a basic block diagram of an MMC;

FIG. 2 is a graph of the capacitor discharge phase after an MMC fault;

FIG. 3 is a diagram of an equivalent circuit for discharging a capacitor;

FIG. 4 is a schematic diagram of a DC fault current suppression method based on two-stage active control of a submodule;

FIG. 5 is a diagram of a simulation system;

FIG. 6 is a DC current diagram for MMC;

fig. 7 is a graph comparing current flowing through circuit breaker CB 23.

Detailed Description

The method comprises the following steps:

step 1MMC basic structure is shown in FIG. 1

In fig. 1, the three-phase main circuit consists of six bridge arms, each bridge arm consisting of N series submodules SM_n(n ═ 1, 2.) and a bridge arm inductance L_armAnd (4) forming. The sub-modules can be configured to be of a half-bridge type, a full-bridge type or a mixed type, and the active current-limiting design method is based on a half-bridge type MMC.

In normal operation, the IGBT switch S in the half-bridge submodule is controlled₁、S₂Make or break half-bridge submodule capacitor C₀Switching between the engaged or bypass state. When S is₁＝1，S₂When equal to 0, the bypass diode D₁Conducting and C₀Feeding u_SM＝u_C(ii) a When S is₁＝0，S₂When 1, the bypass diode D₂Conducting and C₀Bypass, u _SM0, wherein u_SMIs the sub-module voltage, u_CIs a capacitor voltage and a capacitor C₀The charging and discharging state of (2) is determined by the current direction of the bridge arm.

To maintain a DC voltage U_dcAnd (2) stabilizing, ensuring that the sum N of the number of the submodules input by each phase of upper and lower bridge arms is the same, enabling the three-phase bridge arms to run in a symmetrical state, and generating expected voltage by modulating and distributing the number of the submodules of the upper and lower bridge arms:

U_dc＝u_p+u_n＝N×u_c (1)

in the formula (1), u_p、u_nThe voltage of a single-phase upper bridge arm and the voltage of a single-phase lower bridge arm are respectively, MMC generates trigger signals of an upper bridge arm submodule and a lower bridge arm submodule through modulation, and K in the graph 1 is the output reduction proportion of the designed current limiting controller STAC.

As shown in FIG. 2, after the MMC is short-circuited at the direct current side, the equivalent circuit, C, of the capacitor discharge stage of the submodule inside the MMC_legFor single-phase equivalent capacitance in the discharge phase, L_dc、R_dcThe sum of the current-limiting inductance and the line inductance from the converter to the short-circuit point and the line resistance R_gIs a fault resistance. Wherein C is_leg＝2C₀And N is the input number of the submodules.

Step 2, in the existing engineering application, each converter station outlet direct current bus is provided with a direct current reactor, so that the fault current and the fault diffusion rate are effectively limited after the fault, and the line impedance is increased. For an adjacent end MMC connected with a near end MMC, the adjacent end MMC is a source of a small part of fault current, meanwhile, the whole direct current power grid is stable, and the voltage drop of the adjacent end MMC is very limited after the fault. Further, an equivalent circuit of a capacitor discharging phase before the converter is locked after the fault is obtained by combining the figure 2 is shown in a figure 3.

From fig. 3, the equation can be derived:

if a fault occurs when t is equal to 0, assume a pre-fault operating state U_c＝U₀，i_dc＝I₀The method comprises the following steps:

wherein tau, omega, I₀Depending on the original parameters of the circuit and the running state of the converter station, the method cannot predict and quantitatively analyze, but the capacitor discharge stage can be regarded as almost unchanged in capacitor voltage within a few ms after the fault, and the method comprises the following steps:

performing first-order Taylor expansion on the obtained solution to obtain:

can clearly obtain the fault current i_dcIs determined by U at fault₀And equivalent inductance L_eqWherein U is₀The input quantity of the sub-module can be controlled by the transient process of the MMC after the fault, and the I is defined_dcThe function K of the bridge arm unit is combined with the number of the sub-modules input by the bridge arm unit given by the valve controller to reduce U₀Thereby enabling the MMC to actively suppress the short-circuit current.

Step 3, designing the STAC controller, wherein the STAC controller is shown in FIG. 4

The control loop in the control strategy of the half-bridge type MMC adopts closed-loop control, the outer ring controller maintains the active power or alternating current and direct current voltage of the MMC at a set value, and the outer ring outputs a direct current reference value I_dcrefProviding input for inner loop control, and outputting DC voltage reference value U via proportional-integral control (PI) link_dcnCombining with a Circulating Current Suppressing Controller (CCSC) to output a differential mode voltage V_diffAnd participating in switching control of the sub-modules, wherein the Modulation stage adopts Nearest Level Modulation (NLM). The number N of upper and lower bridge arm input submodules generated by conventional control_refThen, combining the output K of the current limiting controller (STAC) based on the submodule two-stage control to determine the post-fault cut-offThe proportion of the submodules, the voltage of the capacitor is balanced by the capacitor voltage-sharing control loop, and the switching-in or switching-off of each submodule is determined by a modulated trigger signal, so that the direct-current side voltage is reduced and the fault current is limited.

The current limiting controller is designed as shown in FIG. 4, and when the system is in steady-state operation, the DC current change rate di_dcAlmost invariable/dt, line voltage and DC outlet voltage U_dcAlso operating at nominal value while limiting the inductor voltage U_LdcNo change occurs.

Defined with respect to i_dcIs a piecewise function, t₀Time of occurrence of DC side fault, t_CGenerally setting 1-2 ms delay for the signal output time of fault detection 2, and also setting the mode selection switching time, t, of the current limiting controller_BFor the DC breaker DCCB breaking time, the formula is expressed as follows

When short-circuit fault occurs on the DC side, the DC current i_dcRapidly rises, the voltage of the fault line immediately falls, and at fault detection t₀＜t＜t_CStage when the current variation exceeds a set threshold di_thDt, fault detection 1 output current rate of change di_dc/dt, where λ (0)<λ<1) According to the requirements of the alternating current side outlet of different converter stations and different operation conditions. The output of the current limiting controller is switched from a steady state value K-1 to K-1-alphai_dc)×λdi_dcAnd/dt, reducing the input proportion of the submodules to limit the short-circuit current.

After a short-circuit fault at the DC outlet i_dcRising substantially linearly for i obtained during the sampling period_dcThe current change rate di obtained by data set derivation_dcThe/dt can meet the requirement of a current limiting controller to realize preliminary current limiting. As the short-circuit current continues to increase, at t_C＜t＜t_BIn the stage, the inductance and capacitance in the whole discharge loop inevitably produce large oscillation, especially in the case of cable line, if the fault position occurs in the middle section of the line, i_dcThe oscillation is more pronounced, di_dcThe output of the feedback control circuit is used as a reference variable input by a current limiter, so that the feedback control circuit is difficult to stably support the reduction proportion coefficient K, and the current limiting effect of the STAC is seriously influenced.

The 2 nd stage of current limiting is added, the voltage of the current limiting reactor can rise in a short time after the system has direct current fault, the system does not change in normal operation, and the voltage change dU of the current limiting inductor of the detection circuit is detected_LdcWhen the/dt exceeds a set threshold value, the STAC second-stage control is activated, the output of the switching current-limiting controller is K-1-beta (i)_max,set-i_dc) The submodule further reduces the throw ratio to limit the fault current.

The voltage change of the current-limiting inductor adopts single-ended quantity to carry out fault detection, the fault detection cannot be influenced by communication delay, the smaller the detection threshold value is, the faster the detection speed is, and the larger the detection threshold value is, the detection accuracy can be improved, and because the current-limiting inductor voltage can be raised immediately after the fault, the current limiting inductor voltage in the 2 nd stage can be used prematurely, so that the detection threshold value of the voltage change rate of the current-limiting inductor is 0.25 in consideration of the detection speed and the anti-interference capacity. i.e. i_max,setI, for ensuring the safety of IGBT device and ensuring the MMC is not locked in fault clearing stage_max,setSelecting rated current I of 2 times_NNamely:

i_max,set＝2I_N (7)

and 4, setting current limiter control parameters suitable for the converter stations under different operating conditions, and starting current limiting control according to the two sections of fault detection criteria and the preset maximum short-circuit current, so that the MMC valve controller reduces the proportion of the switching sub-module to limit the fault current. The STAC continuously outputs adaptive reduction-throw ratio to inhibit fault current before the DCCB is successfully switched off, so that the maximum switching-off current of the DCCB can be effectively reduced. After the DCCB is disconnected, the direct current change rate does not meet the STAC starting criterion any more, the MMC is immediately switched to a normal control mode, the STAC exits and recovers a normal submodule to control switching, and the power and voltage of the whole system are gradually recovered to a normal operation state.

Simulation experiment

Each converter station is a half-bridge type MMC topology, the converter stations are not locked in the fault period, each converter station is provided with a current-limiting controller designed in the text, an overhead line adopts a frequency domain vector model, main parameters of the system are shown in a table 1, and a simulation system is shown in a figure 5.

TABLE 1 DC SYSTEM PRIMARY PARAMETERS

Comparing three schemes of no current-limiting measure (scheme 1), increasing inductance of a current-limiting reactor (scheme 2) and STAC (scheme 3) proposed herein, analyzing fault current characteristics, verifying a current-limiting effect, when t is set to be 1s in all the three cases, generating a bipolar short-circuit fault at a port of an overhead Line23 close to an MMC2, wherein fault detection and identification time is 1ms, under the condition of configuring the same DCCB, the DCCB is switched off after 5ms of fault, and fault current is cleared, and simulation results are shown in fig. 6 and 7.

In schemes 1 and 2, only the current limiting reactor and each bridge arm inductor limit the fault current from the fault occurrence to the fault current clearing process of the DCCB, and in scheme 3, at t₀～t_C、t_C～t_BAnd the stage STAC limits the fault current together with the current-limiting reactor and the bridge arm inductor, wherein the comparison of the schemes 2 and 3 obviously shows that the STAC can avoid the problems of system oscillation and stability caused by the overlarge current-limiting reactor while effectively inhibiting the fault current, and can also constructively reduce the investment and the occupied area of the converter station.

In terms of fault clearing time, scenarios 1, 3 are almost at the same time t₁And t₂The fault current is cleared, and the scheme 2 of limiting the current by increasing the current-limiting inductor enables the DCCB to clear the fault time t₃The energy dissipation during fault clearing is mainly determined by fault clearing time and the DCCB arrester current, so the designed current limiting measures can reduce the fault current and accelerate the fault clearing speed, the energy dissipation after the fault is correspondingly reduced, and the service life of the arrester is prolonged.

For the DCCB on-off current, the successful on-off current of the circuit breaker in the scheme 1 reaches 14.7kA, the corresponding circuit breaker design and the on-off capacity have higher requirements, and the DCCB in the scheme 3 is on-offThe fault current is reduced by 49.7% compared with 1 and 36.4% compared with scheme 2 of increasing the current-limiting reactor, and compared with a simulation result of 3.4 sections, I in a four-terminal network₂₃There will be some variation, but the current feed of the non-fault end converter station is generally less than 20%, the current limiting effect will not be affected, and the fault current is still limited. Therefore, the designed scheme 3 current limiting method can be suitable for a DCCB fault clearing scheme with both economy and reliability.

In the fault detection stage, as can be seen from the schemes 1 and 2, the smaller current-limiting reactor in the scheme 1 enables the rising rate of the direct-current fault current to be obviously higher than that in the scheme 2, theoretically, the higher current rising rate can be improved, which is beneficial to improving the detection sensitivity, and meanwhile, the improvement of the fault detection speed is beneficial to the control flexibility of the STAC, and the condition that the output of the current-limiting controller is close to the lower limit threshold value for limiting current is avoided.

In the scheme 3, a certain current limiting effect is achieved in the fault detection stage, because the current limiting controller starts to reduce the sub-module by a certain proportion K at the moment of the fault corresponding to the switching microsecond level of the sub-module. In fact, the first-stage current limiting is matched with fault detection to adapt to different fault detection time, and if the fault detection criterion and the second-stage starting criterion of the current limiting controller are simultaneously met, the fault current is limited to a greater extent in the second stage, so that the system is prevented from being impacted due to false operation under the condition that the operating conditions are changed. In the scheme 3, after the fault, the STAC reduces the voltage of the direct current side to limit the fault current immediately after the fault, which can cause the outlet voltage of the alternating current side to be reduced, so that the alternating current and the bridge arm current are increased and even overcurrent, and simultaneously, the DCCB can interrupt the fault current according to the requirement of the system on safe operation, and the bridge arm current and the alternating current should not exceed the maximum allowable current in the whole fault detection and removal process. In fact, the problems of bridge arm current transient caused by direct current fault are also influenced by factors such as initial conditions of a fault circuit, direct current fault line parameters, capacitor charging during recovery and the like, and the maximum value of the transient current is difficult to accurately solve, so that the preset parameters such as the maximum short-circuit current still have certain conservatism, and the fault current can still be limited to the maximum extent in a scene with low requirement on the voltage of an alternating current side.

Claims (1)

1. A direct current fault current suppression method based on submodule two-stage active control comprises the following steps:

s1, MMC basic structure

The three-phase main circuit consists of six bridge arms, and each bridge arm consists of N series submodules SM_n(n ═ 1, 2.) and a bridge arm inductance L_armAnd (4) forming. The sub-modules may be configured as half-bridge, full-bridge, or hybrid;

s2 MMC equivalent circuit after fault

If a fault occurs when t is equal to 0, assume a pre-fault operating state U_c＝U₀，i_dc＝I₀The method comprises the following steps:

wherein tau, omega, I₀Depending on the original parameters of the circuit and the running state of the converter station, the method cannot predict and quantitatively analyze, but the capacitor discharge stage can be regarded as almost unchanged in capacitor voltage within a few ms after the fault, and the method comprises the following steps:

performing first-order Taylor expansion on the obtained solution to obtain:

fault current i_dcIs determined by U at fault₀And equivalent inductance L_eqWherein U is₀Controlling the input quantity of the sub-module by the transient process of the MMC after the fault, and defining the input quantity of the MMC relative to i_dcThe function K of the bridge arm unit is combined with the number of the sub-modules input by the bridge arm unit given by the valve controller to reduce U₀Thereby enabling the MMC to actively restrain short-circuit current;

the method is characterized in that:

s3 designing STAC controller

The control loop in the control strategy of the half-bridge type MMC adopts closed-loop control, the outer ring controller maintains the active power or alternating current and direct current voltage of the MMC at a set value, and the outer ring outputs a direct current reference value I_dcrefProviding input for inner loop control, and outputting DC voltage reference value U via proportional-integral control link_dcnCombined with a circulating current suppression controller to output a differential mode voltage V_diffParticipating in switching control of the sub-modules, and adopting nearest level approximation modulation in a modulation stage;

defined with respect to i_dcIs a piecewise function, t₀Time of occurrence of DC side fault, t_CGenerally setting 1-2 ms delay for the signal output time of fault detection 2, and also setting the mode selection switching time, t, of the current limiting controller_BFor the DC breaker DCCB breaking time, the formula is expressed as follows

When short-circuit fault occurs on the DC side, the DC current i_dcRapidly rises, the voltage of the fault line immediately falls, and at fault detection t₀＜t＜t_CStage when the current variation exceeds a set threshold di_thDt, fault detection 1 output current rate of change di_dc/dt, where λ (0)<λ<1) According to the requirements of the alternating-current side outlets of different converter stations and different operation condition settings, the output of the current limiting controller is switched from a steady-state value K-1 to K-1 (1-alpha i)_dc)×λdi_dcThe/dt is used for reducing the input proportion of the submodules to limit the short-circuit current;

after a short-circuit fault at the DC outlet i_dcRising substantially linearly for i obtained during the sampling period_dcThe current change rate di obtained by data set derivation_dcThe/dt meets the requirement of a current limiting controller to realize a preliminary limitA stream;

the 2 nd stage of current limiting is added, the voltage of the current limiting reactor can rise in a short time after the system has direct current fault, the system does not change in normal operation, and the voltage change dU of the current limiting inductor of the detection circuit is detected_LdcWhen the/dt exceeds a set threshold value, the STAC second-stage control is activated, the output of the switching current-limiting controller is K-1-beta (i)_max,set-i_dc) The submodule further reduces the throw ratio to further reduce and limit the fault current;

in order to take detection speed and anti-interference capability into consideration, the detection threshold value of the voltage change rate of the current-limiting inductor is 0.25, i_max,setFor a set maximum short-circuit current i to ensure that the MMC is not operated locked_max,setSelecting rated current I of 2 times_NNamely:

i_max,set＝2I_N (7)

s4, setting current limiter control parameters suitable for the converter stations under different operating conditions, and starting current limiting control according to the two sections of fault detection criteria and the preset maximum short-circuit current, so that the MMC valve controller reduces the proportion of the sub-modules to limit the fault current.

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