CN113035941B - Channel structure of GAAFET device and preparation method thereof - Google Patents
Channel structure of GAAFET device and preparation method thereof Download PDFInfo
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- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/66409—Unipolar field-effect transistors
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention discloses a channel structure of a GAAFET device and a preparation method thereof, belongs to the technical field of semiconductor processes, and can provide a device with higher integration level and better gate control. The channel structure comprises a silicon substrate, a channel layer, a plurality of silicon layers and a plurality of supporting layers, wherein the plurality of silicon layers are sequentially stacked on the silicon substrate, the supporting layers are arranged between the silicon substrate and the silicon layers and between two adjacent silicon layers, the channel layer is arranged on the surface of the silicon layers, the channel layer of a PMOS (P-channel metal oxide semiconductor) device is a single crystal SiGeSn layer, the improvement of hole mobility is facilitated by low-component Sn, the channel layer of the NMOS device is SiGe/Si which is sequentially extended on a released Si nanosheet, the concentration of Ge is less than or equal to 0.3, and the increase of electron mobility is facilitated by Si which is strained silicon. The preparation method comprises the following steps: providing a silicon substrate; forming a silicon layer and a support layer on a silicon substrate; a channel layer is formed on a surface of the silicon layer. The channel structure and the preparation method thereof can be used for GAAFET devices.
Description
Technical Field
The invention belongs to the technical field of semiconductor processes, and particularly relates to a channel structure of a GAAFET device and a preparation method thereof.
Background
As device dimensions shrink, the short channel effect problem becomes more pronounced. The SiGeSn channel can improve the driving current and reduce the static power consumption, but the SiGeSn epitaxial growth on Si has the problem of lattice mismatch, and meanwhile, the solid solubility of Sn in Ge is low, so that the problem that a single crystal material is difficult to obtain is solved.
In addition, the structure adopted by the channel of the existing PMOS device is a single-layer structure, the common channel material is single crystal Si, and the carrier mobility of the channel structure is low.
Disclosure of Invention
In view of the above analysis, the present invention aims to provide a channel structure of a GAAFET device and a preparation method thereof, so as to solve the problems that in the prior art, epitaxial SiGeSn on a silicon layer has lattice mismatch or Sn has low solid solubility in Ge, a single crystal material is difficult to obtain, and the channel carrier mobility of the PMOS device with the GAAFET structure is low.
The purpose of the invention is mainly realized by the following technical scheme:
the invention provides a channel structure of a GAAFET device, which comprises a silicon substrate, a channel layer, a plurality of silicon layers (Si layers) and a plurality of supporting layers, wherein the plurality of silicon layers are sequentially laminated on the silicon substrate, the supporting layers are arranged between the silicon substrate and the silicon layers and between two adjacent silicon layers, the channel layer is arranged on the surface (namely the upper surface, the lower surface and the side surface of the silicon layer) of the silicon layers, and the channel layer is a single crystal SiGeSn layer.
Furthermore, the content of Sn in the channel layer is 0.01wt.% to 20wt.%.
Furthermore, in the channel layer, the content of Sn is 0.01wt.% to 8wt.%.
Further, the support layer is a SiGe layer.
Furthermore, the content of Ge in the SiGe layer is 10-40 wt.%.
Further, the number of silicon layers may be 3 to 5.
Further, the width of the silicon layer is 10 to 100nm, and the ratio of the length to the width of the silicon layer is 1:1 to 10:1.
further, the thickness of the support layer is 10 to 30nm, and the thickness of the channel layer is 1 to 10nm.
The invention also provides a preparation method of the channel structure of the GAAFET device, which comprises the following steps:
providing a silicon substrate;
forming a silicon layer and a support layer on a silicon substrate;
and forming a channel layer on the surface of the silicon layer to finish the preparation of the channel structure of the GAAFET device.
Further, forming the silicon layer and the support layer on the silicon substrate includes the steps of:
forming a supporting layer to be processed and a silicon layer to be processed which are sequentially stacked on a silicon substrate;
vertically etching the support layer to be processed and the silicon layer to be processed to obtain a support layer to be released and a silicon layer which are sequentially and alternately stacked, wherein the widths of the support layer to be released and the silicon layer obtained after vertical etching influence the size of a channel in a channel structure of the final GAAFET device;
and carrying out partial release etching on the vertically etched support layer to be released to obtain the support layer.
Further, a dry etching method is adopted to perform HBr/O 2 And vertically etching the supporting layer to be processed and the silicon layer to be processed by etching gas.
Further, dry etching is adopted, and CF is adopted 4 /O 2 And performing partial release etching on the support layer to be processed after vertical etching by using the etching gas.
Further, after the silicon layer is obtained by vertically etching the support layer to be processed and the silicon layer to be processed, and before the support layer is obtained by partially releasing and etching the vertically etched support layer to be processed, the method further comprises the following steps:
depositing SiO on the surface of the silicon layer, the surface of the vertically etched support layer to be processed and the upper surface of the silicon substrate 2 A layer; to SiO 2 The layer is etched to SiO covering the silicon substrate 2 The upper surface of the layer or etching of SiO partially covering the silicon substrate 2 Layer for exposing the surface of the silicon layer and the vertically etched support layer to be processed, and SiO 2 The layer still covers the upper surface of the silicon substrate.
Further, the content of Sn in the channel layer is realized by adjusting the flow rates of the Ge source and the Sn source.
Further, the channel layer is a single crystal SiGeSn layer, and the process conditions of the selective epitaxy process are as follows:
the temperature of selective epitaxy is 250-400 ℃, the cavity pressure of selective epitaxy is 10-20Torr, snCl is added into the reaction chamber 4 And H 2 The flow rate of the mixed gas (Sn source) of (2) is 20-500sccm 4 、Ge 2 H 6 And H 2 The flow rate of the mixed gas (i.e., ge source) of (2) is 20to 1000sccm 4 、Si 2 H 6 Mixing of H 2 The flow rate of the mixed gas (namely Si source) is 5-30 sccm, the temperature of selective epitaxy is 300-700 ℃, the time of selective epitaxy is 20-240 s, and the selective epitaxy etching gas is HCl and/or Cl 2 。
Compared with the prior art, the invention can realize at least one of the following beneficial effects:
a) In the channel structure of the GAAFET device, the single crystal SiGeSn is used as the material of the channel layer of the PMOS device, and the single crystal SiGeSn layer has the characteristic of high mobility, so that the hole carrier mobility of the channel structure can be improved, and the comprehensive performance of the GAAFET device can be adjusted.
b) The channel structure of the GAAFET device provided by the invention is provided with the silicon nanosheet structure for forming the channel layer, the multiple layers of silicon layers are separated through the supporting layer to form partial suspended silicon layers, and channels are formed on the upper surface, the lower surface and the side surfaces of the silicon layers, so that the multiple layers of channel structures can be formed, and the overall hole carrier mobility of the channel structure of the GAAFET device and the comprehensive performance of the GAAFET device are further improved.
c) In the channel structure of the GAAFET device, the content of Sn in the channel layer is 0.01-20 wt%, and the carrier mobility of the channel structure of the GAAFET PMOS device can be remarkably improved by adjusting the content of Sn in the channel layer.
d) In the channel structure of the GAAFET device, the content of Sn in the channel layer is 0.01-8 wt%, the content of Sn is controlled within the range, strain can be introduced into the channel structure by adding the low-component Sn, so that the carrier mobility of the channel structure of the GAAFET PMOS device is improved, and meanwhile, the segregation and precipitation of Sn can be reduced by adding the low-component Sn, so that the failure of the GAAFET device caused by the addition of the high-component Sn is avoided.
e) In the channel structure of the GAAFET device, the supporting layer is a SiGe layer, the selection ratio of SiGe and Si is high, two materials with high selection ratio are selected in an etching process, and the preparation of the channel structure of the GAAFET device is facilitated.
f) In the channel structure of the GAAFET device, the width of the silicon layer is 10-100 nm, and the ratio of the length to the width is 1:1 to 10: the width and the length-width ratio of the silicon layer are limited in the range, the silicon layer is mainly set according to the use requirement, and the nanosheet of the silicon layer with the narrow width can have the characteristic of low power consumption.
g) According to the preparation method of the channel structure of the GAAFET device, the width of the silicon layer obtained after vertical etching influences the size of the channel in the channel structure of the final GAAFET device. Due to the high selection ratio of SiGe/Si, the morphology of the silicon layer can be kept to the maximum extent while the support layer to be processed is released.
h) In order to prevent the channel layer from being formed on the silicon substrate, the method for preparing the channel structure of the GAAFET device further comprises the following steps of, after the silicon layer is obtained by vertically etching the supporting layer to be processed and the silicon layer to be processed, and before the supporting layer to be processed after the vertical etching is partially released and etched to obtain the supporting layer: depositing SiO on the surface of the silicon layer, the surface of the support layer to be processed after vertical etching and the upper surface of the silicon substrate 2 A layer; to SiO 2 The layer is etched to SiO covering the silicon substrate 2 The upper surface of the layer or etching of SiO partially covering the silicon substrate 2 Layer for exposing the surface of the silicon layer and the vertically etched support layer to be processed, and SiO 2 The layer still covers the upper surface of the silicon substrate. Thus, by forming SiO for protecting the silicon substrate on the silicon substrate 2 Layer to effectively protect the silicon linerAnd a substrate such that the channel layer is formed only on the silicon layer and not on the silicon substrate.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The drawings are only for purposes of illustrating the particular invention and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout the figures.
Fig. 1 is a top view of a channel structure of a GAAFET device according to an embodiment of the present invention;
fig. 2 is a front cross-sectional view (Y-Y cross-sectional view) of a channel structure of a GAAFET device according to an embodiment of the present invention;
fig. 3 is a side sectional view (X-X sectional view) of a channel structure of a GAAFET device according to an embodiment of the present invention;
fig. 4 is a side sectional view (Z-Z sectional view) of a channel structure of a GAAFET device according to an embodiment of the present invention;
fig. 5 is a flowchart of a method for manufacturing a channel structure of a GAAFET device according to a second embodiment of the present invention.
Reference numerals:
1-a silicon substrate; 2-a silicon layer; 3-a support layer; 4-a channel layer; 5-a silicon layer to be treated; 6-a support layer to be treated; 7-SiO 2 A layer.
Detailed Description
The preferred invention will now be described in detail with reference to the accompanying drawings, which form a part hereof, and which together with the description serve to explain the principles of the invention.
Example one
The present embodiment provides a channel structure of a GAAFET device, and referring to fig. 1 to 4, the channel structure includes a silicon substrate 1, a channel layer 4, a plurality of silicon layers 2 (Si layers), and a plurality of support layers 3, where the plurality of silicon layers 2 are sequentially stacked on the silicon substrate 1, the support layers 3 are disposed between the silicon substrate 1 and the silicon layers 2 and between two adjacent silicon layers 2, the channel layer 4 is disposed on a surface of the silicon layer 2 (i.e., an upper surface, a lower surface, and a side surface of the silicon layer 2), that is, the surface of the silicon layer 2 includes a support layer contact surface and a non-support layer contact surface, and the channel layer 4 is disposed on the non-support layer contact surface of the silicon layer 2. The channel layer 4 is a single crystal SiGeSn layer.
Compared with the prior art, in the channel structure of the GAAFET device provided by the embodiment, the single crystal SiGeSn is used as the material of the channel layer 4, and the single crystal SiGeSn layer has high mobility, so that the overall hole carrier mobility of the channel structure of the PMOS device can be improved, and the comprehensive performance of the GAAFET device can be further adjusted.
Meanwhile, a silicon nanosheet structure for forming a channel layer is arranged in the channel structure of the GAAFET device, the multiple layers of silicon layers 2 are separated through the supporting layer 3 to form partial suspended silicon layers 2, and channels are formed on the upper surface, the lower surface and the side surfaces of the silicon layers 2, so that the multiple layers of channel structures can be formed, and the overall hole carrier mobility of the channel structure of the GAAFET device and the comprehensive performance of the GAAFET device are further improved.
It is noted that, in the channel layer 4, the content of Sn may affect the carrier mobility of the channel structure of the GAAFET device, and for example, the content of Sn in the channel layer 4 is 0.01wt.% to 20wt.%, because the content of Sn in the channel layer 4 is adjusted to facilitate the improvement of the hole mobility of the PMOS device, so that the carrier mobility of the channel structure of the GAAFET device can be significantly improved.
In order to avoid the influence of high-composition Sn on the channel structure of the GAAFET device, the content of Sn in the channel layer 4 is 0.01wt.% to 8wt.%. The reason is that, by controlling the content of Sn within the above range, the addition of Sn can introduce strain into the channel structure, thereby improving the carrier mobility of the channel structure of the GAAFET device, and at the same time, the addition of low-component Sn can also reduce segregation and precipitation of Sn, thereby avoiding failure of the GAAFET device due to the addition of high-component Sn.
In practical applications, in order to facilitate the formation of the silicon layer 2 and the preparation of the channel structure of the GAAFET device, the support layer 3 is a SiGe layer, because the selection ratio of SiGe and Si is high, and two materials with high selection ratio are selected in the etching process, which is more beneficial to the preparation of the channel structure of the GAAFET device.
In order to further control the selection ratio of the two materials (SiGe and Si), the content of Ge in the SiGe layer is 10wt.% to 40wt.%.
The number of layers of the silicon layer 2 may be 3 to 5 from the viewpoint of improvement of carrier mobility and simplification of the structure. However, it should be noted that the number of layers of the silicon layer 2 in the channel structure of the GAAFET device is not limited to 3 to 5, and in practical applications, the number may be appropriately adjusted according to different process conditions and requirements of the GAAFET device, and details thereof are not repeated herein.
Considering that the channel layer 4 is directly formed on the surface of the silicon layer 2, and therefore, the width of the silicon layer 2 directly affects the carrier mobility of the channel structure of the GAAFET device, illustratively, the width of the silicon layer 2 is 10 to 100nm, and the ratio of the length to the width is 1:1 to 10:1. this is because the width and the ratio of the length to the width of the silicon layer 2 are limited to the above ranges, and are set mainly according to the use requirements, and a nanosheet using a silicon layer 2 having a narrow width can have a low power consumption characteristic.
In order to further improve the overall performance of the channel structure of the GAAFET device, the thickness of the support layer 3 is 10 to 30nm, and the thickness of the channel layer 4 is 1 to 10nm. In this way, by setting appropriate thicknesses of the support layer 3 and the channel layer 4, the overall performance of the channel structure of the GAAFET device can be further improved.
Example two
The embodiment provides a method for preparing a channel structure of a GAAFET device, and referring to fig. 5, the method includes the following steps:
providing a silicon substrate 1;
forming a silicon layer 2 and a support layer 3 on a silicon substrate 1;
and forming a channel layer 4 on the surface of the silicon layer 2 to finish the preparation of the channel structure of the GAAFET device.
Compared with the prior art, the beneficial effects of the method for preparing the channel structure of the GAAFET device provided in this embodiment are substantially the same as those of the channel structure of the GAAFET device provided in the first embodiment, and are not repeated herein.
Specifically, forming the silicon layer 2 and the support layer 3 on the silicon substrate 1 includes the steps of:
forming a supporting layer 6 to be processed and a silicon layer 5 to be processed which are sequentially stacked on the silicon substrate 1;
adopting a dry etching mode and adopting HBr/O 2 The support layer 6 to be processed and the silicon layer 5 to be processed are vertically etched as etching gas, so that anisotropic corrosion of the support layer 6 to be processed and the silicon layer 5 to be processed is realized, a pattern after etching can have steep side walls, and the support layer to be released and the silicon layer 2 which are sequentially and alternately laminated are obtained;
by dry etching, with CF 4 /O 2 And performing partial release etching on the vertically etched support layer to be released as etching gas, and selectively etching the support layer to be released to obtain the support layer 3.
It should be noted that the width of the silicon layer 2 obtained after the vertical etching affects the size of the channel in the channel structure of the final GAAFET device.
It should also be noted that, due to the high selectivity of SiGe/Si, the topography of the silicon layer 2 is preserved to the greatest extent while the support layer 6 to be treated is released.
In order to avoid the channel layer 4 from being formed on the silicon substrate 1, the method further includes, for example, after the silicon layer 2 is obtained by vertically etching the support layer 6 to be processed and the silicon layer 5 to be processed, and before the support layer 3 is obtained by partially releasing and etching the support layer 6 to be processed after vertical etching, the method further includes the following steps:
SiO is deposited on the surface of the silicon layer 2, the surface of the support layer 6 to be processed after vertical etching and the upper surface of the silicon substrate 1 2 A layer 7; to SiO 2 The layer 7 is etched to SiO covering the silicon substrate 1 2 The upper surface of layer 7 or etching of SiO partially covering the silicon substrate 1 2 A layer 7 of SiO exposing the surface of the silicon layer 2 and the vertically etched support layer 6 to be processed 2 Layer 7 still covers the upper surface of silicon substrate 1.
Thus, by forming SiO on the silicon substrate 1 2 Layer 7, which is capable of effectively protecting silicon substrate 1, so that channel layer 4 is formed only on silicon layer 2 and is not formed on silicon substrate 1.
It is noted that the Sn content in the channel layer 4 affects the carrier mobility of the channel structure of the GAAFET device, and the Sn content in the channel layer 4 can be implemented by adjusting the flow rates of the Ge source and the Sn source.
In order to make the content of Sn in the channel layer 4 be 0.01wt.% to 20wt.%, for example, when the channel layer 4 is a single crystal SiGeSn layer, the process conditions of the above selective epitaxial process are as follows:
the temperature of selective epitaxy is 250-400 ℃, the cavity pressure of selective epitaxy is 10-20Torr, snCl is added into the reaction chamber 4 And H 2 The flow rate of the mixed gas (i.e., sn source) of (1) is 20to 500sccm 4 、Ge 2 H 6 And H 2 The flow rate of the mixed gas (i.e., ge source) of (2) is 20to 1000sccm 4 ，Si 2 H 6 Mixing of H 2 The flow rate of the mixed gas (namely the Si source) is 5 to 30sccm, the temperature of selective epitaxy is 300 to 700 ℃, the time of selective epitaxy is 20to 240s, and the etching gas of selective epitaxy is HCl and/or Cl 2 。
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (6)
1. A channel structure of a GAAFET device is characterized by comprising a silicon substrate, a channel layer, a plurality of layers of silicon layers and a plurality of layers of supporting layers, wherein the plurality of layers of silicon layers are sequentially stacked on the silicon substrate, and the supporting layers are arranged between the silicon substrate and the silicon layers and between two adjacent layers of silicon layers;
the channel layer is arranged on the surface of the silicon layer;
the channel layer is a single crystal SiGeSn layer;
the surface of the silicon layer comprises a supporting layer contact surface and a non-supporting layer contact surface, and a channel layer is arranged on the non-supporting layer contact surface of the silicon layer;
the supporting layer separates the multiple layers of silicon layers to form partial suspended silicon layers;
the supporting layer is a SiGe layer, and the content of Ge in the SiGe layer is 10-40 wt.%.
2. The channel structure of the GAAFET device of claim 1, wherein the content of Sn in the channel layer is 0.01wt.% to 20wt.%.
3. The channel structure of a GAAFET device according to claim 1 or 2, wherein the width of the silicon layer is 10 to 100nm, and the ratio of the length to the width of the silicon layer is 1:1 to 10:1.
4. a method for fabricating a channel structure of a GAAFET device, for fabricating a channel structure of a GAAFET device according to any of claims 1 to 3, the method comprising the steps of:
providing a silicon substrate;
forming a silicon layer and a support layer on a silicon substrate;
forming a channel layer on the surface of the silicon layer to finish the preparation of a channel structure of the GAAFET device;
the forming of the silicon layer and the support layer on the silicon substrate comprises the steps of:
forming a supporting layer to be processed and a silicon layer to be processed which are sequentially stacked on a silicon substrate;
vertically etching the support layer to be treated and the silicon layer to be treated to obtain a support layer to be released and a silicon layer which are sequentially and alternately laminated;
performing partial release etching on the vertically etched support layer to be released to obtain a support layer;
after the silicon layer is obtained by vertically etching the support layer to be processed and the silicon layer to be processed, and before the support layer to be processed after vertical etching is partially released and etched to obtain the support layer, the method further comprises the following steps:
depositing SiO on the surface of the silicon layer, the surface of the vertically etched support layer to be processed and the upper surface of the silicon substrate 2 A layer; to SiO 2 The layer is etched to SiO covering the silicon substrate 2 The upper surface of the layer or etching of SiO partially covering the silicon substrate 2 Layer for exposing the surface of the silicon layer and the vertically etched support layer to be processed, and SiO 2 The layer still covers the upper surface of the silicon substrate.
5. The method of claim 4, wherein the forming the channel layer on the surface of the silicon layer is performed by a selective epitaxy process.
6. The method of claim 5, wherein the channel layer is a single-crystal SiGeSn layer, and the selective epitaxy process has the following process conditions:
the epitaxial temperature is 250-400 ℃, the epitaxial cavity pressure is 10-20Torr, snCl 4 And H 2 The flow rate of the mixed gas is 20-500sccm 4 、Ge 2 H 6 And H 2 The flow rate of the mixed gas is 20-1000sccm 4 ，Si 2 H 6 Mixing of H 2 The flow rate of the mixed gas is 5-30 sccm, the epitaxial time is 20-240 s, and the selective epitaxial etching gas is HCl and/or Cl 2 。
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