CN113032312B - Multi-chip circuit cascade communication system - Google Patents

Multi-chip circuit cascade communication system Download PDF

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CN113032312B
CN113032312B CN201911346919.5A CN201911346919A CN113032312B CN 113032312 B CN113032312 B CN 113032312B CN 201911346919 A CN201911346919 A CN 201911346919A CN 113032312 B CN113032312 B CN 113032312B
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chip
signal
serial
daisy chain
sub
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CN113032312A (en
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邓军
唐枋
刘凡
雷昕
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CETC 24 Research Institute
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CETC 24 Research Institute
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a multi-chip circuit cascade communication system, wherein multi-level sub-level chips of the multi-chip circuit cascade communication system are connected in a daisy chain mode, a cascade communication interface of each sub-level chip comprises a configurable daisy chain circuit structure compatible with an SPI (serial peripheral interface), and by combining a universal SPI (serial peripheral interface) communication interface and the daisy chain structure, under the condition of the same SPI communication interface pin resource, cascade communication between a main control chip and the multi-level sub-level circuit chips can be realized, the main control chip can carry out register writing and register reading operations of all registers on each cascaded sub-level circuit chip, carry out register writing and reading operations of different addresses on each cascaded sub-level circuit chip, selectively bypass the sub-level circuit chips and other accurate point-to-point and point-to-multiple operations, realize the accurate management and control of the main control chip on the cascaded sub-level circuit chips, and effectively solve the problems of single function, low cost and high efficiency of the cascade communication system in the existing multi-chip cascade communication system, Can not be applied to the occasions with complex requirements.

Description

Multi-chip circuit cascade communication system
Technical Field
The invention relates to the technical field of signal processing and communication, in particular to a multi-chip circuit cascade communication system.
Background
With the development of technology, the functions of electronic systems facing the application market are increasing, the number of integrated circuits integrated on the systems is increasing, and even in some electronic systems, the same integrated circuits are integrated into a plurality of circuits for realizing complex multi-channel processing. This results in a multiplied demand for the same signal pin wiring resources, which places a heavy pin resource burden on the processor performing the final signal processing. For example, an electronic system needs to integrate an ADC circuit, the SPI-based communication interface needs to have a minimum of 4 (SCLK, CSN, SDI, SDO) pin resources, if the system functions are expanded and 10 identical ADC circuits need to be integrated, 40 pin resources are needed, and the pin resource requirement increases by 36, which is undoubtedly a very heavy burden for the pin resources of the electronic system, and even a processor (DSP or FPGA, etc.) with more pin resources may be modified to meet the sufficient pin resource requirement, which may cause the risk of modifying the design and increase the cost.
Currently, to solve the above problem, several manufacturers in the industry have introduced SPI interfaces supporting daisy chain mode to solve the multi-chip cascade problem. For example, the AD7690 product of the american ADI company, whose SPI interface includes CNV, SCK, SDI, and SDO four signals, as shown in fig. 1, the proposed cascade solution is to cascade the preceding stage output SDO and the following stage input SDI by sharing the enable signal CNV and the clock signal SCK, and in case of sufficient driving capability, only three signal interfaces are provided for the following stage signal processor no matter how many pieces of AD7690 are cascaded, thereby greatly saving the pin resources of the signal processor.
However, the above solutions and other similar cascading solutions all only sequentially and serially shift output data in the monolithic integrated circuit in a shifting manner through interface signals (CNV, SCK, SDI and SDO), namely, read data; however, when complex operations such as writing configuration information to a plurality of registers in a monolithic integrated circuit, reading register values to check, and selectively bypassing a certain cascade circuit during cascading are required, the scheme cannot be satisfied, that is, the scheme has a single function and cannot be applied to complex occasions.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a multi-chip circuit cascade communication system including a configurable daisy-chain circuit structure with compatible SPI interfaces, which solves the above-mentioned technical problems.
In order to achieve the above and other related objects, the present invention provides a multi-chip circuit cascade communication system, which includes a main control chip and a plurality of sub-chips, wherein the plurality of sub-chips are cascaded with the main control chip, and the plurality of sub-chips are connected in a daisy chain manner;
the serial clock output by the main control chip is connected with the clock input ends of all the sub-level chips, the chip selection signal output by the main control chip is connected with the chip selection input ends of all the sub-level chips, and the loading control signal output by the main control chip is connected with the loading control input ends of all the sub-level chips;
the serial output end of the main control chip is connected with the serial input end of the first-stage sub-stage chip; except the first-stage sublevel chip, the serial input ends of other sublevel chips are connected with the serial output end of the preceding-stage sublevel chip; the serial output end of the last-stage sub-stage chip is connected with the serial input end of the main control chip;
the cascade communication interface of each stage of the substage chip comprises a configurable daisy chain circuit structure compatible with the SPI interface.
Optionally, a bypass input end of each stage of the sub-stage chip is floating, the bypass input end of each stage of the sub-stage chip is in a pull-down design, and the bypass input end is in a low level in a floating state.
Optionally, the SPI interface compatible configurable daisy chain circuit structure includes:
the universal SPI communication interface is respectively connected with the chip selection signal, the serial clock input signal, the serial input signal and the reset input signal and receives serial data input in a common serial communication mode;
the daisy chain interface based on the SPI is respectively connected with the chip selection signal, the serial clock input signal, the serial input signal and the reset input signal and receives serial data input in a daisy chain communication mode;
the serial output signal selection module is connected with the serial input signal, the universal SPI communication interface and the SPI-based daisy chain interface and is used for selectively outputting the serial input signal, the serial output signal of the universal SPI communication interface and the serial output signal of the SPI-based daisy chain interface;
and the data register output selection module is connected with the universal SPI communication interface and the daisy chain interface based on the SPI, selects and outputs register data output signals of the universal SPI communication interface and register data output signals of the daisy chain interface based on the SPI, and the output end of the data register output selection module is connected with the control register group of each stage of the sublevel chip.
Optionally, the serial output signal selection module includes:
a first selector, which is respectively connected with the universal SPI communication interface, the daisy chain interface based on the SPI and the enabling control signal of the daisy chain mode, and selectively outputs the serial output signal of the universal SPI communication interface and the serial output signal of the daisy chain interface based on the SPI under the control of the enabling control signal of the daisy chain mode;
the second selector is respectively connected with the output of the first selector, the serial input signal and the bypass input signal, and selectively outputs the serial input signal and the output of the first selector under the control of the bypass signal;
wherein the output signal of the second selector is used as the serial output signal of each stage of the sub-stage chip.
Optionally, the data registering and outputting selection module includes:
the input end of the inverter is connected with the chip selection signal and logically inverts the chip selection signal;
the input end of the first AND gate is respectively connected with the universal SPI communication interface and the output end of the phase inverter;
and the first and gate generates an enable signal when the first data register group latches data, and latches the parallel data output by the universal SPI communication interface at the rising edge of the last serial clock.
Optionally, the data registering and outputting selection module further includes:
the D trigger is provided with a reset end and is respectively connected with the serial clock input signal and the reset input signal to generate an enabling control signal of the daisy chain mode;
the third selector is respectively connected with the D trigger and the chip selection signal and is used for selectively outputting the Q end and the Qn end of the D trigger under the control of the chip selection signal;
the input end of the second AND gate is respectively connected with the daisy chain interface based on the SPI, the chip selection signal and the input end of the third selector;
and the second data register group is respectively connected with the SPI-based daisy chain interface, the output end of the second AND gate and the loading control signal, the second AND gate generates an enable signal when the second data register group latches data, and the shift storage value of the SPI-based daisy chain interface in the second data register group is latched on the rising edge of the loading control signal.
Optionally, the data registering and outputting selection module further includes:
and the fourth selector is respectively connected with the first data register group, the second data register group and the daisy chain mode enable control signal, and is used for selectively outputting the register data of the first data register group and the register data of the second data register group under the control of the daisy chain mode enable control signal.
Optionally, the first and gate includes a two-input and gate, the second and gate includes a three-input and gate, and the first selector, the second selector, the third selector, and the fourth selector include an one-out-of-two selector.
Optionally, during a high level period of the chip select signal, two falling edges occurring in succession in the serial clock input signal constitute a pair of trigger signals, so that the enable control signal in the daisy chain mode generates a high level pulse, and a corresponding pulse width is determined by an interval between the two falling edges.
Optionally, when the bypass input signal is at a low level, the sub-chips are in a daisy chain operation mode; when the bypass input signal is at a high level, the daisy chain working mode of the sublevel chip is bypassed, and the serial clock input signal received by the sublevel chip through the serial interface is directly transmitted to the serial output port of the sublevel chip.
As described above, the multi-chip circuit cascade communication system of the present invention has the following advantageous effects:
the multi-level sub-level chips are connected in a daisy chain mode, the cascade communication interface of each level of sub-level chip comprises a configurable daisy chain circuit structure compatible with the SPI, and one main control chip can realize cascade communication with a plurality of sub-level circuit chips under the condition of the same SPI communication interface pin resource by combining a universal SPI communication interface and the daisy chain structure; the main control chip can perform register writing and reading operations of all registers on each cascaded sub-level circuit chip, can perform register writing and reading operations of different addresses on each cascaded sub-level circuit chip at the same time, and can selectively bypass the sub-level circuit chips; in addition, under the condition that pin resources are not additionally increased, the circuit structure can enable the main control chip to carry out accurate point-to-point and point-to-multipoint operations on the cascaded sub-level circuit chips, so that accurate management and control of the main control chip on the cascaded sub-level circuit chips are realized, and the circuit chip with the communication interface can be applied to occasions with complex requirements.
Drawings
Fig. 1 shows a daisy chain cascade connection structure of AD7690 products by ADI corporation of usa.
Fig. 2 shows a daisy chain cascade connection structure of a multi-chip circuit cascade communication system according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of a preferred embodiment of a configurable daisy-chain circuit structure compatible with SPI interface of a multi-chip cascade communication system according to the present invention.
FIG. 4 is a timing diagram of the serial interface communication at the input end according to an embodiment of the present invention.
Fig. 5 is a schematic diagram illustrating a structure of transmitting command data by a main control chip applied in a multi-chip circuit cascade communication system according to an embodiment of the present invention.
FIG. 6 is a timing diagram illustrating a preferred embodiment of a process of generating a control signal DCM _ EN in a daisy-chain mode in a multichip cascade communication system according to an embodiment of the invention.
FIG. 7 is a timing diagram illustrating a preferred embodiment of a write register operation process in a daisy chain mode in a multi-chip cascade communication system according to the present invention.
FIG. 8 is a timing diagram illustrating a preferred embodiment of a read register operation process in a daisy chain mode in a multi-chip cascade communication system according to the present invention.
Fig. 9 is a timing diagram illustrating a preferred embodiment of the operation process of bypassing the sub-stage circuits in the daisy chain mode in the implementation method of the multi-chip circuit cascade communication system according to the present invention.
Detailed Description
The inventor researches and discovers that the existing cascading solutions only sequentially and serially shift and output (namely read data) output data in a monolithic integrated circuit in a shifting mode through interface signals (CNV, SCK, SDI and SDO), but when complex operations such as writing configuration information and reading register values to check a plurality of registers in the monolithic integrated circuit and selectively bypassing a certain cascading circuit during cascading are needed, the solutions cannot meet the requirements, namely the solutions are single in function and cannot be applied to complex occasions.
Based on this, the invention provides a multi-chip circuit cascade communication system with a configurable daisy chain circuit structure including compatible SPI interfaces, wherein, the multi-level sub-level chips of the multi-chip circuit cascade communication system are connected in a daisy chain way, the cascade communication interface of each sub-level chip includes a configurable daisy chain circuit structure compatible with SPI interfaces, by combining a universal SPI communication interface and the daisy chain structure, under the condition of the same SPI communication interface pin resource, the cascade communication between a main control chip and the multi-level sub-level circuit chips can be realized, the main control chip can carry out register writing and register reading operations of all registers to each cascaded sub-level circuit chip, and the main control chip can simultaneously carry out register writing and reading operations of different addresses to each cascaded sub-level circuit chip, and the circuit structure can lead the main control chip to carry out precise point-to-point and multi-point operations to the cascaded sub-level circuit chips, the accurate management and control of the main control chip on the cascaded sub-stage circuit chip are realized, so that the circuit chip with the communication interface can be applied to occasions with complex requirements.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. The structures, proportions, sizes, and other dimensions shown in the drawings and described in the specification are for understanding and reading the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined in the claims, and are not essential to the art, and any structural modifications, changes in proportions, or adjustments in size, which do not affect the efficacy and attainment of the same are intended to fall within the scope of the present disclosure.
As shown in fig. 2, the present invention provides a multi-chip circuit cascade communication system, which includes a main control chip and a multi-level sub-level chip, wherein the multi-level sub-level chip and the main control chip are cascaded, and the multi-level sub-level chips are connected with each other in a daisy chain manner;
the serial clock signal SCK output by the main control chip is connected with the clock input ends of all the sub-level chips, the chip selection signal SEN output by the main control chip is connected with the chip selection input ends of all the sub-level chips, and the loading control signal LOAD output by the main control chip is connected with the loading control input ends of all the sub-level chips;
the serial output end of the main control chip is connected with the serial input end of the first-stage sublevel chip; except the first-stage sublevel chip, the serial input ends of other sublevel chips are connected with the serial output end of the preceding-stage sublevel chip; the serial output end of the last-stage sub-stage chip is connected with the serial input end of the main control chip;
the cascade communication interface of each stage of the substage chip comprises a configurable daisy chain circuit structure compatible with the SPI interface.
Optionally, as shown in fig. 2, the bypass input terminal of each stage of the sub-stage chip is floating, the bypass input terminal of each stage of the sub-stage chip is in a pull-down design, and the bypass input terminal is at a low level in a floating state.
Optionally, the multi-chip circuit cascade communication system as shown in fig. 2 includes a 4-stage sub-stage chip; the multi-chip circuit cascade communication system shown in fig. 6 includes L-stage sub-chips.
Optionally, as shown in fig. 3, the SPI interface compatible configurable daisy chain circuit structure includes:
the universal SPI communication interface is respectively connected with a chip select signal SEN, a serial clock input signal SCLK, a serial input signal SDI and a reset input signal RST, and receives serial data input in a common serial communication mode;
the daisy chain interface based on the SPI is respectively connected with a chip select signal SEN, a serial clock input signal SCLK, a serial input signal SDI and a reset input signal RST and receives serial data input in a daisy chain communication mode;
the serial output signal selection module is connected with the serial input signal SDI, the universal SPI communication interface and the SPI-based daisy chain interface and is used for selectively outputting the serial input signal SDI, the serial output signal SDO _ SPI of the universal SPI communication interface and the serial output signal SDO _ DCM of the SPI-based daisy chain interface;
and the data register output selection module is connected with the universal SPI communication interface and the daisy chain interface based on the SPI, selects and outputs register data output signals of the universal SPI communication interface and register data output signals of the daisy chain interface based on the SPI, and the output end of the data register output selection module is connected with the control register group of each stage of the sublevel chip.
The general SPI communication interface is a general SPI communication interface, and the structure thereof can refer to the prior art and is not described herein again.
In detail, as shown in fig. 3, the serial output signal selection module includes:
a first selector MUX1, respectively connected to the general SPI communication interface, the daisy chain interface based on the SPI, and the enable control signal DCM _ EN in the daisy chain mode, for selectively outputting the serial output signal SDO _ SPI of the general SPI communication interface and the serial output signal SDO _ DCM based on the daisy chain interface based on the SPI under the control of the enable control signal DCM _ EN in the daisy chain mode, and outputting the serial output signal SDO _ T at an output end thereof;
a second selector MUX2, which is respectively connected to the output of the first selector MUX1, the serial input signal SDI, and the BYPASS input signal BYPASS, and under the control of the BYPASS signal BYPASS, selectively outputs the serial input signal SDI and the output SDO _ T of the first selector MUX 1;
wherein, the output signal of the second selector MUX2 is used as the serial output signal SDO of each stage of the sub-stage chip.
In detail, as shown in fig. 3, the data register output selection module includes:
an inverter INV1, the input end of which is connected with the chip select signal SEN and logically inverts the chip select signal SEN;
the input end of the first AND gate AND2x1 is connected with the general SPI communication interface AND the output end of the inverter INV1, respectively, AND the first AND gate AND2x1 perform AND operation on the inverted signals of the signal M/R _ SPI AND the chip select signal SEN output by the general SPI communication interface, AND obtain an enable signal EN1 at the output end of the first AND gate AND2x 1;
AND the first data register group is respectively connected with the universal SPI communication interface, the output end of the first AND gate AND2x1 AND the serial clock input signal SCLK, the first AND gate AND2x1 generates an enable signal EN1 when the first data register group latches data, latches parallel data output by the universal SPI communication interface at the rising edge of the last serial clock, receives an address signal ADDR _ SPI [ N-m-1] AND a serial output signal SPI _ D [ m-1:0] output by the universal SPI communication interface AND outputs a registered data signal data _ SPI [ m-1:0 ].
The first data register group is an m-bit data register group, and m is a positive integer such as 8, 16, etc.
In detail, as shown in fig. 3, the data register output selection module further includes:
the D trigger DFFR1 is provided with a reset end and is respectively connected with the serial clock input signal SCLK and the reset input signal RST, the serial clock input signal SCLK is connected with the CK end, the reset input signal RST is connected with the R end, and the enable control signal DCM _ EN in a daisy chain mode is generated at the output end Q end;
the third selector MUX3 is respectively connected with the D flip-flop DFFR1 and the chip selection signal SEN, two input ends of the third selector MUX3 are respectively connected with the Q end and the Qn end of the output end of the D flip-flop DFFR1, the control end of the third selector MUX3 is connected with the chip selection signal SEN, the output end of the third selector MUX3 is connected with the D end of the input end of the D flip-flop DFFR1, and the Q end and the Qn end of the D flip-flop DFFR1 are selectively output under the control of the chip selection signal SEN;
a second AND gate AND3x1, the input terminals of which are connected to the input terminals of the SPI-based daisy chain interface, the chip select signal SEN, AND the third selector MUX3, respectively, AND which performs an AND operation on the signal DCM _ M/R, the chip select signal SEN, AND the daisy chain mode enable control signal DCM _ EN outputted from the SPI-based daisy chain interface, AND outputs an enable signal EN2 at the output terminal thereof;
AND the second data register group is respectively connected with the SPI-based daisy chain interface, the output end of the second AND gate AND3x1 AND the LOAD control signal LOAD, the second AND gate AND3x1 generates an enable signal EN2 when the second data register group latches data, latches the shift storage value of the SPI-based daisy chain interface in the second data register group at the rising edge of the LOAD control signal LOAD, receives the address signal DCM _ ADDR [ N-m-1] AND the serial output signal DCM _ D [ m-1:0] output by the universal SPI communication interface AND outputs a registered data signal data _ DCM [ m-1:0 ].
The second data register group is also an m-bit data register group.
In detail, as shown in fig. 3, the data register output selection module further includes:
and the fourth selector MUX group 1 is respectively connected with the first Data register group, the second Data register group and the daisy chain mode enable control signal DCM _ EN, selectively outputs the register Data signal Data _ SPI [ m-1:0] of the first Data register group and the register Data signal Data _ DCM [ m-1:0] of the second Data register group under the control of the daisy chain mode enable control signal DCM _ EN, outputs the Data signal Data [ m-1:0] at the output end of the fourth selector MUX group, and the output end of the fourth selector MUX group is connected with the control register group of each stage of the sub-stage chip.
Optionally, as shown in fig. 3, the first AND gate AND2x1 includes a two-input AND gate, the second AND gate AND3x1 includes a three-input AND gate, AND the first selector MUX1, the second selector MUX2, the third selector MUX3, AND the fourth selector MUX group 1 include a one-out-of-two selector.
In one embodiment of the present invention, the signal timing of the serial input ports of the SPI communication interface and the SPI-based daisy-chain interface in the multi-chip circuit cascade communication system is shown in fig. 4.
In detail, the operation principle of the above-mentioned configurable daisy chain circuit structure compatible with the SPI interface will be briefly described below.
In more detail, when the configurable daisy chain circuit structure compatible with the SPI interface is in the general SPI communication mode, at this time, for writing register operation, serial input data outside each stage of the sub-stage chip will be received in the general SPI communication interface, and if the received command W/R is 0, at the time of receiving the falling edge of the last clock of the serial clock input signal SCLK, the serially received data is stored in the register corresponding to the received address ADDR in the first data register group and is simultaneously output to the outside of the chip under the control of the received command W/R, the address signal ADDR _ SPI [ N-m-1] and the serial communication chip select signal SEN; when the operation is to read the register, the serial input data outside each level of the sub-level chip is received in the universal SPI communication interface, and if the received command W/R is equal to 1, after the address ADDR information is received, the data stored in the register corresponding to the address is read into the serial receiving register according to the received command W/R and the address signal ADDR _ SPI [ N-m-1] at the rising edge of the first clock of the serial clock input signal SCLK, and is output through the serial output port SDO _ SPI, and finally is output to the off-chip SDO port under the control of the daisy chain mode enable control signal DCM _ EN and the BYPASS input signal BYPASS.
In more detail, as shown in fig. 5, the generation process of the daisy-chain mode enable control signal DCM _ EN is as follows:
a. when the externally input reset signal RST is effectively reset at a high level, the Q end outputs a low level, namely the level of the D trigger DFFR1 No. DCM _ EN is a low level after reset;
b. when the input chip select signal SEN is at a high level, the third selector MUX3 selects the Qn terminal output of the D flip-flop DFFR1 as the data input of the D terminal of the D flip-flop DFFR 1; during the period of keeping the chip select signal SEN at high level, when the serial input clock signal SCLK first appears falling edge, the D end input data is collected by the trigger D flip-flop DFFR1, and the D end input data is connected with the Qn end of the D flip-flop DFFR1 at this time, namely, during the period of high level of the chip select signal SEN, when the serial input clock signal SCLK falls edge, the Q end output of the D flip-flop DFFR1 is inverted, and is changed from the reset low level to the high level, namely, the enable control signal DCM _ EN of the daisy chain mode is at high level;
c. when the input chip select signal SEN changes from high level to low level, the third selector MUX3 selects the Q terminal of the D flip-flop DFFR1 to output as the data input of the D terminal of the D flip-flop DFFR1, when several falling edge signals occur to the serial input clock signal SCLK while maintaining the chip select signal SEN at low level, the D flip-flop DFFR1 will be triggered to collect the D terminal input data, and the D terminal input data is always connected to the Q terminal of the D flip-flop DFFR1, that is, when the falling edge of the serial input clock signal SCLK triggers during the low level of the chip select signal SEN, the Q terminal of the D flip-flop DFFR1 will keep the high level output value unchanged, that is, the enable control signal DCM _ EN in daisy chain mode keeps the high level unchanged;
d. when the serial input clock signal SCLK is again in the falling edge signal during the period when the input chip select signal SEN is restored from the low level to the high level, the D-side flip-flop DFFR1 is triggered to acquire D-side input data, and the D-side input data is connected with the Qn side of the D-side flip-flop DFFR1 at the moment, namely when the serial input clock signal SCLK is triggered again in the falling edge signal during the high level period of the chip select signal SEN, the Q side output of the D-side flip-flop DFFR1 is inverted, the high level maintained by the Q side is converted into the low level, namely the enable control signal DCM _ EN in the daisy chain mode is converted into the low level;
e. during the high level period of the chip select signal SEN, the enable control signal DCM _ EN in the daisy chain mode repeatedly switches between the high level and the low level as the falling edge signal of the serial input clock signal SCLK continues to appear, i.e., during the high level period of the chip select signal SEN, two falling edges of the serial input clock signal SCLK appearing consecutively constitute a pair of trigger signals, so that the enable control signal DCM _ EN in the daisy chain mode generates one high level pulse, and the pulse width is determined by the interval between the two corresponding falling edges.
As shown in fig. 5, when the chip select signal SEN is maintained at the high level and the first falling edge of the serial input clock signal SCLK, the enable control signal DCM _ EN of the daisy chain mode changes from the low level to the high level (the enable control signal DCM _ EN of the daisy chain mode is asserted at the high level), and the circuit enters the daisy chain mode; when the chip select signal SEN is maintained at the high level and the second falling edge of the serial input clock signal SCLK occurs, the enable control signal DCM _ EN in the daisy chain mode changes from the high level to the low level, the circuit ends the daisy chain mode, and returns to the normal SPI mode; the daisy chain mode enable control signal DCM _ EN is a signal generated inside the circuit, and does not occupy the pin resources of the port.
In more detail, as shown in fig. 6 and 7, when the configurable daisy chain circuit structure compatible with the SPI interface is in the SPI-based daisy chain mode for communication, the principle of the corresponding write register operation is as follows:
a' as shown in fig. 6, for a multi-chip circuit cascade communication system including an L-level sub-level chip, a main control chip is required to send L write register operation commands during the write register operation, the write register commands have N bits in total and are composed of a one-bit read-write command R/W, N-m-1 bit register addressing address ADDR and data of an m-bit configuration register; when the master control chip operates the write register of the cascaded L-level sub-level chips, the N-bit write command data of each level of sub-level chips in the L-level sub-level chips needs to be configured in the master control chip, namely the write command R/W is '0', an N-m-1 bit register addressing address ADDR is a register address which needs to be configured corresponding to the sub-level chip, and the data of the m-bit configuration register is the data which needs to be configured by the register pointed by the address ADDR;
b', serial writing command data from the falling edge of the chip select signal SEN and shift transmission, after the chip select signal SEN enters a low level state, as shown in FIG. 6 and FIG. 7, the main control chip starts to serially transmit write command data to the first-stage cascade sub-stage chips through the serial output port and shift-stores the write command data in the registers of the N-bit shift registers of the first-stage cascade sub-stage chips, after the first N-bit write command data is completely transmitted, the N-bit shift registers in the first sub-stage sequentially store the N-bit write command data, and when the main control chip transmits the first bit data R/W of the second N-bit write command data, the N-bit shift registers in the first sub-stage shift to receive the bit data, and simultaneously, the registers N of the N-bit shift registers in the first sub-stage shift registers shift-output the first bit data R/W of the first N-bit write command data to the registers of the N-bit registers in the second sub-stage chip, continuing the above steps, after the L N-bit write command data are sent, the L N-bit write command data are respectively and correspondingly stored in the N-bit shift registers of the sub-chips;
c', resetting the LOAD control signal LOAD signal to be a low level by the main control chip during resetting, setting the LOAD control signal LOAD signal to be a high level by the main control chip after all write command data are shifted and stored in the shift register and the chip select signal SEN is set to be a high level, setting the duration of the high level of the LOAD control signal LOAD to be at least more than one cycle of the serial clock during the high level of the chip select signal SEN, and setting the LOAD control signal LOAD signal to be a low level by the main control chip;
d', when the LOAD control signal LOAD changes from low level to high level during the period that the chip select signal maintains high level of SEN, the data in the shift register of each cascaded sub-stage chip is loaded into the m-bit register corresponding to an address in the second data register group, the address is determined by ADDR in the write command, thereby completing the write operation in the daisy chain mode. That is, a rising edge command of the LOAD control signal LOAD is executed while the chip select signal is maintained at the SEN high level, and the shift register value is loaded into the N-bit data register group.
In more detail, in the multi-chip circuit cascade communication system, different write control command information can be sent to different sub-chips so as to realize the configuration of different information on registers with different addresses; when the master control chip operates in the write register, the master control chip needs to send L N-bit write command data through the serial communication interface, the sending data format is to send a command R/W bit first, then send an addressing address ADDR and send a data bit last, and all the data are in a high order before and after.
In more detail, as shown in fig. 8, when the configurable daisy chain circuit structure compatible with the SPI interface is in the SPI-based daisy chain mode for communication, the principle of the corresponding read register operation is as follows:
a', aiming at a multi-chip circuit cascade communication system comprising an L-level sub-level chip, when a register is read, L register reading operation commands need to be sent, wherein the register reading commands have N bits in total and are composed of a one-bit reading and writing command R/W, N-m-1 bit register addressing address ADDR and data of an m-bit configuration register; when the main control chip operates the read register of the L-level sub-level chip, the N-bit read command data of each level of sub-level chip in the L-level sub-level chip needs to be configured in the main control chip, namely, the read command R/W is '1', an N-m-1 bit register addressing address ADDR is a register address which needs to be configured corresponding to the sub-level chip, and the data of the m-bit configuration register is data which needs to be configured by a register pointed by the address ADDR;
b', after the chip select signal SEN enters a low level state, as shown in FIG. 8, the main control chip starts to serially send read command data to the first-level sub-level chip through the SDO port, and shift and store the read command data in the register 1 of the N-bit shift register of the first-level sub-level chip, after the first N-bit read command data is sent, the N-bit shift register in the first sub-level sequentially stores the N-bit read command data, and when the main control chip sends the first bit data command R/W of the second N-bit read command data, the N-bit shift register in the first sub-level shifts and receives the bit data, and simultaneously, the register N of the N-bit shift register in the first sub-level shifts and outputs the first bit data command R/W of the first N-bit read command data to the register 1 of the N-bit shift register in the second sub-level chip, and continues in this way, after L N-bit read command data are sent, the L N-bit read command data are respectively and correspondingly stored in the sub-level N-bit shift registers;
c', the main control chip resets the LOAD control signal LOAD signal to low level when resetting, after all read command data are shifted and stored in the shift register and the chip select signal SEN is set to high level, the main control chip sets the LOAD control signal LOAD signal to high level, during the period that the chip select signal maintains the SEN high level, the duration time of the LOAD control signal LOAD high level is at least more than one period of the serial clock, and then the main control chip sets the LOAD control signal LOAD signal to low level;
d', when the LOAD control signal LOAD changes from low level to high level, the sub-chip of each cascade stage will LOAD the data in the m-bit register of the address to the corresponding data position in the shift register according to the received address ADDR, i.e. replace the data in the corresponding m-bit configuration register in the shift register with the data in the received address corresponding register, thereby completing the fetch operation of the register data, as shown in FIG. 8, executing the read command at the rising edge of the LOAD control signal LOAD, and loading the read data to the shift register corresponding data positions D11-D0;
e ″, when the chip select signal SEN changes from high level to low level, the main control chip sends the same L read register operation commands again, that is, the taken out data is shifted and output to the main control chip by the shift method, thereby completing the read operation in the daisy chain mode, and as shown in fig. 8, the read data needs to be shifted and output, and the dummy data of the same byte needs to be continuously sent.
The L register reading operation commands sent by the main control chip for the first time are used for sending a read command control bit and a register address to be read, and the L register reading operation commands sent by the main control chip for the second time are used for shifting data obtained after data fetching operation is carried out on the rising edge of the LOAD control signal LOAD and outputting the data to the main control chip.
Similarly, in the multi-chip circuit cascade communication system, when the master control chip reads the register, different read control command information can be sent to different sub-chips so as to read the registers with different addresses; when the master control chip reads the register, the master control chip needs to send L N-bit read command data through the serial communication interface, the sending data format is to send a read command R/W bit first, then read the register address ADDR and send a data bit finally, the data bit can send any data, and all the data have the high order before and after.
In detail, the sub-stage circuit of the above-mentioned configurable daisy chain circuit compatible with SPI interface in daisy chain mode can be operated by bypass control, as shown in fig. 9, and the principle is as follows:
in the multi-chip circuit cascade communication system, when a BYPASS input signal BYPASS is at a low level, a sub-chip is in a normal daisy chain working mode; when the BYPASS input signal BYPASS is at a high level, the daisy chain mode of the daughter chip is bypassed (shielded), and the serial clock input signal received by the serial interface of the daughter chip is directly transmitted to the serial output port of the daughter chip.
In addition, the multi-chip circuit cascade communication system is realized based on pure digital logic, is applied to a sub-level circuit chip in a multi-chip circuit cascade communication system, and is determined by adopting a process according to the sub-level circuit chip.
To sum up, in the multi-chip circuit cascade communication system having the configurable daisy chain circuit structure with the compatible SPI interface provided by the present invention, the multi-level sub-chips of the multi-chip circuit cascade communication system are connected in a daisy chain manner, the cascade communication interface of each sub-chip includes the configurable daisy chain circuit structure with the compatible SPI interface, by combining the general SPI communication interface and the daisy chain structure, under the condition of the same pin resource of the SPI communication interface, the cascade communication between one main control chip and the plurality of sub-chips can be realized, the main control chip can perform register writing and register reading operations of all registers for each cascaded sub-chip, perform register writing and reading operations of different addresses for each cascaded sub-chip, selectively bypass the accurate point-to-point and point-to-multiple operations of the sub-chips, and the like, the circuit structure realizes the accurate management and control of the main control chip on the cascade sub-level circuit chip, and effectively solves the problems that the cascade scheme in the traditional multi-chip circuit cascade communication interface has single function and can not be applied to occasions with complex requirements.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (9)

1. A multi-chip circuit cascade communication system is characterized by comprising a main control chip and a multi-stage sublevel chip, wherein the multi-stage sublevel chip and the main control chip are cascaded, and the multi-stage sublevel chip is connected with the main control chip in a daisy chain manner;
the serial clock output by the main control chip is connected with the clock input ends of all the sub-level chips, the chip selection signal output by the main control chip is connected with the chip selection input ends of all the sub-level chips, and the loading control signal output by the main control chip is connected with the loading control input ends of all the sub-level chips;
the serial output end of the main control chip is connected with the serial input end of the first-stage sub-stage chip; except the first-stage sublevel chip, the serial input ends of other sublevel chips are connected with the serial output end of the preceding-stage sublevel chip; the serial output end of the last-stage sub-stage chip is connected with the serial input end of the main control chip;
the cascade communication interface of each stage of the sub-stage chip comprises a configurable daisy chain circuit structure compatible with an SPI interface;
wherein, the configurable daisy chain circuit structure compatible with the SPI interface comprises:
the universal SPI communication interface is respectively connected with the chip selection signal, the serial clock input signal, the serial input signal and the reset input signal and receives serial data input in a common serial communication mode;
the daisy chain interface based on the SPI is respectively connected with the chip selection signal, the serial clock input signal, the serial input signal and the reset input signal and receives serial data input in a daisy chain communication mode;
the serial output signal selection module is connected with the serial input signal, the universal SPI communication interface and the SPI-based daisy chain interface and is used for selectively outputting the serial input signal, the serial output signal of the universal SPI communication interface and the serial output signal of the SPI-based daisy chain interface;
and the data register output selection module is connected with the universal SPI communication interface and the daisy chain interface based on the SPI, and is used for selectively outputting register data output signals of the universal SPI communication interface and register data output signals of the daisy chain interface based on the SPI, and the output end of the data register output selection module is connected with the control register group of each stage of the sublevel chip.
2. The multi-chip circuit cascade communication system of claim 1, wherein the bypass input of each of the sub-chips is floating, and the bypass input of each of the sub-chips is of a pull-down design and is at a low level when floating.
3. The multi-chip circuit cascade communication system of claim 2, wherein the serial output signal selection module comprises:
a first selector, which is respectively connected with the universal SPI communication interface, the daisy chain interface based on the SPI and the enabling control signal of the daisy chain mode, and selectively outputs the serial output signal of the universal SPI communication interface and the serial output signal of the daisy chain interface based on the SPI under the control of the enabling control signal of the daisy chain mode;
the second selector is respectively connected with the output of the first selector, the serial input signal and the bypass input signal, and selectively outputs the serial input signal and the output of the first selector under the control of the bypass signal;
wherein the output signal of the second selector is used as the serial output signal of each stage of the sub-stage chip.
4. The multi-chip circuit cascade communication system according to claim 3, wherein the data registering output selecting module comprises:
the input end of the inverter is connected with the chip selection signal and logically inverts the chip selection signal;
the input end of the first AND gate is respectively connected with the universal SPI communication interface and the output end of the phase inverter;
and the first and gate generates an enable signal when the first data register group latches data, and latches the parallel data output by the universal SPI communication interface at the rising edge of the last serial clock.
5. The multi-chip circuit cascade communication system of claim 4, wherein the data register output selection module further comprises:
the D trigger is provided with a reset end and is respectively connected with the serial clock input signal and the reset input signal to generate an enabling control signal of the daisy chain mode;
the third selector is respectively connected with the D trigger and the chip selection signal and is used for selectively outputting the Q end and the Qn end of the D trigger under the control of the chip selection signal;
the input end of the second AND gate is respectively connected with the daisy chain interface based on the SPI, the chip selection signal and the input end of the Q end of the third selector-connected D trigger;
and the second data register group is respectively connected with the SPI-based daisy chain interface, the output end of the second AND gate and the loading control signal, the second AND gate generates an enable signal when the second data register group latches data, and the shift storage value of the SPI-based daisy chain interface in the second data register group is latched on the rising edge of the loading control signal.
6. The multi-chip circuit cascade communication system of claim 5, wherein the data register output selection module further comprises:
and the fourth selector is respectively connected with the first data register group, the second data register group and the daisy chain mode enable control signal, and is used for selectively outputting the register data of the first data register group and the register data of the second data register group under the control of the daisy chain mode enable control signal.
7. The multi-chip circuit cascading communication system of claim 6, wherein the first AND gate comprises a two-input AND gate, the second AND gate comprises a three-input AND gate, and the first selector, the second selector, the third selector, and the fourth selector comprise one-out-of-two selectors.
8. The multi-chip circuit cascade communication system according to claim 7, wherein two falling edges occurring consecutively in the serial clock input signal form a pair of trigger signals during the high level period of the chip select signal, so that the daisy chain mode enable control signal generates a high level pulse, and the corresponding pulse width is determined by the interval between the two falling edges.
9. The multi-chip circuit cascade communication system of claim 8, wherein the sub-chips are in a daisy chain mode of operation when the bypass input signal is low; when the bypass input signal is at a high level, the daisy chain working mode of the sub-chip is bypassed, and the serial input signal received by the sub-chip through the serial interface is directly transmitted to the serial output port of the sub-chip.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105812392A (en) * 2016-05-18 2016-07-27 西安航天民芯科技有限公司 Cascading SPI communication system applied to battery monitoring chip and communication method
CN107145460A (en) * 2017-04-13 2017-09-08 上海云统信息科技有限公司 A kind of expansible serial bus system and its means of communication
CN108388492A (en) * 2018-03-20 2018-08-10 珠海格力电器股份有限公司 More dsp chip debugging control programs and device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10216678B2 (en) * 2014-10-07 2019-02-26 Infineon Technologies Ag Serial peripheral interface daisy chain communication with an in-frame response
US10642769B2 (en) * 2017-03-24 2020-05-05 Analog Devices Global Unlimited Company Serial peripheral interface daisy chain mode system and apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105812392A (en) * 2016-05-18 2016-07-27 西安航天民芯科技有限公司 Cascading SPI communication system applied to battery monitoring chip and communication method
CN107145460A (en) * 2017-04-13 2017-09-08 上海云统信息科技有限公司 A kind of expansible serial bus system and its means of communication
CN108388492A (en) * 2018-03-20 2018-08-10 珠海格力电器股份有限公司 More dsp chip debugging control programs and device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
理解ATE SPI（串行外设接口）;佚名;《http://www.eepw.com.cn/article/209452.htm》;20111122;1-5 *

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