CN113032312B - Multi-chip circuit cascade communication system - Google Patents

Abstract

The invention provides a multi-chip circuit cascade communication system. The multi-stage sub-level chips of the multi-chip circuit cascade communication system are connected in a daisy chain manner, and the cascade communication interface of each sub-level chip includes a SPI interface compatible interface. The daisy-chain circuit structure can be configured. By combining the general SPI communication interface and the daisy-chain structure, with the same SPI communication interface pin resources, cascaded communication between one main control chip and multiple sub-circuit chips can be realized. The chip can write and read registers of all registers for each cascaded sub-circuit chip, perform register write and read operations with different addresses for each cascaded sub-circuit chip, and selectively bypass the sub-level Accurate point-to-point and point-to-multiple operations such as circuit chips realize the precise management and control of the main control chip to the cascaded sub-level circuit chips, effectively solving the existing multi-chip circuit cascade communication interface. Problems that cannot be applied to complex demand occasions.

Description

Multi-chip circuit cascade communication system

technical field

The present invention relates to the technical field of signal processing and communication, in particular to a multi-chip circuit cascade communication system.

Background technique

With the development of science and technology, the functions of electronic systems oriented to the application market continue to increase, and the number of integrated circuits integrated on the system is also increasing. In some electronic systems, in order to achieve complex multi-channel processing, the same integrated circuit will integrate several . This will result in an exponential increase in the demand for the same signal pin connection resources, thereby placing a heavy pin resource burden on the processor that performs the final signal processing. For example, if an electronic system needs to integrate an ADC circuit, the SPI-based communication interface requires at least 4 (SCLK, CSN, SDI, SDO) pin resources. Needing 40 pin resources, the pin resource requirement will increase by 36 pins, which will undoubtedly be a very heavy burden on the pin resources of an electronic system. Change the design to use a processor with more pin resources (DSP or FPGA, etc.), which will bring the risk of design changes and increase the cost.

At present, in order to solve the above problems, many manufacturers in the industry have introduced SPI interfaces that support the daisy-chain mode to solve the multi-chip cascade problem. For example, the AD7690 product of ADI Company in the United States, its SPI interface includes four signals CNV, SCK, SDI and SDO, as shown in Figure 1, the recommended cascading solution is to share the enable signal CNV and clock signal SCK, and the previous In this way, the output SDO of the stage is cascaded with the input SDI of the latter stage. If the driving capacity is sufficient, no matter how many AD7690s are cascaded, for the signal processor of the latter stage, only three signal interfaces are provided, which greatly saves money. Pin resources for signal processors.

However, the above solutions and other similar cascaded solutions only serially shift and output the output data in the monolithic integrated circuit by means of interface signals (CNV, SCK, SDI and SDO) in a shifted manner, that is, read data; However, when it is necessary to write configuration information to multiple registers in a monolithic integrated circuit, read register values for verification, and to selectively bypass a certain cascaded circuit when cascading, the above solution cannot be satisfied. , that is, the above scheme has a single function and cannot be applied to complex occasions.

SUMMARY OF THE INVENTION

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a multi-chip circuit cascade communication system including a configurable daisy-chain circuit structure compatible with an SPI interface, to solve the above-mentioned technical problems.

In order to achieve the above object and other related purposes, the present invention provides a multi-chip circuit cascade communication system, which includes a main control chip and a multi-level sub-level chip, and the multi-level sub-level chip and the main control chip are cascaded, And the multi-level sub-level chips are connected by a daisy chain;

The serial clock output by the main control chip is connected with the clock input terminals of all the sub-level chips, the chip select signal output by the main control chip is connected with the chip select input terminals of all the sub-level chips, and the main control chip is connected. The loading control signal output by the control chip is connected with the loading control input terminals of all the sub-level chips;

The serial output terminal of the main control chip is connected to the serial input terminal of the first-level sub-level chip; except for the first-level sub-level chip, the serial input terminals of the other sub-level chips are all connected to the serial input terminal of the first-level sub-level chip. The serial output terminal of the sub-level chip in the previous stage is connected; the serial output terminal of the sub-level chip in the last stage is connected with the serial input terminal of the main control chip;

The cascaded communication interface of the sub-level chips at each stage includes a configurable daisy-chain circuit structure compatible with the SPI interface.

Optionally, the bypass input terminal of the sub-level chip of each stage is suspended, and the bypass input terminal of the sub-level chip of each stage is a pull-down design, and is a low level in a floating state.

Optionally, the configurable daisy-chain circuit structure compatible with the SPI interface includes:

a general SPI communication interface, which is respectively connected with the chip select signal, the serial clock input signal, the serial input signal and the reset input signal, and receives serial data input in a common serial communication mode;

The SPI-based daisy-chain interface is respectively connected with the chip select signal, the serial clock input signal, the serial input signal and the reset input signal, and receives serial data input in the daisy-chain communication mode;

The serial output signal selection module is connected with the serial input signal, the general SPI communication interface and the SPI-based daisy-chain interface, and is connected to the serial input signal, the serial output signal of the general SPI communication interface and the The serial output signal based on the SPI daisy-chain interface is selected and output;

A data register output selection module, connected with the general SPI communication interface and the SPI-based daisy-chain interface, and selects the register data output signal of the general SPI communication interface and the register data output signal of the SPI-based daisy-chain interface output, the output terminal of which is connected to the control register group of the sub-level chip of each level.

Optionally, the serial output signal selection module includes:

The first selector is respectively connected with the general-purpose SPI communication interface, the SPI-based daisy-chain interface, and the enabling control signal of the daisy-chain mode, and under the control of the enabling control signal of the daisy-chain mode, the general The serial output signal of the SPI communication interface and the serial output signal of the SPI-based daisy-chain interface are selectively output;

The second selector is respectively connected to the output of the first selector, the serial input signal and the bypass input signal, and under the control of the bypass signal, selects the serial input signal and the first selector. The output of the controller is selected for output;

Wherein, the output signal of the second selector is used as the serial output signal of the sub-level chip of each stage.

Optionally, the data register output selection module includes:

an inverter, the input end of which is connected to the chip selection signal, and logically inverts the chip selection signal;

the first AND gate, the input end of which is respectively connected with the output end of the general SPI communication interface and the inverter;

The first data register group is respectively connected with the general SPI communication interface, the output end of the first AND gate and the serial clock input signal, and the first AND gate generates the first data register group to latch data. Enable signal to latch the parallel data output by the general SPI communication interface at the rising edge of the last serial clock.

Optionally, the data register output selection module further includes:

A D flip-flop, with a reset terminal, is respectively connected with the serial clock input signal and the reset input signal to generate an enable control signal of the daisy-chain mode;

The third selector is respectively connected with the D flip-flop and the chip selection signal, and under the control of the chip selection signal, selects and outputs the Q terminal and the Qn terminal of the D flip-flop;

The second AND gate, the input ends of which are respectively connected with the input ends of the SPI-based daisy-chain interface, the chip select signal and the third selector;

The second data register group is respectively connected to the SPI-based daisy-chain interface, the output end of the second AND gate and the load control signal. When the second AND gate generates the second data register group to latch data The enable signal of the SPI-based daisy-chain interface in the second data register group is latched at the rising edge of the load control signal.

Optionally, the data register output selection module further includes:

The fourth selector is respectively connected with the first data register group, the second data register group and the enable control signal of the daisy-chain mode, and under the control of the enable control signal of the daisy-chain mode, the The registered data of one data register group and the registered data of the second data register group are selected and output.

Optionally, the first AND gate includes a two-input AND gate, the second AND gate includes a three-input AND gate, and the first selector, the second selector, the third selector, and the fourth selector include Two-to-one selector.

Optionally, during the high level period of the chip select signal, two consecutive falling edges in the serial clock input signal constitute a pair of trigger signals, so that the enable control signal of the daisy-chain mode generates a trigger signal. For a high-level pulse, the corresponding pulse width is determined by the interval between the two falling edges.

Optionally, when the bypass input signal is at a low level, the sub-level chip is in a daisy-chain operation mode; when the bypass input signal is at a high level, the daisy-chain operation mode of the sub-level chip is disabled. Bypass, the serial clock input signal received by the sub-level chip through the serial interface is directly transmitted to the serial output port of the sub-level chip.

As mentioned above, the multi-chip circuit cascade communication system of the present invention has the following beneficial effects:

The multi-level sub-level chips are connected by a daisy-chain method. The cascaded communication interface of each level of sub-level chips includes a configurable daisy-chain circuit structure compatible with the SPI interface. By combining the general SPI communication interface and the daisy-chain structure, the same SPI In the case of communication interface pin resources, one main control chip can communicate with multiple sub-level circuit chips in cascade; the main control chip can write and read all registers for each cascaded sub-level circuit chip. operation, the main control chip can simultaneously perform register write and read operations with different addresses for each cascaded sub-circuit chip, and the main control chip can selectively bypass the sub-circuit chips; in addition, without additional pin resources This circuit structure allows the main control chip to perform precise point-to-point and point-to-multiple operations on the cascaded sub-circuit chips, and realizes the precise management and control of the cascaded sub-circuit chips by the main control chip. The circuit chip with such a communication interface can be applied to complex demand occasions.

Description of drawings

Figure 1 shows the daisy-chain cascade connection structure of AD7690 products of ADI Company.

FIG. 2 shows a daisy-chain cascade connection structure of a multi-chip circuit cascade communication system according to an embodiment of the present invention.

FIG. 3 is a schematic structural diagram of a preferred implementation manner of a configurable daisy-chain circuit structure compatible with an SPI interface of a multi-chip circuit cascade communication system according to an embodiment of the present invention.

FIG. 4 is a sequence diagram of a serial interface communication of an input terminal in an embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating a data transmission structure of a main control chip sent in a multi-chip circuit cascade communication system according to an embodiment of the present invention.

FIG. 6 is a timing diagram illustrating a preferred embodiment of a process of generating an enable control signal DCM_EN in a daisy-chain mode in a multi-chip circuit cascaded communication system according to an embodiment of the present invention.

FIG. 7 is a timing diagram illustrating a preferred implementation manner of a register write operation process in a daisy-chain mode of a multi-chip circuit cascaded communication system according to an embodiment of the present invention.

FIG. 8 is a timing diagram illustrating a preferred implementation manner of a read register operation process of a multi-chip circuit cascade communication system in a daisy-chain mode according to an embodiment of the present invention.

FIG. 9 is a timing diagram illustrating a preferred embodiment of an operation process in which sub-level circuits are bypassed in a daisy-chain mode of a method for implementing a multi-chip circuit cascaded communication system according to an embodiment of the present invention.

Detailed ways

The inventor's research found that the existing cascading solutions only serially shift the output data in the monolithic integrated circuit through the interface signals (CNV, SCK, SDI and SDO) in a shifted manner (that is, read data), but when it is necessary to write configuration information to multiple registers in a monolithic integrated circuit, read register values for verification, and to selectively bypass a certain cascaded circuit when cascading complex operations, the above scheme is not Unable to meet the needs, that is, the above solutions have a single function and cannot be applied to complex occasions.

Based on this, the present invention proposes a multi-chip circuit cascading communication system including a configurable daisy-chain circuit structure compatible with an SPI interface. The cascaded communication interface of the sub-level chip includes a configurable daisy-chain circuit structure compatible with the SPI interface. By combining the general SPI communication interface and the daisy-chain structure, under the same SPI communication interface pin resources, one master can be realized. The control chip communicates with multiple sub-level circuit chips in cascade, and the main control chip can write and read all registers for each cascaded sub-level circuit chip, and the main control chip can simultaneously write and read registers for each cascaded The sub-level circuit chips perform register write and read operations at different addresses, and this circuit structure allows the main control chip to perform precise point-to-point and point-to-multiple operations on the cascaded sub-level circuit chips, realizing the cascade of the main control chips. The precise management and control of sub-level circuit chips enables circuit chips with such communication interfaces to be applied to complex demand occasions.

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 to 9. It should be noted that the drawings provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, so the drawings only show the components related to the present invention rather than the number, shape and the number of components in actual implementation. For dimension drawing, the type, quantity and proportion of each component can be changed at will in actual implementation, and the component layout may also be more complicated. The structures, proportions, sizes, etc. shown in the drawings in this specification are only used to cooperate with the contents disclosed in the specification for the understanding and reading of those who are familiar with the technology, and are not intended to limit the conditions for the implementation of the present invention. , therefore does not have technical substantive significance, any structural modification, proportional relationship change or size adjustment, without affecting the effect that the present invention can produce and the purpose that can be achieved, should still fall within the scope of the present invention. The technical content must be able to cover the scope.

As shown in FIG. 2, the present invention provides a multi-chip circuit cascade communication system, which includes a main control chip and a multi-level sub-level chip, the multi-level sub-level chip and the main control chip are cascaded, and the multi-level sub-level chip is connected. connected by daisy chain;

The serial clock signal SCK output by the main control chip is connected with the clock input terminals of all sub-level chips, the chip select signal SEN output by the main control chip is connected with the chip select input terminals of all sub-level chips, and the loading control signal output by the main control chip LOAD is connected to the load control input terminals of all sub-level chips;

The serial output terminal of the main control chip is connected to the serial input terminal of the first-level sub-level chip; except for the first-level sub-level chip, the serial input terminals of other sub-level chips are connected to the serial input terminal of the previous-level sub-level chip. The output terminal is connected; the serial output terminal of the last stage sub-level chip is connected with the serial input terminal of the main control chip;

The cascaded communication interface of each sub-level chip includes a configurable daisy-chain circuit structure compatible with the SPI interface.

Optionally, as shown in FIG. 2 , the bypass input terminal of each sub-level chip is suspended, and the bypass input terminal of each sub-level chip is designed to be pulled down, and is low level in the floating state.

Optionally, the multi-chip circuit cascade communication system shown in FIG. 2 includes 4-level sub-level chips; the multi-chip circuit cascade communication system shown in FIG. 6 includes L-level sub-level chips.

Optionally, as shown in Figure 3, the configurable daisy-chain circuit structure compatible with the SPI interface includes:

The general SPI communication interface is respectively connected with the chip select signal SEN, the serial clock input signal SCLK, the serial input signal SDI and the reset input signal RST, and receives serial data input in the ordinary serial communication mode;

The SPI-based daisy-chain interface is respectively connected with the chip select signal SEN, the serial clock input signal SCLK, the serial input signal SDI and the reset input signal RST, and receives serial data input in the daisy-chain communication mode;

The serial output signal selection module is connected with the serial input signal SDI, the general SPI communication interface and the SPI-based daisy-chain interface, and the serial input signal SDI, the serial output signal SDO_spi of the general SPI communication interface and the SPI-based daisy-chain interface The serial output signal SDO_DCM of the port is selected and output;

The data register output selection module is connected with the general-purpose SPI communication interface and the SPI-based daisy-chain interface, and selects and outputs the register data output signal of the general-purpose SPI communication interface and the register data output signal of the SPI-based daisy-chain interface. Terminates the control register bank of each sub-level chip.

The general-purpose SPI communication interface is a general-purpose SPI communication interface, and its structure may refer to the prior art, which will not be repeated here.

In detail, as shown in Figure 3, the serial output signal selection module includes:

The first selector MUX1 is respectively connected with the general SPI communication interface, the SPI-based daisy-chain interface and the enable control signal DCM_EN of the daisy-chain mode, and under the control of the enable control signal DCM_EN of the daisy-chain mode, the general SPI communication interface The serial output signal SDO_spi of the SPI and the serial output signal SDO_DCM of the SPI-based daisy-chain interface are selected and output, and the output terminal outputs the serial output signal SDO_T;

The second selector MUX2 is respectively connected to the output of the first selector MUX1, the serial input signal SDI and the bypass input signal BYPASS, and under the control of the bypass signal BYPASS, the serial input signal SDI and the first selector MUX1 The output SDO_T is selected for output;

Wherein, the output signal of the second selector MUX2 is used as the serial output signal SDO of each sub-level chip.

In detail, as shown in Figure 3, the data register output selection module includes:

Inverter INV1, the input terminal of which is connected to the chip select signal SEN, and logically inverts the chip select signal SEN;

The first AND gate AND2x1, whose input ends are respectively connected with the general SPI communication interface and the output end of the inverter INV1, performs AND operation on the signal M/R_spi output by the general SPI communication interface and the inverted signal of the chip select signal SEN, Its output terminal gets the enable signal EN1;

The first data register group is respectively connected with the general SPI communication interface, the output end of the first AND gate AND2x1 and the serial clock input signal SCLK, and the first AND gate AND2x1 generates the enable signal EN1 when the first data register group latches data , latch the parallel data output by the general SPI communication interface at the rising edge of the last serial clock, which receives the address signal ADDR_spi[N-m-1] and the serial output signal spi_D[m-1:0] output by the general SPI communication interface And output the registered data signal data_SPI[m-1:0].

The first data register group is an m-bit data register group, and m is a positive integer such as 8, 16, and so on.

In detail, as shown in Figure 3, the data register output selection module further includes:

D flip-flop DFFR1, with a reset terminal, is connected to the serial clock input signal SCLK and the reset input signal RST respectively, the CK terminal is connected to the serial clock input signal SCLK, the R terminal is connected to the reset input signal RST, and the output terminal Q is connected Generate daisy-chain mode enable control signal DCM_EN;

The third selector MUX3 is connected to the D flip-flop DFFR1 and the chip selection signal SEN respectively. The two input ends of the third selector MUX3 are respectively connected to the output end Q and the output end Qn of the D flip-flop DFFR1. The third selector The control terminal of MUX3 is connected to the chip selection signal SEN, and the output terminal of the third selector MUX3 is connected to the input terminal D of the D flip-flop DFFR1. Under the control of the chip selection signal SEN, the Q terminal and the Qn terminal of the D flip-flop DFFR1 are selected. output;

The second AND gate AND3x1 is connected to the input end of the SPI-based daisy-chain interface, the chip selection signal SEN and the input end of the third selector MUX3, respectively. The enable control signal DCM_EN of SEN and daisy-chain mode performs AND operation, and outputs the enable signal EN2 at its output;

The second data register group is respectively connected with the SPI-based daisy-chain interface, the output end of the second AND gate AND3x1 and the loading control signal LOAD, and the second AND3x1 generates an enable signal EN2 when the second data register group latches data , at the rising edge of the load control signal LOAD to latch the shift stored value of the SPI-based daisy-chain interface in the second data register group, which receives the address signal DCM_ADDR[N-m-1] output by the general SPI communication interface and the serial output signal DCM_D[m-1:0] and output the registered data signal data_DCM[m-1:0].

The second data register group is also an m-bit data register group.

In detail, as shown in Figure 3, the data register output selection module further includes:

The fourth selector MUX group 1 is respectively connected to the first data register group, the second data register group and the enable control signal DCM_EN of the daisy-chain mode. Under the control of the enable control signal DCM_EN of the daisy-chain mode, the first The registered data signal data_SPI[m-1:0] of the data register group and the registered data signal data_DCM[m-1:0] of the second data register group are selected and output, and the data signal Data[m-1: 0], and its output is connected to the control register group of each sub-level chip.

Optionally, as shown in FIG. 3, the first AND gate AND2x1 includes a two-input AND gate, the second AND gate AND3x1 includes a three-input AND gate, the first selector MUX1, the second selector MUX2, the third selector MUX3 and The fourth selector MUX group 1 includes a binary selector.

In an embodiment of the present invention, please refer to FIG. 4 for the signal timings of the serial input ports of the general SPI communication interface and the SPI-based daisy-chain interface in the multi-chip circuit cascade communication system.

In detail, the working principle of the above-mentioned configurable daisy-chain circuit structure compatible with the SPI interface will be briefly described below.

In more detail, when the configurable daisy-chain circuit structure compatible with the SPI interface is in the general SPI communication mode, it is a write register operation at this time, and the external serial input data of each stage of the sub-chip will be read in the general SPI communication interface. Receive, if the received command W/R=0, when receiving the falling edge of the last clock of the serial clock input signal SCLK, the received command W/R, the address signal ADDR_spi[N-m-1] and the serial communication chip Under the control of the selection signal SEN, the serially received data is stored in the register corresponding to the receiving address ADDR located in the first data register group, and output to the off-chip at the same time; when the operation is to read the register, each level of sub-chip The external serial input data will be received in the general SPI communication interface. If the received command W/R=1, after receiving the address ADDR information, the first clock of the serial clock input signal SCLK will rise. Edge, according to the received command W/R, address signal ADDR_spi[N-m-1], read the data stored in the register corresponding to this address into the serial receive register, and output it through the serial output port SDO_spi, and finally in the daisy chain Under the control of the mode enable control signal DCM_EN and the bypass input signal BYPASS, it is output to the off-chip SDO port.

In more detail, as shown in FIG. 5 , the generation process of the enable control signal DCM_EN in the daisy-chain mode is as follows:

a. When the externally input reset signal RST is reset at a high level, the Q terminal outputs a low level, that is, the level of the DCM_EN of the D flip-flop DFFR1 is a low level after the reset;

b. When the input chip selection signal SEN is at a high level, the third selector MUX3 selects the Qn terminal of the D flip-flop DFFR1 to output as the data input of the D terminal of the D flip-flop DFFR1; while maintaining the chip selection signal SEN at a high level , when the serial input clock signal SCLK has a falling edge for the first time, the D flip-flop DFFR1 will be triggered to collect the input data of the D terminal, and the input data of the D terminal is connected to the Qn terminal of the D flip-flop DFFR1 at this time, that is, the chip select signal During the high level of SEN and the falling edge of the serial input clock signal SCLK, the output of the Q terminal of the D flip-flop DFFR1 will be inverted, and the reset low level will be changed to a high level, that is to say, the daisy-chain mode is enabled. Can control signal DCM_EN to be high level;

c. When the input chip selection signal SEN changes from high level to low level, the third selector MUX3 selects the Q terminal of the D flip-flop DFFR1 to output as the data input of the D terminal of the D flip-flop DFFR1, while maintaining the chip selection signal SEN During the low level period, when the serial input clock signal SCLK has several falling edge signals, the D flip-flop DFFR1 will be triggered to collect the input data of the D terminal, and the input data of the D terminal is always connected to the Q terminal of the D flip-flop DFFR1 at this time. That is, when the serial input clock signal SCLK is triggered by the falling edge of the serial input clock signal SCLK during the low level of the chip select signal SEN, the Q terminal of the D flip-flop DFFR1 will keep the high level output value unchanged, that is to say, the enable control signal DCM_EN of the daisy chain mode keep the high level unchanged;

d. When the input chip select signal SEN is restored from low level to high level, and the serial input clock signal SCLK has a falling edge signal again, the D flip-flop DFFR1 flip-flop will be triggered to collect the input data of the D terminal, and the D terminal will be triggered. The input data is connected to the Qn terminal of the D flip-flop DFFR1 at this time, that is, when the chip select signal SEN is at a high level and the serial input clock signal SCLK is triggered by the falling edge again, the output of the Q terminal of the D flip-flop DFFR1 will be inverted. The high level maintained at the Q terminal changes to a low level, that is, the enable control signal DCM_EN of the daisy-chain mode changes to a low level;

e. During the high level period of the chip select signal SEN, with the continuous occurrence of the falling edge signal of the serial input clock signal SCLK, the enable control signal DCM_EN of the daisy-chain mode will also switch repeatedly between the high level and the low level. , that is, during the high-level period of the chip select signal SEN, the two falling edges of the serial input clock signal SCLK that appear continuously constitute a pair of trigger signals, so that the enable control signal DCM_EN of the daisy-chain mode generates a high-level pulse, The pulse width is determined by the interval between the corresponding two falling edges.

As shown in Figure 5, when the chip select signal SEN is maintained at a high level and the first falling edge of the serial input clock signal SCLK, the enable control signal DCM_EN of the daisy-chain mode changes from a low level to a high level (The enable control signal DCM_EN of the daisy-chain mode is active high), the circuit enters the daisy-chain mode; when the chip select signal SEN is maintained at a high level, when the second falling edge of the serial input clock signal SCLK, the daisy-chain The enable control signal DCM_EN of the mode changes from high level to low level, the circuit ends the daisy-chain mode and returns to the normal SPI mode; the enable control signal DCM_EN of the daisy-chain mode is a signal generated inside the circuit and does not occupy the port’s Pin resources.

In more detail, as shown in Figure 6 and Figure 7, when the configurable daisy-chain circuit structure compatible with the SPI interface is in the SPI-based daisy-chain mode for communication, the principle of the corresponding write register operation is as follows:

a', as shown in Figure 6, for a multi-chip circuit cascade communication system including L-level sub-chips, the main control chip needs to send L write register operation commands during the write register operation. This write register command has a total of N bits, It consists of one-bit read and write command R/W, N-m-1-bit register addressing address ADDR, and m-bit configuration register data; when the main control chip writes registers to the cascaded L-level sub-level chips, it needs to be The chip configures the N-bit write command data of each sub-level chip in the L-level sub-level chip, that is, the write command R/W is "0", and the N-m-1-bit register addressing address ADDR is the corresponding sub-level chip. The register address to be configured and the data of the m-bit configuration register are the data that the register pointed to by the address ADDR needs to be configured;

b', starting from the falling edge of the chip select signal SEN to serially write the command data and shift transmission, after the chip select signal SEN enters the low level state, as shown in Figure 6 and Figure 7, the main control chip starts to pass the serial The line output port serially sends the write command data to the cascaded first-level sub-level chip, and shifts and stores it in the register of the N-bit shift register of the first-level sub-level chip, waiting for the first N-bit write command After the data is sent, the N-bit shift register in the first sub-level stores the N-bit write command data in turn. When the main control chip sends the first data "command R/W" of the second N-bit write command data, When the N-bit shift register in the first sub-stage shifts to receive this data, the register N of the N-bit shift register in the first sub-stage will shift and output the first bit of the first N-bit write command data" Command R/W" to the register of the N-bit shift register in the second sub-chip, and this continues until the L N-bit write command data is sent, the L N-bit write command data will be stored in each corresponding In the N-bit shift register of the sub-chip;

c'. The main control chip resets the load control signal LOAD signal to a low level during reset. After all the write command data is shifted and stored in the shift register and the chip select signal SEN is set to a high level, the main control chip will The loading control signal LOAD signal is set to high level. During the high level of the chip select signal SEN, the duration of the loading control signal LOAD high level is at least one cycle longer than the serial clock, and then the main control chip sets the loading control signal LOAD signal to a high level. is low level;

d'. During the period when the chip select signal maintains the high level of SEN, when the load control signal LOAD changes from low level to high level, the data in the shift register of each level of cascaded sub-level chips will be loaded into the first level. In the m-bit register corresponding to an address of the two data register groups, this address is determined by the ADDR in the write command, thereby completing the write operation in the daisy-chain mode. That is, while the chip select signal maintains the high level of SEN, the rising edge command of the load control signal LOAD is executed, and the shift register value is loaded into the N-bit data register group.

In more detail, in a multi-chip circuit cascade communication system, different write control command information can be sent to different sub-level chips, so as to realize the configuration of different information for registers with different addresses; , the main control chip needs to send L N-bit write command data through the serial communication interface. The sending data format is to send the command R/W bit first, then send the addressing address ADDR, and finally send the data bit. All data are high-order first. , the status is behind.

In more detail, as shown in Figure 8, when the configurable daisy-chain circuit structure compatible with the SPI interface is in the SPI-based daisy-chain mode for communication, the principle of the corresponding read register operation is as follows:

a". For a multi-chip circuit cascade communication system including L-level sub-level chips, when reading a register, it is necessary to send L read register operation commands. This register read command has a total of N bits, and one read and write command R/W , N-m-1-bit register addressing address ADDR, m-bit configuration register data composition; when the main control chip reads the register to the L-level sub-level chip, it needs to be in the main control chip for each of the L-level sub-level chips. The N-bit read command data of the sub-level chip is configured, that is, the read command R/W is "1", the N-m-1-bit register addressing address ADDR is the register address that needs to be configured for the corresponding sub-level chip, and the m-bit configuration register data. The data that needs to be configured for the register pointed to by the address ADDR;

b". After the chip select signal SEN enters the low level state, as shown in Figure 8, the main control chip starts to serially send the read command data to the cascaded first-level sub-level chip through the SDO port, and shift and store it in In the register 1 of the N-bit shift register of the first-level sub-level chip, after the first N-bit read command data is sent, the N-bit shift register in the first sub-level sequentially stores the N-bit read command data. When the main control chip sends the first data "command R/W" of the second N-bit read command data, while the N bit shift register in the first sub-stage shifts to receive this data, the first sub-stage The register N of the N-bit shift register will shift and output the first bit data "command R/W" of the first N-bit read command data to the register 1 of the N-bit shift register in the second sub-chip, and so on. , when the L N-bit read command data is sent, the L N-bit read command data will be stored in each sub-level N bit shift register correspondingly;

c". The main control chip resets the load control signal LOAD signal to a low level during reset. After all the read command data is shifted and stored in the shift register and the chip select signal SEN is set to a high level, the main control chip will The load control signal LOAD signal is set to high level. During the period when the chip select signal maintains SEN high level, the duration of the load control signal LOAD high level is at least one cycle longer than the serial clock, and then the main control chip will load the control signal LOAD signal. set to low level;

d". During the period when the chip select signal SEN maintains a high level, each sub-level chip in the cascade receives a read command, so when the load control signal LOAD changes from a low level to a high level, the sub-level chip will For the received address ADDR, the data in the m-bit register of the address is loaded into the corresponding data position in the shift register, that is, the data in the corresponding register of the received address is used to replace the corresponding m-bit configuration register in the shift register. data, so as to complete the fetch operation of the register data, as shown in Figure 8, execute the read command on the rising edge of the load control signal LOAD, and load the read data into the corresponding data positions D11 to D0 of the shift register;

e". When the chip select signal SEN changes from high level to low level, the main control chip sends the same L read register operation commands again, that is, by shifting, the extracted data is shifted and output to the main control chip , so as to complete the read operation in the daisy-chain mode. As shown in Figure 8, the data read out is shifted and output, and it is necessary to continue to send the same byte of empty data.

Among them, the L read register operation commands sent by the main control chip for the first time are to send the read command control bit and the register address to be read, and the L read register operation commands sent by the main control chip for the second time On the rising edge of the signal LOAD, the data after the data fetch operation is shifted and output to the main control chip.

Similarly, in a multi-chip circuit cascade communication system, when the main control chip performs a register read operation, different read control command information can be sent to different sub-level chips to realize the read operation of registers with different addresses; When the chip reads the register, the main control chip needs to send L N-bit read command data through the serial communication interface. The format of the data sent is to send the read command R/W bit first, then send the read register address ADDR, and finally send the data bit. The data bits can send any data, and all data are high-order first and last.

In detail, the sub-level circuit of the above-mentioned configurable daisy-chain circuit compatible with the SPI interface in the daisy-chain mode can be operated by bypass control, as shown in Figure 9, and the principle is as follows:

In a multi-chip circuit cascade communication system, when the bypass input signal BYPASS is low level, the sub-level chip is in the normal daisy-chain working mode; when the bypass input signal BYPASS is high level, the sub-level chip is in the daisy-chain mode. Being bypassed (shielded), the serial clock input signal received by the sub-stage chip through the serial interface is directly transmitted to the serial output port of the sub-stage chip.

In addition, the multi-chip circuit cascade communication system of the present invention is realized based on pure digital logic, and is applied to the sub-level circuit chips in the multi-chip circuit cascade communication system.

To sum up, in the multi-chip circuit cascade communication system including the configurable daisy-chain circuit structure compatible with the SPI interface provided by the present invention, the multi-level sub-chips of the multi-chip circuit cascade communication system pass through the daisy chain. The cascading communication interface of each sub-level chip includes a configurable daisy-chain circuit structure compatible with the SPI interface. By combining the general SPI communication interface and the daisy-chain structure, under the same SPI communication interface pin resources, the Realize cascade communication between one main control chip and multiple sub-level circuit chips. The main control chip can write and read registers of all registers for each cascaded sub-level circuit chip. The circuit chip performs precise point-to-point and point-to-multiple operations such as register write and read operations at different addresses, and selectively bypasses the sub-level circuit chips. This circuit structure realizes the precise management of the cascaded sub-level circuit chips by the main control chip. and control, effectively solving the problem that the cascading scheme in the existing multi-chip circuit cascading communication interface has a single function and cannot be applied to complex demand occasions.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (9)

1. A multi-chip circuit cascade communication system is characterized in that, comprising a main control chip and a multi-level sub-level chip, the multi-level described sub-level chip and the described main control chip are cascaded, and the multi-level described sub-level chip The chips are connected by daisy chain; The serial clock output by the main control chip is connected with the clock input terminals of all the sub-level chips, the chip select signal output by the main control chip is connected with the chip select input terminals of all the sub-level chips, and the main control chip is connected. The loading control signal output by the control chip is connected with the loading control input terminals of all the sub-level chips; The serial output terminal of the main control chip is connected to the serial input terminal of the first-level sub-level chip; except for the first-level sub-level chip, the serial input terminals of the other sub-level chips are all connected to the serial input terminal of the first-level sub-level chip. The serial output terminal of the sub-level chip in the previous stage is connected; the serial output terminal of the sub-level chip in the last stage is connected with the serial input terminal of the main control chip; The cascaded communication interface of the sub-level chips of each level includes a configurable daisy-chain circuit structure compatible with the SPI interface; Wherein, the configurable daisy-chain circuit structure compatible with the SPI interface includes: a general SPI communication interface, which is respectively connected with the chip select signal, the serial clock input signal, the serial input signal and the reset input signal, and receives serial data input in a common serial communication mode; The SPI-based daisy-chain interface is respectively connected with the chip select signal, the serial clock input signal, the serial input signal and the reset input signal, and receives serial data input in the daisy-chain communication mode; The serial output signal selection module is connected with the serial input signal, the general SPI communication interface and the SPI-based daisy-chain interface, and is connected to the serial input signal, the serial output signal of the general SPI communication interface and the The serial output signal based on the SPI daisy-chain interface is selected and output; A data register output selection module, connected with the general SPI communication interface and the SPI-based daisy-chain interface, and selects the register data output signal of the general SPI communication interface and the register data output signal of the SPI-based daisy-chain interface output, the output terminal of which is connected to the control register group of the sub-level chip of each level. 2. The multi-chip circuit cascade communication system according to claim 1, wherein the bypass input end of the sub-level chip of each level is suspended, and the bypass input end of the sub-level chip of each level is a pull-down design , it is low level in the floating state. 3. The multi-chip circuit cascade communication system according to claim 2, wherein the serial output signal selection module comprises: The first selector is respectively connected with the general-purpose SPI communication interface, the SPI-based daisy-chain interface, and the enabling control signal of the daisy-chain mode, and under the control of the enabling control signal of the daisy-chain mode, the general The serial output signal of the SPI communication interface and the serial output signal of the SPI-based daisy-chain interface are selectively output; The second selector is respectively connected to the output of the first selector, the serial input signal and the bypass input signal, and under the control of the bypass signal, selects the serial input signal and the first selector. The output of the controller is selected for output; Wherein, the output signal of the second selector is used as the serial output signal of the sub-level chip of each stage. 4. The multi-chip circuit cascade communication system according to claim 3, wherein the data register output selection module comprises: an inverter, the input end of which is connected to the chip selection signal, and logically inverts the chip selection signal; the first AND gate, the input end of which is respectively connected with the output end of the general SPI communication interface and the inverter; The first data register group is respectively connected with the general SPI communication interface, the output end of the first AND gate and the serial clock input signal, and the first AND gate generates the first data register group to latch data. Enable signal to latch the parallel data output by the general SPI communication interface at the rising edge of the last serial clock. 5. The multi-chip circuit cascade communication system according to claim 4, wherein the data register output selection module further comprises: A D flip-flop, with a reset terminal, is respectively connected with the serial clock input signal and the reset input signal to generate an enable control signal of the daisy-chain mode; The third selector is respectively connected with the D flip-flop and the chip selection signal, and under the control of the chip selection signal, selects and outputs the Q terminal and the Qn terminal of the D flip-flop; The second AND gate, the input end of which is respectively connected with the input end of the SPI-based daisy-chain interface, the chip select signal and the Q end of the third selector connected to the D flip-flop; The second data register group is respectively connected to the SPI-based daisy-chain interface, the output end of the second AND gate and the load control signal. When the second AND gate generates the second data register group to latch data The enable signal of the SPI-based daisy-chain interface in the second data register group is latched at the rising edge of the load control signal. 6. The multi-chip circuit cascade communication system according to claim 5, wherein the data register output selection module further comprises: The fourth selector is respectively connected with the first data register group, the second data register group and the enable control signal of the daisy-chain mode, and under the control of the enable control signal of the daisy-chain mode, the The registered data of one data register group and the registered data of the second data register group are selected and output. 7. The multi-chip circuit cascade communication system according to claim 6, wherein the first AND gate comprises a two-input AND gate, the second AND gate comprises a three-input AND gate, and the first selection The selector, the second selector, the third selector and the fourth selector include a two-to-one selector. 8 . The multi-chip circuit cascade communication system according to claim 7 , wherein, during the high level period of the chip select signal, two falling edges appearing continuously in the serial clock input signal form a For the trigger signal, the enable control signal of the daisy-chain mode generates a high-level pulse, and the corresponding pulse width is determined by the interval between the two falling edges. 9 . The multi-chip circuit cascade communication system according to claim 8 , wherein when the bypass input signal is at a low level, the sub-level chip is in a daisy-chain working mode; when the bypass input When the signal is high, the daisy-chain operation mode of the sub-chip is bypassed, and the serial input signal received by the sub-chip through the serial interface is directly transmitted to the serial output port of the sub-chip .

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