CN113032199B

CN113032199B - Error injection method and device for expansion bus of high-speed serial computer

Info

Publication number: CN113032199B
Application number: CN202110446810.XA
Authority: CN
Inventors: 黄玲; 李婧; 叶鹏玉; 倪亚路; 陈玉龙; 张攀勇
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2021-04-25
Filing date: 2021-04-25
Publication date: 2022-07-08
Anticipated expiration: 2041-04-25
Also published as: CN113032199A

Abstract

The invention provides a high-speed serial computer expansion bus error injection method, which is applied to a controller of a PCIe bus of a high-speed serial computer expansion bus and comprises the following steps: a register configured to record an error; sending a first request to a slave device of the PCIe bus to enable the slave device to close an automatic response function of a second request; sending a second request to the slave device to trigger the slave device to send an error injection data packet to a controller of the PCIe bus; receiving the error injection data packet; and querying the register to determine whether to process the error of the error injection data packet. The invention can flexibly inject errors into the PCIe controller, thereby flexibly verifying the processing mode of the PCIe bus on various types of errors.

Description

Error injection method and device for expansion bus of high-speed serial computer

Technical Field

The invention relates to the technical field of processors, in particular to an error injection method and device for an expansion bus of a high-speed serial computer.

Background

The PCIe bus is a widely used computer bus and has the characteristics of point-to-point, high bandwidth, reliable transmission and the like. However, the verification process of the error handling method is usually realized by adopting a normal communication process between a controller and a slave device of the PCIe bus, which is difficult to reproduce the error, and the processing method of the PCIe bus to various types of errors cannot be flexibly verified.

Disclosure of Invention

The error injection method and the device for the expansion bus of the high-speed serial computer can flexibly inject errors into the PCIe controller, thereby flexibly verifying the processing mode of the PCIe bus on various types of errors.

In a first aspect, the present invention provides a method for error injection of a high-speed serial computer expansion bus, which is applied to a controller of a PCIe bus of the high-speed serial computer expansion bus, and includes:

a register configured to record an error;

sending a first request to a slave device of the PCIe bus to enable the slave device to close an automatic response function of a second request;

sending a second request to the slave device to trigger the slave device to send an error injection data packet to a controller of the PCIe bus;

receiving the error injection data packet;

and querying the register to determine whether to process the error of the error injection data packet.

Optionally, sending a second request to the slave device to trigger the slave device to send an error injection packet to the controller of the PCIe bus comprises:

and receiving a data packet which is sent by the slave device and used for representing the closing state of the automatic response function, and sending a second request to the slave device according to the data packet so as to trigger the slave device to send an error injection data packet to a controller of the PCIe bus.

and after waiting for a preset time, sending a second request to the slave device to trigger the slave device to send an error injection data packet to the controller of the PCIe bus.

Optionally, the error injection packet is used to inject a configuration response error or a data link layer acknowledgement error to the PCIe controller.

Optionally, the register configured to record the error comprises:

configuring an error shielding register so that the register records the shielding state of the error;

the error severity register is configured to enable the register to record the severity of errors injected by error injected packets.

Optionally, before configuring the register for recording the error, the method further includes:

and configuring an interrupt register of a CPU (central processing unit) to avoid the halt of the CPU caused by the injection error of the error injection data packet, wherein the CPU is used for controlling a controller of the PCIe bus.

In a second aspect, the present invention provides an error injection device for a serial computer expansion bus, which is applied to a controller of a PCIe bus of a serial computer expansion bus, and includes:

the configuration module is used for configuring a register for recording errors;

the first request module is used for sending a first request to a slave device of the PCIe bus so as to enable the slave device to close an automatic response function of a second request;

a second request module, configured to send a second request to the slave device to trigger the slave device to send an error injection packet to the controller of the PCIe bus;

a receiving module, configured to receive the error injection data packet;

and the verification module is used for inquiring the register so as to determine whether to process the error of the error injection data packet.

Optionally, the second request module is specifically configured to receive a data packet that is sent by the slave device and used for indicating the auto-response function off state, and send a second request to the slave device according to the data packet, so as to trigger the slave device to send an error injection data packet to the controller of the PCIe bus; alternatively, the first and second electrodes may be,

the second request module is specifically configured to send a second request to the slave device after waiting for a predetermined time, so as to trigger the slave device to send an error injection data packet to the controller of the PCIe bus.

Optionally, the configuration module includes:

the shielding configuration unit is used for configuring the error shielding register so as to enable the register to record the shielding state of the error;

and the severity configuration unit is used for configuring the error severity register so that the register can record the severity of the error injected by the error injection data packet.

Optionally, the PCIe bus interface further includes an interrupt configuration module, configured to configure an interrupt register of a CPU to avoid that the CPU crashes due to an error of the error injection packet, where the CPU is configured to control the controller of the PCIe bus.

According to the technical scheme provided by the invention, the automatic response of the slave equipment to the second request is closed through the first request, and then the second request is sent. According to the invention, error injection can be flexibly carried out by controlling the error injection data packet, so that the error processing of PCIe can be flexibly verified.

Drawings

FIG. 1 is a flowchart illustrating a method for error injection of an expansion bus of a high-speed serial computer according to an embodiment of the present invention;

FIG. 2 is a flowchart illustrating the specific interaction of the error injection method for the high-speed serial computer expansion bus applied to the data link layer of the programmable PCIe device in accordance with another embodiment of the present invention;

FIG. 3 is a specific interaction flowchart of an error injection method for a high-speed serial computer expansion bus applied to a data link layer of an FPGA according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating the specific interaction of a high-speed serial computer expansion bus error injection method applied to the configuration response error injection of a programmable PCIe device in accordance with another embodiment of the present invention;

FIG. 5 is a specific interaction flowchart of the error injection method for the high-speed serial computer expansion bus applied to the configuration response of the FPGA according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating an error injection apparatus for an expansion bus of a high-speed serial computer according to an embodiment of the present invention;

FIG. 7 is a diagram of an application environment of a high-speed serial computer expansion bus error injection method according to another embodiment of the present invention;

FIG. 8 is a diagram of an application environment of a method for error injection of a high-speed serial computer expansion bus according to another embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The embodiment of the invention provides an error injection method for an expansion bus of a high-speed serial computer, which is applied to a controller of a PCIe bus of the expansion bus of the high-speed serial computer, and as shown in figure 1, the error injection method comprises the following steps:

step 101, configuring a register for recording errors; in some embodiments, the register for recording the error is usually written with a predetermined value when the error occurs, and in the subsequent verification process, whether the corresponding error occurs can be determined by verifying the value of the register.

Step 102, sending a first request to a slave device of the PCIe bus so as to enable the slave device to close a response function of a second request; in some embodiments, the slave device turning off the response function to the second request means that the slave device turns off the automatic response to the second request. Those skilled in the art will appreciate that the slave device is still able to respond to the second request in a controlled state after the response function for the second request is turned off.

Step 103, sending a second request to the slave device to trigger the slave device to send an error injection data packet to the controller of the PCIe bus; in some embodiments, since the response to the second request is turned off in step 102, the slave device does not automatically respond to the second request, which provides a condition for flexibly performing error injection. To inject an error into the PCIe controller, the slave device may be controlled to send the error injection packet in a controlled state.

Step 104, receiving the error injection data packet; in some embodiments, the PCIe controller, upon receiving the error-filled packet, responds to the error in the error-filled packet and processes the error, and during the processing, the processing is recorded in the register in step 101.

Step 105, querying the register to determine whether to process the error of the error-injected data packet. In some embodiments, because the error handling is logged in step 104, a query to the register may determine the error handling by the PCIe controller. And comparing the processing process with the processing mode specified in the standard, if the processing modes are consistent, indicating that the PCIe controller can successfully process the error, and if the processing modes are inconsistent, indicating that the PCIe controller cannot successfully process the error.

According to the technical scheme provided by the embodiment of the invention, the response of the slave equipment to the second request is closed through the first request, and then the second request is sent. According to the invention, error injection can be flexibly carried out by controlling the error injection data packet, so that the error processing of PCIe can be flexibly verified.

As an optional implementation, the sending a second request to the slave device to trigger the slave device to send an error injection packet to the controller of the PCIe bus includes:

and receiving a data packet which is sent by the slave device and used for representing the response function closing state, and sending a second request to the slave device according to the data packet so as to trigger the slave device to send an error injection data packet to the controller of the PCIe bus.

In some embodiments, since the second request needs to be sent after the response function of the slave device is turned off, sending a data packet by the slave device triggers sending of the second request, thereby ensuring that the second request is sent after the response function is turned off.

In some embodiments, since the second request needs to be sent after the response function of the slave device is turned off, in this embodiment, the sending of the second request is ensured after the response is turned off by waiting for a predetermined time.

In a preferred embodiment, the error injection packet is used to inject a configuration response error or a data link layer acknowledgement error into the PCIe controller.

As an alternative embodiment, the register configured to record the error comprises:

In some embodiments, the error mask register generally has two states, an enabled state and a disabled state, in which one of the two states masks the corresponding error so that the error is not processed and does not generate an error flag in the error severity register, and the other does not mask the corresponding error so that the error is processed and generates an error flag in the error severity register. The two states in the error mask register can control the error severity register, and the error severity register can record the corresponding error processing process.

In some embodiments, if the error is an uncorrectable error, the CPU is easily interrupted to cause the test system to crash, so that in this embodiment, the interrupt register of the CPU is configured to avoid the CPU from crashing, thereby implementing the verification of the error handling mode.

Fig. 2 shows an error injection method for injecting a data link layer response error into a high-speed serial computer expansion bus and a response mode of a programmable PCIe device for the error injection method, taking an interaction between a PCIe controller and a programmable PCIe device as an example, specifically as follows:

in step 201, the PCIe controller configures interrupt registers to be set, for example, to configure the RAS-related registers for reliability, availability, and service capability to avoid a crash.

At step 202, the PCIe controller configures a register for logging errors, such as configuring the value of an advanced error reporting AER control module register.

In step 203, the PCIe controller sends a first request to the slave device, for example, sends a memory write request to the programmable PCIe device.

Step 204, the slave device receives the first request, and closes the response to the second request according to the first request, for example, after the programmable PCIe device receives the memory write request, the function of automatically replying ACK/NAK DLLP is closed.

Step 205, the slave device sends a packet indicating the response function off status, for example, after the programmable PCIe device turns off the auto-reply ACK/NAK DLLP setting into effect, it sends a vector-Specific DLLP to the PCIe controller.

In step 206, the PCIe controller detects whether a packet indicating the response function off status is received, for example, the PCIe controller detects whether a Vendor-Specific DLLP is received.

Step 207, receiving the data packet sent by the slave device to indicate the response function shutdown state, and sending a second request to the slave device according to the data packet, for example, sending a memory read request after the PCIe controller receives the Vendor-Specific DLLP.

Step 208, after receiving the second request, the slave device sends an error injection packet in a controlled state to inject a data link layer response error to the PCIE controller, for example, the programmable PCIE device responds to the memory read request, and replies a DLLP with an AckNak _ SeqNum field having an error value of 2184, so as to inject a data link layer response error to the PCIE controller.

At step 209, the slave device's response function to the second request is resumed, e.g., the function of turning on the programmable PCIe device to automatically reply to ACK/NAK DLLP.

Step 210, querying the register to determine whether to process the error of the error-injected data packet. For example, the PCIe controller performs an AER error check step.

Fig. 3 illustrates, by taking an interaction between a PCIe controller and a field programmable gate array FPGA as an example, an error injection method for injecting a data link layer response error into a high-speed serial computer expansion bus and a response mode of the FPGA for the error injection method specifically as follows:

in step 301, the PCIe controller configures interrupt registers to be set, for example, to configure trust, availability, and service capability RAS related registers to avoid a crash.

At step 302, the PCIe controller configures a register for logging errors, such as the value of the advanced error report AER control module register.

In step 303, the PCIe controller sends a first request to the slave device, for example, sends a memory write request to the field programmable gate array FPGA.

Step 304, the slave device receives the first request, and closes the response to the second request according to the first request, for example, after the field programmable gate array FPGA receives the memory write request, the function of automatically replying ACK/NAK DLLP is closed.

At step 305, the PCIe controller waits a predetermined time, e.g., 100 milliseconds after the PCIe controller delays, for the FPGA device to turn off the function of auto-reply ACK/NAK DLLP into effect.

Step 306, sending a second request to the slave device, for example, sending a memory read request to the slave device after the latency of 100 milliseconds is completed.

Step 307, after receiving the second request, the slave device sends an error injection packet in a controlled state to inject a data link layer response error to the PCIE controller, for example, the field programmable gate array FPGA responds to the memory read request, and replies a DLLP with an error value of 2184 in the AckNak _ SeqNum field, so as to inject a data link layer response error to the PCIE controller.

And step 308, restoring the response function of the slave device to the second request, for example, the function of automatically replying ACK/NAK DLLP by opening the field programmable gate array FPGA.

Step 309, the register is queried to determine whether to process the error of the error-injected data packet. For example, the PCIe controller performs AER error checking steps.

In the above two examples, after injecting a data link layer response error to the PCIE controller, it may be checked whether the triggered error meets expectations through two checkpoints:

checkpoint 1: based on the value of the uncorrectable error severity register, it is checked whether the corresponding error processing has been performed according to the set severity.

Checkpoint 2: based on the value of the uncorrectable error mask register, it is checked whether error information is generated. If the value is set to 0x0, an error message is generated; if this value is set to 0x1, no error information is generated.

Fig. 4 shows an error injection method for injecting configuration response errors into a high-speed serial computer expansion bus and a response mode of a programmable PCIe device for the error injection method, taking interaction between a PCIe controller and a programmable PCIe device as an example, specifically as follows:

step 401, the PCIe controller configures an interrupt register to set up, so as to avoid a crash.

At step 402, the PCIe controller configures registers for error logging, such as root port DPC RPPIO related registers of the downstream port connector.

At step 403, the PCIe controller sends a first request to the slave device, for example, sends a memory read request to the programmable PCIe device.

Step 404, receiving the first request from the device, and closing the response to the second request according to the first request, for example, after the programmable PCIe device receives the memory read request, setting to stop the interaction with the configuration request automatically.

Step 405, the slave device sends a data packet indicating the response function shutdown status, for example, after the programmable PCIe device stops the setting of the automatic interaction with the configuration request from being effective, the slave device sends a memory write request to the PCIe controller.

In step 406, the PCIe controller detects whether a data packet indicating the response function off status is received, for example, the PCIe controller detects whether a memory write request sent by the programmable PICE device is received.

Step 407, receiving a data packet sent by the slave device and used for indicating the response function closed state, and sending a second request to the slave device according to the data packet, for example, after receiving a memory write request sent by a programmable PCIe device, the PCIe controller sends a configuration read request to the programmable PCIe device.

Step 408, after receiving the second request, the slave device sends an error injection packet in the controlled state to inject a configuration response error into the PCIE controller, for example, the programmable PCIE device responds to the configuration read request to reply a complete packet CPL, and the status bit in the CPL is the request status UR state that is not supported, so as to inject the configuration response error into the PCIE controller.

Step 409, the register is queried to determine whether to process the error of the error-injected data packet. For example, the PCIe controller performs a root port DPC RPPIO related register error checking step of the downstream port connector.

Fig. 5 shows an error injection method for injecting configuration response errors into a high-speed serial computer expansion bus and a response mode of the field programmable gate array FPGA for the error injection method, taking the interaction between the PCIe controller and the field programmable gate array FPGA as an example, specifically as follows:

step 501, the PCIe controller configures an interrupt register to set up, so as to avoid a crash.

At step 502, the PCIe controller configures registers for error logging, such as root port DPC RPPIO related registers of the downstream port connector.

In step 503, the PCIe controller sends a first request to the slave device, for example, sends a memory read request to the field programmable gate array FPGA.

Step 504, the slave device receives the first request, and closes the response to the second request according to the first request, for example, after the FPGA receives the memory read request, the interaction with the configuration request is set to stop automatically.

At step 505, the PCIe controller waits a predetermined time, e.g., the PCIe controller delays 100 milliseconds, to ensure that the settings that the FPGA device stops automatically interacting with the configuration request are in effect.

At step 506, a second request is sent to the slave device, for example, a configuration read request is sent to the FPGA after a wait time of 100 milliseconds has elapsed.

Step 507, after receiving the second request, the slave device sends an error injection packet in the controlled state to inject a configuration response error into the PCIE controller, for example, the programmable PCIE device responds to the configuration read request to reply a complete packet CPL, and the status bit in the CPL is the request status UR state that is not supported, so as to inject the configuration response error into the PCIE controller.

Step 508, the register is queried to determine whether to handle errors of the error-injected data packet. For example, the PCIe controller performs DPC RPPIO related register error checking steps.

Similar to the embodiments shown in fig. 2 and 3, after the embodiments shown in fig. 4 and 5 inject configuration response errors for a PCIE controller, it can be checked whether the errors occurred meet expectations through two checkpoints:

checkpoint 1: according to the value of a completion data packet Cfg UR Cpl with the PCIe protocol transaction layer state UR in an RPPIO error shielding register, whether an error is recorded in a PRPIO error log register or not is checked, and whether a first error pointer of the RPPIO in a DPC state register needs to be turned over or not is checked.

Checkpoint 2: according to the value of Cfg UR Cpl in the RPPIO error severity register, the processing error level is checked, whether DPC has been triggered or not is checked, and whether the link training state machine has been shut down or not is checked.

The embodiment of the invention provides a high-speed serial computer expansion bus fault injection device, which is applied to a controller of a PCIe bus of a high-speed serial computer expansion bus, and as shown in FIG. 6, the device comprises:

the configuration module is used for configuring a register for recording errors; in some embodiments, the register for recording the error is usually written with a predetermined value when the error occurs, and in the subsequent verification process, whether the corresponding error occurs can be determined by verifying the value of the register.

The first request module is used for sending a first request to a slave device of the PCIe bus so as to enable the slave device to close the response function of a second request; in some embodiments, the slave device turning off the response function to the second request means that the slave device turns off the automatic response to the second request. Those skilled in the art will appreciate that the slave device is still able to respond to the second request in a controlled state after the response function for the second request is turned off.

A second request module, configured to send a second request to the slave device to trigger the slave device to send an error injection packet to the controller of the PCIe bus; in some embodiments, since the response to the second request is turned off in step 102, the slave device does not automatically respond to the second request, which provides a condition for flexibly performing error injection. To inject an error into the PCIe controller, the slave device may be controlled to send the error injection packet in a controlled state.

A receiving module, configured to receive the error injection data packet; in some embodiments, the PCIe controller, after receiving the error injection packet, responds to an error in the error injection packet, and processes the error, and during the processing, the processing is recorded in a register in the configuration module.

And the verification module is used for inquiring the register so as to determine whether to process the error of the error injection data packet. In some embodiments, because the error handling is recorded in the receiving module, querying the register may determine the error handling by the PCIe controller. And comparing the processing process with the processing mode specified in the standard, if the processing modes are consistent, indicating that the PCIe controller can successfully process the error, and if the processing modes are inconsistent, indicating that the PCIe controller cannot successfully process the error.

As an optional implementation manner, the second request module is specifically configured to receive a data packet sent by the slave device and used for indicating the response function off state, and send a second request to the slave device according to the data packet, so as to trigger the slave device to send an error injection data packet to the controller of the PCIe bus. In some embodiments, since the second request needs to be sent after the response function of the slave device is turned off, sending a data packet by the slave device triggers sending of the second request, thereby ensuring that the second request is sent after the response function is turned off. Alternatively, the first and second electrodes may be,

the second request module is specifically configured to send a second request to the slave device after waiting for a predetermined time, so as to trigger the slave device to send an error injection data packet to the controller of the PCIe bus. In some embodiments, since the second request needs to be sent after the response function of the slave device is turned off, in this embodiment, it is ensured that the second request is sent after the response is turned off by waiting for a predetermined time.

As an optional implementation, the configuration module includes:

As an optional implementation manner, the apparatus further includes an interrupt configuration module, configured to configure an interrupt register of a CPU, so as to avoid a crash of the CPU caused by an error of the error injection packet, where the CPU is configured to control a controller of the PCIe bus.

Fig. 7 is a schematic diagram of an application environment in which the foregoing method and apparatus are applied in an interaction process between a PCIE controller and a programmable PCIE device, where the PCIE controller is disposed on a CPU and is driven by a test program, and the programmable PCIE device is driven by a programmable PCIE device control program.

Fig. 8 is a schematic diagram of an application environment applying the foregoing method and apparatus in an interactive process between a PCIe controller and an FPGA, where the PCIe controller is disposed on a CPU and driven by a test program, and the FPGA is driven by an FPGA control program.

It will be understood by those skilled in the art that all or part of the processes of the embodiments of the methods described above may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A high-speed serial computer expansion bus error injection method is characterized in that a controller applied to a PCIe bus of a high-speed serial computer expansion bus comprises the following steps:

a register configured to record an error;

receiving the error injection data packet;

2. The method of claim 1, wherein sending a second request to the slave device to trigger the slave device to send an error injection packet to a controller of the PCIe bus comprises:

3. The method of claim 1, wherein sending a second request to the slave device to trigger the slave device to send an error injection packet to a controller of the PCIe bus comprises:

4. The method of claim 1, wherein the error-injected packet is used to inject a configuration response error or a data link layer acknowledgement error into the PCIe controller.

5. The method of claim 1, wherein configuring the register to record the error comprises:

6. The method of claim 1, wherein configuring the register for logging errors further comprises, prior to:

7. The utility model provides a high speed serial computer expansion bus notes mistake device which characterized in that, is applied to the controller of high speed serial computer expansion bus PCIe bus, includes:

a receiving module, configured to receive the error injection data packet;

8. The apparatus according to claim 7, wherein the second request module is specifically configured to receive a packet sent by the slave device to indicate the auto-response function off status, and send a second request to the slave device according to the packet, so as to trigger the slave device to send an error-injecting packet to the controller of the PCIe bus; alternatively, the first and second electrodes may be,

9. The apparatus of claim 7, wherein the configuration module comprises:

10. The apparatus of claim 7, further comprising an interrupt configuration module configured to configure an interrupt register of a CPU to prevent the CPU from crashing due to the error injected by the error-injected packet, wherein the CPU is configured to control a controller of the PCIe bus.