CN113014519A - Method for avoiding frequency spectrum zero in double-pulse forming transmitting system - Google Patents

Method for avoiding frequency spectrum zero in double-pulse forming transmitting system Download PDF

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CN113014519A
CN113014519A CN202110243536.6A CN202110243536A CN113014519A CN 113014519 A CN113014519 A CN 113014519A CN 202110243536 A CN202110243536 A CN 202110243536A CN 113014519 A CN113014519 A CN 113014519A
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李航
程知群
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Hangzhou Dianzi University
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202Channel estimation
    • H04L25/022Channel estimation of frequency response
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202Channel estimation
    • H04L25/024Channel estimation channel estimation algorithms
    • H04L25/0242Channel estimation channel estimation algorithms using matrix methods
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202Channel estimation
    • H04L25/024Channel estimation channel estimation algorithms
    • H04L25/0256Channel estimation using minimum mean square error criteria
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006Arrangements for removing intersymbol interference

Abstract

The invention discloses a method for avoiding a frequency spectrum zero point in a double-pulse forming transmitting system, which comprises the following steps: s10, setting an initial value for the clock phase of the analog-to-digital conversion module of the second path in the receiving end; s20, sending a test signal at the transmitting end; s30, estimating the frequency response of the channel at the receiving end, further calculating the signal-to-noise ratio of the balanced signal and recording the signal-to-noise ratio; s40, adjusting the clock phase of the analog-to-digital conversion module in S10 to obtain the receiving signals with different delays or advanced samples; s50, repeating the steps S20-S40, and determining the clock phase corresponding to the maximum signal-to-noise ratio. The invention adjusts the sampling clock phase of the analog-digital conversion device at the receiving end through off-line static calibration or on-line adaptive calibration, namely, samples the received signal in advance or in delay, so as to avoid the frequency spectrum zero point which may appear in the channel frequency response and provide strong robust performance for a point-to-point high-speed wireless transmission system.

Description

Method for avoiding frequency spectrum zero in double-pulse forming transmitting system
Technical Field
The invention belongs to the field of digital signal processing of a wireless communication system, and relates to a method for avoiding a frequency spectrum zero point in a double-pulse forming transmitting system.
Background
In a traditional digital single carrier communication system, nyquist pulse shaping is generally adopted at a transmitting end. Accordingly, the receiving end uses matched filtering to avoid inter-symbol interference introduced by non-ideal channels, thereby maximizing the received signal-to-noise ratio. Raised cosine pulses, which are a typical class of nyquist pulses, are widely used in digital transmission systems and are equivalently implemented by employing root raised cosine filters, respectively, at the transmitting and receiving ends. Wherein an important parameter of the filter, i.e. the roll-off coefficient, determines the actual transmission bandwidth of the signal and the spectral efficiency of the system. A smaller roll-off factor results in higher spectral efficiency, but in practical high-speed transmission systems, such a root-raised cosine filter is extremely difficult to design and implement. On the other hand, a large signal bandwidth is also a necessary condition for realizing a high-speed transmission system. The millimeter wave and terahertz frequency bands are between 30GHz and 10THz, which are considered to be excellent choices for achieving this goal. Although conventional nyquist pulse shaping can achieve intersymbol interference free transmission in theory, large bandwidth signals require data conversion devices with rather high sampling rates to meet the sampling requirements, and data conversion devices that are currently available in the market to meet the requirements are scarce and expensive.
In order to improve the spectral efficiency of the system and to solve the problem of difficult acquisition of high sampling rate devices, methods based on double pulse shaped emission are proposed. The method can carry out combined emission on two half symbol rate data streams with overlapped frequency spectrums under the condition of no intersymbol interference and no data stream interference, and theoretically realize full-rate transmission. Due to various distortions in wireless channel transmission, it becomes necessary to employ equalization techniques at the receiving end to remove intersymbol interference and intersymbol interference. The conventional fractionally spaced equalization technique requires a sampling rate higher than a data symbol rate and high implementation cost and complexity, which makes it extremely difficult to realize high-speed transmission using the data conversion device that is currently mainstream.
On the other hand, the symbol interval equalization technology performs symbol rate sampling equalization on the received signal, so that the requirement of high-speed transmission on a high-sampling-rate device can be reduced. Therefore, it is favored to use low complexity linear symbol interval equalization techniques in high speed transmission systems based on double pulse shaping transmission. However, since the roll-off coefficient of the filter used for symbol interval equalization is greater than zero, sampling at the symbol rate often causes edge overlapping of the signal spectrum, even generates a spectrum zero point, thereby greatly reducing the equalization performance of the system.
Disclosure of Invention
In order to solve the above problems, the double-pulse forming transmission system of the present invention includes a transmitting end and a receiving end, wherein the transmitting end includes a code modulation module, a serial-to-parallel conversion module, two analog-to-digital conversion modules, two pulse forming filters and a transmitting filter, the code modulation module performs coding and modulation mapping to data symbols, the data symbol stream is divided into two parallel half-rate symbol streams by the serial-to-parallel conversion module, each digital signal is converted into an analog signal by the digital-to-analog conversion module, each half-rate symbol stream is pulse-formed by one pulse forming filter, and the combined half-rate symbol streams are output as a transmitting signal by the transmitting filter; the receiving end comprises a receiving filter, two paths of analog-to-digital conversion modules, a channel estimation module, two paths of equalizers, a parallel-to-serial conversion module and a demodulation decoding module, wherein received baseband signals are filtered by the receiving filter, the two paths of analog-to-digital conversion modules convert output analog signals into digital signals, and the channel estimation module respectively estimates output symbols of the two paths of analog-to-digital conversion modules and outputs the estimated output symbols to equivalent channel frequency responses of the two pulse shaping filters and sends the equivalent channel frequency responses to the two paths of equalizers; meanwhile, the channel estimation module calculates the signal-to-noise ratio, determines the optimal clock phase of the analog-to-digital conversion module, and feeds back the optimal clock phase to a second analog-to-digital conversion module in the two paths of analog-to-digital conversion modules to adjust the clock phase; the two paths of equalizers respectively equalize the two paths of digital signals by using the channel frequency response estimation values output by the channel estimation module, the parallel-serial conversion module performs parallel-serial conversion on the signals output by the two paths of equalizers to obtain a path of symbols and outputs the path of symbols to the demodulation decoding module, and the demodulation decoding module performs demapping and decoding on the symbols to obtain sent bit data;
based on the system, the method for avoiding the frequency spectrum zero point comprises the following steps:
s10, setting an initial value for the clock phase of the analog-to-digital conversion module of the second path in the receiving end;
s20, sending a test signal at the transmitting end;
s30, estimating the frequency response of the channel at the receiving end, further calculating the signal-to-noise ratio of the balanced signal and recording the signal-to-noise ratio;
s40, adjusting the clock phase of the analog-to-digital conversion module in S10 to obtain the receiving signals with different delays or advanced samples;
s50, repeating the steps S20-S40, and determining the clock phase corresponding to the maximum signal-to-noise ratio.
Preferably, in S40, the clock phase of the receiving-end analog-to-digital conversion module is adjusted through off-line static calibration or on-line adaptive calibration.
Preferably, in S10, an initial value is set for the clock phase of the analog-to-digital conversion module of the second path in the receiving end, where the clock phase of the analog-to-digital conversion module of the first path is fixed to 0.
Preferably, the S20, sending a test signal at the transmitting end, includes the following steps:
s21, the input test signal bit is coded and modulated and mapped to the symbol by the code modulation module, the corresponding symbol rate is 1/TsThe symbol stream is divided into two parallel half-rate symbol streams by a serial-to-parallel conversion module, and the Fourier transform of the symbol stream is expressed as S1(ej2ω) And S2(ej2ω);
S22, converting the two paths of digital symbols into analog signals through D/A conversion modules respectively
Figure BDA0002963220250000031
And
Figure BDA0002963220250000032
corresponding to a sampling rate of 1/2TsWhere ω and f denote digital and analog frequencies, respectively, and ω is 2 ω fTs
S23, the two analog signals are respectively processed by two pulse shaping filters to carry out double pulse shaping, wherein, the bandwidth is (1+ beta)/2TsRoot raised cosine pulse hRRC(t) and hRR+(t-Ts) Shaped pulses as two-way pulse shaping filters, respectively, where hRRC(t) corresponding frequency domain response HRRC(f) Is shown as
Figure BDA0002963220250000033
Wherein, beta is more than or equal to 0 and less than or equal to 1 represents the roll-off coefficient of the pulse shaping filter, and the two shaping pulses are combined and then output to a transmitting test signal through the transmitting filter.
Preferably, the S30, estimating the frequency response of the channel at the receiving end, further calculating the snr of the equalized signal and recording the snr, includes the following steps:
s31, the transmitted test signal reaches the receiving end after passing through the physical channel and is output through the receiving filter;
s32, the output analog signals are respectively passed through two analog-to-digital conversion modules to obtain two digital signals, and the corresponding sampling rate is 1/2TsThe output digital signal is processed by a channel estimation module to obtain the frequency response estimation of a digital equivalent channel
Figure BDA0002963220250000041
And
Figure BDA0002963220250000042
Figure BDA0002963220250000043
Figure BDA0002963220250000044
wherein the content of the first and second substances,
Figure BDA0002963220250000045
and
Figure BDA0002963220250000046
respectively representing signals
Figure BDA0002963220250000047
And
Figure BDA0002963220250000048
frequency domain response estimation of a simulated equivalent channel formed by a double-pulse shaping receiving filter and a physical channel, (tau +1) TsAnd the sampling time delay of the second path of analog-to-digital conversion module relative to the first path of analog-to-digital conversion module is represented, wherein tau is more than or equal to-1 and less than or equal to 1, and when the ratio rho of the average power of a transmitting end to the noise power of a receiving end is known, the signal-to-noise ratio of the minimum mean square error equalization signal is calculated in a channel estimation module as follows:
Figure BDA0002963220250000049
wherein the content of the first and second substances,
Figure BDA00029632202500000410
C(ω,τ)=HH(ω,τ)(H(ω,τ)HH(ω,τ)+I/ρ)-1 (6)
wherein I represents an identity matrix, Tr {. and {. The { }HRespectively representing the trace and transposed conjugate of the matrix.
The invention has at least the following beneficial effects: a method of avoiding spectral nulls in a double pulse shaping transmit system is provided. The method adjusts the sampling clock phase of an analog-digital conversion device at a receiving end through off-line static calibration or on-line adaptive calibration, namely, samples a received signal in advance or in a delayed manner so as to avoid frequency spectrum zero possibly appearing in channel frequency response and provide strong robust performance for a point-to-point high-speed wireless transmission system.
Drawings
Fig. 1 is a schematic structural diagram of a transmitting end of a double pulse forming transmitting system according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a receiving end structure of a double-pulse forming transmitting system according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating steps of a method for avoiding spectral nulls in a dual pulse forming transmitter system in accordance with an embodiment of the present invention;
fig. 4 is a graph showing a relationship between a signal-to-noise ratio gain of an MMSE equalized signal and a normalized sampling delay according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
On the contrary, the invention is intended to cover alternatives, modifications, equivalents and alternatives which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, certain specific details are set forth in order to provide a better understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details.
The invention relates to a method for avoiding possible spectral nulls in a double-pulse forming transmission system, which is executed by a transmitting terminal 10 and a receiving terminal 20. Fig. 1 and 2 show block diagrams of a double pulse shaping transmitting terminal 10 and a receiving terminal 20, respectively. For convenience, the radio frequency chain, including up-and down-converters, high power amplifiers and low noise amplifiers are not shown in the block diagrams of fig. 1 and 2.
In fig. 1, input bit data is first encoded and modulated by the code modulation module 101 to be mapped to data symbols, and the corresponding symbol rate is 1/TsHere TsRepresenting a symbol period. The data symbol stream is split into two parallel half-rate symbol streams by serial-to-parallel conversion module 102. Each path of digital signal is converted into an analog signal by the digital-to-analog conversion module 103, and the corresponding sampling rate is 1/2Ts. The half-rate symbol streams are pulse-shaped by respective pulse-shaping filters 104, combined and output a transmit signal by a transmit filter 106.
In fig. 2, a received baseband signal is first filtered by a reception filter 201. Converting the output analog signal into a number by using two analog-to-digital conversion modules 202Word signal corresponding to a sampling rate of 1/2Ts. The channel estimation module 203 estimates the equivalent channel frequency responses corresponding to the two paths of pulse shaping filters 104 by using the output symbols of the two paths of analog-to-digital conversion modules 202, and sends the equivalent channel frequency responses to the two paths of equalizers 204. Meanwhile, the channel estimation module 203 calculates the signal-to-noise ratio, determines the optimal clock phase of the second channel analog-to-digital conversion module 202, and feeds back the optimal clock phase to the second channel analog-to-digital conversion module 202 to adjust the clock phase. The equalizer 204 equalizes the two paths of digital signals respectively by using the channel frequency response estimation value output by the channel estimation module 203. The parallel-to-serial conversion module 206 performs parallel-to-serial conversion on the two equalized signals to obtain a signal with a rate of 1/TsThe symbol of (2). Finally, the demodulation decoding module 207 performs demapping and decoding on the symbols to obtain the transmitted bit data.
The flow of the method is shown in fig. 3, and comprises the following steps:
s10, setting an initial value for the clock phase of the analog-to-digital conversion module 202 of the second path of signal at the receiving end, for example, delaying the sampling for one symbol period Ts. Here, the clock phase of the first analog-to-digital conversion module 202 is fixed to 0.
S20, the transmitting terminal 10 sends a test signal. The method comprises the following steps:
s21, the input test signal bit is coded and modulated and mapped to the symbol by the code modulation module, the corresponding symbol rate is 1/TsThe symbol stream is divided into two parallel half-rate symbol streams by a serial-to-parallel conversion module, and the Fourier transform of the symbol stream is expressed as S1(ej2ω) And S2(ej2ω);
S22, converting the two paths of digital symbols into analog signals through D/A conversion modules respectively
Figure BDA0002963220250000061
And
Figure BDA0002963220250000062
corresponding to a sampling rate of 1/2TsWhere ω and f denote digital and analog frequencies, respectively, and ω ═ 2 pi fTs
S23, the two analog signals are respectively processed by two pulse shaping filters to carry out double pulse shaping, wherein, the bandwidth is (1+ beta)/2TsRoot raised cosine pulse hRRC(t) and hRRC(t-Ts) Shaped pulses as two-way pulse shaping filters, respectively, where hRRC(t) corresponding frequency domain response HRRC(f) Is shown as
Figure BDA0002963220250000071
Wherein, beta is more than or equal to 0 and less than or equal to 1 represents the roll-off coefficient of the pulse shaping filter, and the two shaping pulses are combined and then output to a transmitting test signal through the transmitting filter.
S30, estimating the frequency response of the channel at the receiving end, further calculating and recording the signal-to-noise ratio of the equalized signal, including the following steps:
s31, the transmitted test signal reaches the receiving end after passing through the physical channel and is output through the receiving filter;
s32, the output analog signals are respectively passed through two analog-to-digital conversion modules to obtain two digital signals, and the corresponding sampling rate is 1/2TsThe output digital signal is processed by a channel estimation module to obtain the frequency response estimation of a digital equivalent channel
Figure BDA0002963220250000072
And
Figure BDA0002963220250000073
Figure BDA0002963220250000074
Figure BDA0002963220250000075
wherein the content of the first and second substances,
Figure BDA0002963220250000076
and
Figure BDA0002963220250000077
respectively representing signals
Figure BDA0002963220250000078
And
Figure BDA0002963220250000079
frequency domain response estimation of a simulated equivalent channel formed by a double-pulse shaping receiving filter and a physical channel, (tau +1) TsAnd the sampling time delay of the second path of analog-to-digital conversion module relative to the first path of analog-to-digital conversion module is represented, wherein tau is more than or equal to-1 and less than or equal to 1, and when the ratio rho of the average power of a transmitting end to the noise power of a receiving end is known, the signal-to-noise ratio of the minimum mean square error equalization signal is calculated in a channel estimation module as follows:
Figure BDA00029632202500000710
Figure DA00029632202535473794
wherein the content of the first and second substances,
Figure BDA0002963220250000082
C(ω,τ)=HH(ω,τ)(H(ω,τ)HH(ω,τ)+I/ρ)-1 (6)
wherein I represents an identity matrix, Tr {. and {. The { }HRespectively representing the trace and transposed conjugate of the matrix.
S40, the receiving end 20 adjusts the clock phase of the second analog-to-digital conversion module 202 to obtain the received signal with different delay or advanced sampling.
And S51, judging whether the signal-to-noise ratio calculated in S30 is the maximum signal-to-noise ratio. If not, repeating S20-S40; if so, the optimal phase of the clock is determined and output in S52, and the clock phase of the second analog-to-digital conversion module 202 is finally set.
In order to evaluate the robustness of the scheme for avoiding the spectrum zero in the double-pulse forming transmission system, computer simulation is performed on the signal-to-noise ratio gain of the equalized signal of MMSE (minimum mean square error) under different sampling time delays when the second path of analog-to-digital conversion module 202 adopts different clock phases. Wherein, the signal-to-noise ratio gain G of the equalized signalM5S7Defined as the sampling time delay of the second path of analog-to-digital conversion module 202 is (tau +1) TsThe signal-to-noise ratio and the sampling time delay of the time-balanced signal are TsThe ratio of the signal-to-noise ratio of the time-equalized signal can be calculated and expressed as
Figure BDA0002963220250000083
In the simulation, the physical channel used introduced a 90 degree phase shift to the transmitted signal, i.e. the physical channel used introduced a 90 degree phase shift to the transmitted signal
Figure BDA0002963220250000084
This causes a null at the edge of the signal spectrum after analog-to-digital conversion, thereby degrading the receiver performance.
Fig. 4 is a computer simulation result of the MMSE equalized signal-to-noise ratio gain versus the normalized sampling delay according to the scheme provided by the present invention. Wherein the sampling time delay is normalized to TsAnd (6) normalizing. It is assumed that the frequency response estimate of the digital equivalent channel in step 303 can be accurately obtained with a sum p of 27 dB. As can be seen from fig. 4, for any roll-off coefficient, the signal-to-noise ratio gain of the equalized signal can reach the maximum value by adjusting the sampling delay of the second received signal, i.e., the clock phase of the second analog-to-digital conversion module 202, to an optimal value. The value of the maximum increases with increasing roll-off factor. When the roll-off factor is 0, the maximum value of the snr gain of the equalized signal is 6.6dB, which occurs when the normalized sampling delay is 0.07,0.93,1.07 and 1.93. When rolling down systemThe maximum value of the snr gain of the equalized signal is 9.5dB for a number of 1, which occurs at normalized sampling delays of 0.5 and 1.5.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (5)

1. A method for avoiding the zero point of frequency spectrum in a double-pulse forming transmitting system is characterized in that the double-pulse forming transmitting system comprises a transmitting end and a receiving end, wherein the transmitting end comprises a code modulation module, a serial-parallel conversion module, two analog-to-digital conversion modules, two pulse forming filters and a transmitting filter, the code modulation module carries out coding and modulation mapping to data symbols, the data symbol streams are divided into two parallel half-rate symbol streams through the serial-parallel conversion module, each digital signal is converted into an analog signal through the digital-to-analog conversion module, each half-rate symbol stream is subjected to pulse forming through one pulse forming filter, and the combined signals are output through the transmitting filter; the receiving end comprises a receiving filter, two paths of analog-to-digital conversion modules, a channel estimation module, two paths of equalizers, a parallel-to-serial conversion module and a demodulation decoding module, wherein received baseband signals are filtered by the receiving filter, the two paths of analog-to-digital conversion modules convert output analog signals into digital signals, and the channel estimation module respectively estimates output symbols of the two paths of analog-to-digital conversion modules and outputs the estimated output symbols to equivalent channel frequency responses of the two pulse shaping filters and sends the equivalent channel frequency responses to the two paths of equalizers; meanwhile, the channel estimation module calculates the signal-to-noise ratio, determines the optimal clock phase of the analog-to-digital conversion module, and feeds back the optimal clock phase to a second analog-to-digital conversion module in the two paths of analog-to-digital conversion modules to adjust the clock phase; the two paths of equalizers respectively equalize the two paths of digital signals by using the channel frequency response estimation values output by the channel estimation module, the parallel-serial conversion module performs parallel-serial conversion on the signals output by the two paths of equalizers to obtain a path of symbols and outputs the path of symbols to the demodulation decoding module, and the demodulation decoding module performs demapping and decoding on the symbols to obtain sent bit data;
based on the system, the method for avoiding the frequency spectrum zero point comprises the following steps:
s10, setting an initial value for the clock phase of the analog-to-digital conversion module of the second path in the receiving end;
s20, sending a test signal at the transmitting end;
s30, estimating the frequency response of the channel at the receiving end, further calculating the signal-to-noise ratio of the balanced signal and recording the signal-to-noise ratio;
s40, adjusting the clock phase of the analog-to-digital conversion module in S10 to obtain the receiving signals with different delays or advanced samples;
s50, repeating the steps S20-S40, and determining the clock phase corresponding to the maximum signal-to-noise ratio.
2. The method according to claim 1, wherein in S40, the clock phase of the receiving-end analog-to-digital conversion module is adjusted by off-line static calibration or on-line adaptive calibration.
3. The method according to claim 1, wherein at S10, an initial value is set for the clock phase of the analog-to-digital conversion module of the second path in the receiving end, and the clock phase of the analog-to-digital conversion module of the first path is fixed to 0.
4. The method of claim 1, wherein said S20, sending a test signal at the transmitting end, comprises the steps of:
s21, the input test signal bit is coded and modulated and mapped to the symbol by the code modulation module, the corresponding symbol rate is 1/TsThe symbol stream is divided into two parallel half-rate symbol streams by a serial-to-parallel conversion module, and the Fourier transform of the symbol stream is expressed as S1(ej2ω) And S2(ej2ω);
S22, converting the two paths of digital symbols into analog signals through D/A conversion modules respectively
Figure FDA0002963220240000021
And
Figure FDA0002963220240000022
corresponding to a sampling rate of 1/2TsWhere ω and f denote digital and analog frequencies, respectively, and ω ═ 2 pi fTs
S23, the two analog signals are respectively processed by two pulse shaping filters to carry out double pulse shaping, wherein, the bandwidth is (1+ beta)/2TsRoot raised cosine pulse hRRC(t) and hRRC(t-Ts) Shaped pulses as two-way pulse shaping filters, respectively, where hRRC(t) corresponding frequency domain response HRRC(f) Is shown as
Figure FDA0002963220240000023
Wherein, beta is more than or equal to 0 and less than or equal to 1 represents the roll-off coefficient of the pulse shaping filter, and the two shaping pulses are combined and then output to a transmitting test signal through the transmitting filter.
5. The method of claim 1, wherein the S30, estimating the frequency response of the channel at the receiving end, further calculating and recording the signal-to-noise ratio of the equalized signal, comprises the following steps:
s31, the transmitted test signal reaches the receiving end after passing through the physical channel and is output through the receiving filter;
s32, the output analog signals are respectively passed through two analog-to-digital conversion modules to obtain two digital signals, and the corresponding sampling rate is 1/2TsThe output digital signal is processed by a channel estimation module to obtain the frequency response estimation of a digital equivalent channel
Figure FDA0002963220240000031
And
Figure FDA0002963220240000032
Figure FDA0002963220240000033
Figure FDA0002963220240000034
wherein the content of the first and second substances,
Figure FDA0002963220240000035
and
Figure FDA0002963220240000036
respectively representing signals
Figure FDA0002963220240000037
And
Figure FDA0002963220240000038
frequency domain response estimation of a simulated equivalent channel formed by a double-pulse shaping receiving filter and a physical channel, (tau +1) TsAnd the sampling time delay of the second path of analog-to-digital conversion module relative to the first path of analog-to-digital conversion module is represented, wherein tau is more than or equal to-1 and less than or equal to 1, and when the ratio rho of the average power of a transmitting end to the noise power of a receiving end is known, the signal-to-noise ratio of the minimum mean square error equalization signal is calculated in a channel estimation module as follows:
Figure FDA0002963220240000039
wherein the content of the first and second substances,
Figure FDA00029632202400000310
C(ω,τ)=HH(ω,τ)(H(ω,τ)HH(ω,τ)+I/ρ)-1 (6)
wherein I represents an identity matrix, Tr {. and {. The { }HRespectively representing the trace and transposed conjugate of the matrix.
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