CN113014403B - Ethernet power supply method and equipment - Google Patents
Ethernet power supply method and equipment Download PDFInfo
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- CN113014403B CN113014403B CN202110222339.6A CN202110222339A CN113014403B CN 113014403 B CN113014403 B CN 113014403B CN 202110222339 A CN202110222339 A CN 202110222339A CN 113014403 B CN113014403 B CN 113014403B
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Abstract
The application provides a power over Ethernet method and equipment. In the equipment, a processor sets a first power slot control value of a first power supply to correspond to first power of the first power supply in a power meter of a power supply chip, and sets a first switchable identifier of the first power supply in a logic control device; the logic control device outputs a first power supply slot control value to the power supply chip according to the first power supply and the first switchable identifier; and the power supply chip receives the first power slot control value output by the logic control device and supplies power according to the first power in the power meter.
Description
Technical Field
The present application relates to communications technologies, and in particular, to an ethernet power supply technology, and in particular, to a power supply method and device for ethernet.
Background
With the introduction of the IEEE802.3BT standard, the demand for PoE (Power over Ethernet) is becoming higher and higher. A PSE (Power Sourcing Equipment, ethernet Power supply Equipment) uses a plurality of Power supply modules to realize high-Power output.
Fig. 1 is a schematic structural diagram of an existing Power over ethernet device, where Power information Power _ MUX (PG0, PG1, PowerType0, PowerType1) stored in a logic control chip CPLD inputs signals to the CPLD chip when a Power supply a and a Power supply B are respectively inserted into a PSE device, a PG0/PG1 register in the CPLD chip is written to 0, the Power information Power _ MUX stored in the CPLD chip is modified from (1,1, XXXX) to (0,0, XXXX), a processor recognizes a PG0/PG1 register change of the CPLD chip, reads a Type a of the Power supply a to 0000, reads a Type of the Power supply B to 0001, sets the Power information Power _ MUX (0,0,0000, 0001), and converts the Power information Power _ MUX (0,0,0000, 0001) into a corresponding Power-bank value, and outputs the Power information to the PSE chip. And the PSE chip supplies Power according to the stored Power-bank value 0100. When Power supplies A and C are inserted into the PSE device, a PG0/PG1 register in the CPLD chip is written to be 0, Power supply information Power _ MUX stored in the CPLD chip is modified from (1,1, XXXX, XXXX) to (0,0, XXXX, XXXX), the processor identifies the PG0/PG1 register change of the CPLD chip, the Type A of the Power supply A is read to be 0000, the Type C of the Power supply C is read to be 0010, and the Power supply information is modified to be (0,0,0000,0010) for indicating that the slot 1, the slot 2, the Type A and the Type C logic chips inserted into the Power supply convert the stored Power _ MUX information (0,0,0000,0010) into a corresponding Power-bank value 0101. In fig. 1, since three types of Power supplies are individually inserted into the PSE device or two types of Power supplies are combined and inserted into the PSE device in 9 arrangements, Power-bank values corresponding to different types of Power supply combinations must be written into the PSE chip in advance, and the logic chip and the PSE chip respectively output signals representing the Power-bank values through four pins. As the types of pluggable Power supplies supported by Power slots of the PSE device increase, the PSE chip needs to provide a greater number of Power-bank pins and write a greater Power-bank value into the PSE chip.
Disclosure of Invention
The present application is directed to a method and device for power over ethernet, which avoid the increase of chip design cost caused by the increase of the number of pluggable power types supported by the power over ethernet device.
In order to achieve the above object, the present application provides a power over ethernet method, including: the processor is used for setting a first power slot control value of a first power supply capable of supplying power to correspond to first power of the first power supply capable of supplying power in a power meter of the power supply chip; setting a first switchable identification of a first powerable supply in the logic control device; the logic control device outputs a first power supply slot control value to the power supply chip according to the first power supply and the first switchable identifier; and the power supply chip receives the first power slot control value output by the logic control device and supplies power according to the first power in the power meter.
In order to achieve the above object, the present application further provides a power over ethernet device, which includes a processor, a logic control chip CPLD, and a power supply chip connected via a bus; the processor is used for setting a first power slot control value of a first power supply capable of supplying power to correspond to first power of the first power supply capable of supplying power in a power meter of the power supply chip; setting a first switchable identification of a first powerable supply in the logic control device; the logic control device is used for outputting a first power supply slot control value according to the set first power supply and the first switchable identifier; and the power supply chip is used for receiving the control value of the first power supply slot and supplying power according to the first power in the power meter.
The beneficial effects of this application lie in, when PSE equipment realized the dynamic power management of PoE, change output control PSE chip according to the slot position that can power supply and adjust power supply power, make the pin figure of the insertion slot position composite value of the control power supply total power on the power supply chip reduce, reduced the chip design degree of difficulty.
Drawings
Fig. 1 is a schematic structural diagram of a conventional power over ethernet device;
FIG. 2 is a flow chart of an embodiment of a power over Ethernet method of the present application;
fig. 3 is a schematic structural diagram of an embodiment of a power over ethernet device according to the present application.
Detailed Description
A detailed description will be given of a number of examples shown in a number of figures. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the examples.
The term "including" as that term is used is meant to include, but is not limited to; the term "comprising" means including but not limited to; the terms "above," "within," and "below" include the instant numbers; the terms "greater than" and "less than" mean that the number is not included. The term "based on" means based on at least a portion thereof.
The embodiment of the power over ethernet method of the present application shown in fig. 2 includes:
in step 201, the processor sets a first power socket control value of a first power supply to correspond to a first power of the first power supply in a power meter of the power supply chip.
In step 202, the processor sets a first switchable identification of a first powerable source in the logic control device.
In step 203, the logic control device outputs a first power slot control value to the power supply chip according to the first power supply and the first switchable identifier.
And 204, the power supply chip receives the first power supply slot control value output by the logic control device and supplies power according to the first power in the power meter.
The beneficial effects of this application lie in, when PSE equipment realized PoE dynamic power management, make PSE chip according to power slot male can power supply dynamic adjustment power, avoid the power supply chip to increase the pin of receiving power-bank value in order to support different powers, be favorable to further promoting the power supply chip miniaturization, also let the design of power supply chip's PoE system convenient succinct more.
Fig. 3 is a schematic structural diagram of an embodiment of the Power over ethernet device of the present application, where Power information Power _ MUX of the CPLD chip of the PSE device is (PG0, PG1, PL0, PL 1); wherein PG0/PG1 is 0, which indicates the available power source inserted into power slot 0/power slot 1; PG0/PG1 equals 1, which indicates that power slot 0/power slot 1 is not plugged in power or is plugged in power failure; PL0/PL1 being 0 indicates a switchable flag of power slot 0/power slot 1, i.e. the switchable flag can be switched to the power supply capable of being inserted into power slot 0/power slot 1; PL0/PL1 equals 1, indicating the non-switchable flag of power slot 0/power slot 1, i.e. power slot 0/power slot 1 has no power supply inserted.
In the embodiment of the application, the Power information Power _ MUX stored in the CPLD chip is (1,1,1, 1).
The CPLD chip and the processor convert the Power _ MUX parameter into a Power-bank value according to the corresponding relation between the Power _ MUX parameter and the Power-bank value shown in the table 1.
TABLE 1
In fig. 3, when the Power supply a is inserted into slot 0, a signal is input to the CPLD chip, the PG0 register of the CPLD chip is written to 0, and the Power supply information Power _ MUX stored in the CPLD chip is modified to (0,1,1, 1). The processor recognizes the change of the PG0 register of the CPLD chip and sends a hardware interrupt signal to the processor. The processor reads the power 500W (watts) of the suppliable power supply A inserted into slot 0, writes a power-bank value [01] representing the power output of the suppliable power supply inserted according to slot 1 and the power 500W of the suppliable power supply A into the power table of the PSE chip in Table 2:
| Power-bank | output power W |
| 11 | 0W (Tile) |
| 01 | 500W |
TABLE 2
After the processor finishes modifying the Power meter of the PSE chip, the Power supply information Power _ MUX stored in the CPLD chip is modified from (0,1,1,1) to (0,1,0,1), namely, the switchable flag of the Power supply A of the Power slot 0 is set.
The CPLD chip outputs a Power-bank value [01] to the PSE chip through two pins according to the modified Power information Power _ MUX (0,1,0, 1).
And the PSE chip starts to supply power according to the power-bank value [01] and the power 500W corresponding to the power-bank value [01 ].
When the Power supply B is inserted into slot 1, a signal is input to the CPLD chip, the PG1 register of the CPLD chip is written to 0, and the stored Power supply information Power _ MUX becomes (0,0,0, 1).
The processor recognizes the PG1 register change of the CPLD chip, reads the power 1000W of the power supply B of the power slot 1, writes the power-bank value [10] representing the power output of the power supply inserted according to the slot 1 and the power 1000W of the power supply B into the power table shown in the table 2-1, and writes the power-bank value [00] representing the power output of the power supply inserted according to the slots 0 and 1 and the total power 1500W of the power supplies A and B into the power table, such as the power table
Shown in Table 2-2:
| Power-bank | output power W |
| 01 | 500W |
| 10 | 1000W |
| 00 | 1500W |
Tables 2 to 2
And after the processor finishes modifying the Power meter of the PSE chip, the Power supply information Power _ MUX stored in the CPLD chip is modified from (0,0,0,1) to (0,0,0, 0).
The CPLD chip outputs a Power-bank value [00] to the PSE chip through two pins according to the modified Power information Power _ MUX (0,0,0, 0). And dynamically changing the output power of the PSE chip from 500W to 1500W according to the input power-bank value [00] to supply power.
When the Power supply A is pulled out of the Power supply slot 0, the PG0 register of the CPLD chip is written as 1, and the Power supply information Power _ MUX stored in the CPLD chip is modified from (0,0,0,0) to (1,0,0,0), which indicates that the Power supply slot 0 is not available for plugging into the Power supply A. The CPLD chip immediately modifies PL0 to 0, i.e. the CPLD chip stores power supply information (1,0,0,0) as (1,0,1, 0). The CPLD chip outputs a Power-bank value [10] to the PSE chip through two pins according to the Power information Power _ MUX (1,0,1, 0).
And the PSE chip starts to supply power according to the power-bank value [10] and the power of 1000W corresponding to the power-bank value [10] in the power table shown in the table 2-2.
When Power supply B is pulled out of Power supply slot 0 or Power supply B fails, the PG1 register of the CPLD chip is written as 1, and the Power supply information Power _ MUX is modified from (1,0,1,0) to (1,1,1,0), indicating that Power supply slot 0 is not available for plugging into Power supply B. The CPLD chip immediately modifies PL1 to 1, namely the CPLD chip stores a power supply chip modified from (1,1,1,0) to (1,1,1, 1). The CPLD chip outputs a Power-bank value [11] to the PSE chip through two pins according to the Power information Power _ MUX (1,1,1, 1).
And the PSE chip receives the power-bank value (11) and stops supplying power to the outside.
In the embodiment of the application, the power supply inserted into the power slot is failed or is pulled out, and the CPLD chip can also control the port power supply power of the PSE chip to be rapidly reduced, so that the port power supply power of the PSE chip exceeds the available power supply power to cause power overload, and the power meter of the PSE chip can be dynamically modified according to the power supply inserted into the power slot.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (8)
1. A power over ethernet method, the method comprising:
the processor sets a first power socket control value of a first power supply to correspond to first power of the first power supply in a power meter of a power supply chip; setting a first switchable identification of the first powerable supply in a logic control device;
the logic control device outputs the first power supply slot control value to the power supply chip according to the first power supply and the first switchable identifier;
and the power supply chip receives the first power supply slot control value output by the logic control device and supplies power according to the first power in the power meter.
2. The method of claim 1, further comprising:
the processor sets a second power slot control value of a second power supply corresponding to second power of the second power supply in the power meter, sets a third power slot control value corresponding to a power slot of the first power supply and a power slot of the second power supply corresponding to total power of the first power supply and the second power supply, and sets a second switchable identifier of the second power supply in the logic control device;
the logic control device outputs a third power slot control value according to the first power supply, the second power supply, the set first switchable identifier and the set second switchable identifier;
and the power supply chip receives the third power supply slot control value output by the logic control device and supplies power according to the total power.
3. The method of claim 2, further comprising:
the logic control device detects that the first power supply source is unavailable, modifies the first switchable identification into a first non-switchable identification, and outputs a second power slot control value according to the second power supply source and the set second switchable identification;
and the power supply chip receives the second power supply slot control value output by the logic control device and supplies power according to the second power in the power meter.
4. The method of claim 3, further comprising:
the logic control device detects that the second power supply source is unavailable, modifies the second switchable identifier into a second non-switchable identifier, and outputs a non-power supply control value;
and the power supply chip receives the non-power supply control value output by the logic control device and stops supplying power.
5. A power over Ethernet device comprising a processor, a logic control device and a power supply chip connected by a bus; wherein,
the processor is used for setting a first power socket control value of a first power supply capable of supplying power to correspond to first power of the first power supply capable of supplying power in a power meter of the power supply chip; setting a first switchable identification of the first powerable supply in the logic control device;
the logic control device is used for outputting the first power supply slot control value according to the set first power supply and the first switchable identifier;
and the power supply chip is used for receiving the first power supply slot control value and supplying power according to the first power in the power meter.
6. The apparatus of claim 5,
the processor is configured to set a second power socket control value of a second power supply corresponding to a second power of the second power supply in the power meter, set a third power socket control value corresponding to the first power supply and the second power supply corresponding to a total power of the first power supply and the second power supply, and set a second switchable identifier of the second power supply in the logic control device;
the logic control device is configured to output the third power socket control value according to the first power supply, the second power supply, the set first switchable identifier, and the set second switchable identifier;
and the power supply chip receives the third power supply slot control value and supplies power according to the total power.
7. The apparatus of claim 6,
the logic control device is further configured to detect that the first power supply is unavailable, modify the first switchable identifier into a first non-switchable identifier, and output the second power slot control value according to the second power supply and the set second switchable identifier;
and the power supply chip is also used for receiving the second power supply slot control value and supplying power according to the second power in the power meter.
8. The apparatus of claim 7,
the logic control device is further used for detecting that the second power supply source is unavailable, modifying the second switchable identifier of luxury postures into a second non-switchable identifier and outputting a non-power supply control value;
and the power supply chip is also used for receiving the non-power supply control value and stopping power supply.
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| CN202110222339.6A CN113014403B (en) | 2021-02-28 | 2021-02-28 | Ethernet power supply method and equipment |
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| CN202110222339.6A CN113014403B (en) | 2021-02-28 | 2021-02-28 | Ethernet power supply method and equipment |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102833079A (en) * | 2012-08-31 | 2012-12-19 | 杭州华三通信技术有限公司 | Method and device for preventing over-supply of pluggable power supply |
| CN106888100A (en) * | 2017-03-31 | 2017-06-23 | 新华三技术有限公司 | POE interchanger and its method of supplying power to |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8595516B2 (en) * | 2008-01-03 | 2013-11-26 | Broadcom Corporation | System and method for global power management in a power over ethernet chassis |
| US11054875B2 (en) * | 2018-09-02 | 2021-07-06 | Arista Networks, Inc. | Centralized adaptive power management |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102833079A (en) * | 2012-08-31 | 2012-12-19 | 杭州华三通信技术有限公司 | Method and device for preventing over-supply of pluggable power supply |
| CN106888100A (en) * | 2017-03-31 | 2017-06-23 | 新华三技术有限公司 | POE interchanger and its method of supplying power to |
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