CN113014243B

CN113014243B - Method for realizing level mismatch ratio optimization of high-speed SST driver in PAM4 mode

Info

Publication number: CN113014243B
Application number: CN201911315850.XA
Authority: CN
Inventors: 金晶; 谢波; 刘晓鸣; 周健军
Original assignee: Shanghai Jiaotong University
Current assignee: Shanghai Jiaotong University
Priority date: 2019-12-19
Filing date: 2019-12-19
Publication date: 2022-11-29
Anticipated expiration: 2039-12-19
Also published as: CN113014243A

Abstract

A method for realizing SST driver level mismatch ratio optimization in a PAM4 mode is characterized in that all input binary digital signals are converted into thermometer codes; and then recording the level mismatch ratio of the output eye pattern, and adjusting the upper and lower levels of the middle eye of the PAM4 eye pattern output by the transmitter to ideal levels through digital loop control, thereby improving the output level mismatch ratio. The invention improves the level mismatch ratio of the output eye diagram in a grouped power supply mode, and realizes that the RLM value is optimized to 99.2%; different groups of power supply voltages are automatically adjusted in a digital loop control mode, area overhead and power consumption are reduced, calibration is performed in a low-speed loop, and the digital loop control method and the digital loop control device can be suitable for a transmitter with a higher-speed SST structure.

Description

Method for realizing level mismatch ratio optimization of high-speed SST driver in PAM4 mode

Technical Field

The invention relates to the technology in the field of communication, in particular to a method for realizing level mismatch ratio optimization of a high-speed SST driver in a PAM4 mode.

Background

Source-Series-Terminated (SST) drivers and current-mode logic (CML) drivers are two mainstream driver architectures. The SST driver has more advantages in power consumption, static power consumption is only 1/4 of that of a corresponding CML driver, even under the condition of balanced full-on, the power consumption is only 1/2 of that of the CML structure, and larger differential output swing can be realized under the same power supply voltage. In order to ensure impedance matching under PVT, SST is usually composed of a switch resistor, a poly resistor and a MOS array, the impedance provided by the MOS array operating in a linear region varies with the variation of the drain-source voltage of the MOS array when the MOS array is turned on in a balanced manner, the level Mismatch Ratio (RLM) when the MOS array outputs a PAM4 mode becomes worse, and the mismatched RLM value means that one of three eyes of the PAM4 eye pattern becomes smaller, which means that the smaller eye will be turned off first after passing through the channel with the same attenuation, thereby greatly increasing the error rate, and therefore a good RLM value means a lower error rate. The prior art uses parasitic resistances to improve the linearity of the overall output voltage, but it is difficult to control its value accurately due to the uncertainty in the parasitic resistances of the power distribution network. The auxiliary DAC is connected with the extra branch in parallel to compensate for the fact that impedance provided by a pull-up and pull-down branch is increased due to the fact that drain-source voltage is increased, the auxiliary DAC is controlled according to an input code pattern through the extra lookup table, however, the lookup table causes a large amount of extra power consumption and area overhead, time sequence of the lookup table of the auxiliary DAC along with the speed increasing is difficult to guarantee, and at present, no RLM value optimization method capable of being applied to a PAM4 mode of the SST driver at a high speed exists.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides a method for realizing the level mismatch ratio optimization of the high-speed SST driver in the PAM4 mode, and solves the problem of the level mismatch ratio when the SST driver is applied to the PAM4 mode.

The invention is realized by the following technical scheme:

the invention relates to a method for realizing optimization of level mismatch ratio of an SST driver in a PAM4 mode, which converts all input binary digital signals into thermometer codes; and then recording the level mismatch ratio of the output eye pattern, and adjusting the upper and lower levels of the middle eye of the PAM4 eye pattern output by the transmitter to ideal levels through digital loop control, thereby improving the output level mismatch ratio.

The SST driver includes: three groups of evenly divided SST slices of interconnect, wherein: the upper and lower groups adopt the same group of voltage to supply power, and the middle group adopts the other group of voltage to supply power.

The intermediate eye is as follows: the transmitter outputs one of the three eye patterns in the PAM4 mode.

The digital coding is converted into the thermometer code and is applied to a low-speed transmitter in a digital logic synthesis mode, a logic circuit which converts binary code into the thermometer code is synthesized by using digital logic, and is set up in an analog mode at high speed, so that the time sequence of a decoding circuit is ensured to be accurate. This form of converting the final slices into thermometers also facilitates matching of the layout.

Technical effects

The invention integrally solves the problem that the signal-to-noise ratio of signals is poor due to the RLM difference of a low-power SST driver under high-speed transmission, so that the requirement of the error rate required by a transmission protocol is difficult to meet.

Compared with the prior art, the SST driver slicing method has the advantages that slicing of the SST driver is achieved through thermometer codes, the slicing is divided into three groups, RLM values in a PAM4 mode are calibrated through two groups of different power supply voltages, calibration is achieved through a low-speed digital loop, the level mismatch ratio of an output eye diagram is improved in a grouped power supply mode, and the level mismatch ratio is optimized to be 99.2%; the digital calibration loop is calibrated at a low speed, two groups of level values after the calibration are given to an SST driver which actually works, the calibration is separated from a normal working mode, and the digital calibration loop can be suitable for a transmitter with a higher-speed SST structure.

Drawings

FIG. 1 is a simplified circuit diagram of the output voltage of an SST driver;

FIG. 2 is a comparison of the level mismatch ratio before and after calibration;

in the figure: a is a PAM4 output eye diagram before calibration; b is the calibrated PAM4 output eye diagram;

FIG. 3 is a schematic structural diagram of an embodiment.

Detailed Description

As shown in fig. 1, a source-series termination driver model applied to this embodiment includes a pull-up branch admittance and a pull-down branch admittance arranged between a supply voltage and a ground point, and a load admittance located therebetween, wherein an output voltage of the load admittance is equal to or higher than the supply voltage

Wherein:

V _OC is an open circuit voltage, G _in For internal resistance admittance, G _load For load admittance, G _up For pull-up branch admittance, G _down For pull-down branch admittance, V _DD For the supply voltage, this voltage is generated for an R-DAC (resistive digital-to-analog converter) or a C-DAC (capacitive digital-to-analog converter).

The ideal level of the source series termination driver is as follows: for single-ended voltage, the output four ideal levels are

For single-ended good calibration, a differential output voltage is ideal due to the symmetry of SST operation

The level mismatch ratio RLM = ((3 × ES) ₁ )，(3×ES ₂ )，(2-3×ES ₁ )，(2-3×ES ₂ ) Whereinsaid:

V ₀ to V ₃ Respectively, four level values of the PAM4 eye diagram from bottom to top.

The embodiment relates to a method for optimizing a level mismatch ratio of a source series termination driver, which specifically comprises the following steps: firstly, recording the level mismatch ratio of an output eye pattern; before the transmitter works, calibrating by a switch; after the calibration is finished, starting the transmitter and recording the level mismatch ratio of the output eye diagram of the transmitter; the obtained data of each set of levels output in the PAM4 mode was calculated in accordance with the definition of the level mismatch Ratio (RLM) in the PAM4 mode, and a comparison result was obtained, as shown in fig. 2.

The digital code is converted into the thermometer code by adopting a digital logic synthesis mode.

As shown in fig. 3, the present embodiment relates to a system for implementing the method, including: two SST drivers, a comparator, a low dropout regulator, and a finite state machine, wherein: each SST driver comprises three groups of slices, the input end of a first SST driver receives 110 and 001 respectively, the input end of the first SST driver is fixed by a node which is input to a comparator, a first node 1 of a second SST driver is input to the other end of the comparator, the comparator outputs a comparison result to a finite state machine to adjust the upper and lower groups of slices of the first SST driver to enable an output level to reach an ideal value, after preliminary calibration is completed, the output node of the second SST driver is switched from the first node 1 to a third node 3, the input of the first SST driver is switched to 000 on one side and 111 on the other side, and the comparator outputs the comparison result to the finite state machine to adjust the output power supply of the low dropout regulator of the middle group of slices of the first SST driver, so that calibration is completed.

The inputs of a P pipe and an N pipe of a branch circuit at one side of the SST driver are consistent, and the input of the branch circuit at the other side and the left branch circuit at the left side are in a pseudo-differential form of 01.

The comparator is a low-speed high-precision analog comparator.

The finite state machine is realized by the synthesis of digital codes.

As shown in fig. 2, the level mismatch ratio of the output eye diagram before calibration is 94% in graph a, and the level mismatch ratio of the output eye diagram after calibration is 99.2% in graph b.

Through specific practical experiments, V is obtained under the specific environment setting of the calibration loop ₀ To V ₃ The values of (b) were-398.5 mV, -133.3mV,133.5mV,400.2mV, respectively. Substituting into the RLM value calculated: v _mid ＝0.85mV，ES ₁ ＝0.3359，ES ₂ ＝0.3322，RLM＝((3×ES ₁ )，(3×ES ₂ )，(2-3×ES ₁ )，(2-3×ES ₂ ))＝0.992。

Compared with the prior art, the transmitter of the device at the high rate of 32Gb/s realizes the calibration of the RLM value in the PAM4 mode.

The foregoing embodiments may be modified in many different ways by those skilled in the art without departing from the spirit and scope of the invention, which is defined by the appended claims and all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims

1. A method for realizing optimization of level mismatch ratio of an SST driver in a PAM4 mode is characterized in that all input binary digital signals are converted into thermometer codes; then recording the level mismatch ratio of the output eye pattern, and adjusting the upper and lower levels of the middle eye of the PAM4 eye pattern output by the transmitter to an ideal level through digital loop control, thereby improving the output level mismatch ratio;

the level mismatch ratio RLM = ((3 × ES) ₁ )，(3×ES ₂ )，(2-3×ES ₁ )，(2-3×ES ₂ ) In which:

V ₀ to V ₃ The four level values of the PAM4 eye diagram are from bottom to top respectively;

the ideal level is: the differential output voltage after single-end calibration is

2. The method for realizing the SST driver level mismatch ratio optimization in the PAM4 mode as claimed in claim 1, wherein the SST driver comprises: three groups of evenly divided SST slices connected to each other, wherein: the upper and lower groups are powered by the same group of voltage, and the middle group is powered by the other group of voltage.

3. The method for realizing the optimization of the SST driver level mismatch ratio in the PAM4 mode as claimed in claim 1, wherein the center eye refers to: the transmitter outputs one of the three eye patterns in the PAM4 mode.

4. The method for realizing the optimization of the level mismatch ratio of the SST driver in the PAM4 mode as claimed in claim 1, wherein the conversion, that is, the application of digital coding into thermometer codes in a low-speed transmitter is realized in a digital logic synthesis mode, a logic circuit for converting binary codes into thermometer codes is synthesized by using digital logic, and the logic circuit is built in an analog mode at a high speed so as to ensure the accurate time sequence of a decoding circuit.

5. An SST driver level mismatch ratio optimization implementation circuit in PAM4 mode, for implementing the method as claimed in any one of claims 1-4, comprising: two SST drivers, a comparator, a low dropout regulator and a finite state machine, wherein: each SST driver comprises three groups of slices, wherein the input end of a first SST driver receives 001 and 110 respectively, the node input to a comparator is fixed, the first node of a second SST driver is input to the other end of the comparator, the comparator outputs a comparison result to a finite state machine to adjust the upper and lower groups of slices of the first SST driver to enable the output level to reach an ideal value, the output node of the second SST driver is switched to a third node from the first node after preliminary calibration is completed, the input of the first SST driver is switched to 000 on one side and 111 on the other side, and the comparator outputs the comparison result to the finite state machine to adjust the output power supply of the low-dropout regulator of the middle group of slices of the first SST driver to complete calibration.