CN113013878B

CN113013878B - System of power management circuit

Info

Publication number: CN113013878B
Application number: CN202110322054.XA
Authority: CN
Inventors: 胡慧雄; 解维虎; 梅小杰; 邹荣涛
Original assignee: Shenzhen Jinyu Semiconductor Co ltd
Current assignee: Shenzhen Jinyu Semiconductor Co ltd
Priority date: 2021-03-25
Filing date: 2021-03-25
Publication date: 2022-09-20
Anticipated expiration: 2041-03-25
Also published as: CN113013878A

Abstract

The invention belongs to the technical field of power management chips, and particularly relates to a device contained in a power management chip, which comprises a switch circuit, a voltage detection circuit, a starting capacitor C1, a voltage maintaining circuit and a working circuit, wherein one end of the switch circuit is connected with a power input end, the other end of the switch circuit is connected with a starting capacitor C1, the input end of the voltage detection circuit is connected with a starting capacitor C1, and the output end of the voltage detection circuit is connected with the switch circuit; when the voltage of the starting capacitor C1 reaches the starting voltage of the power management chip, the voltage is detected by the voltage detection circuit, the voltage detection circuit immediately opens the switch circuit, at the moment, the external power supply cannot continuously charge the starting capacitor C1, namely, the external power supply does not consume extra electric energy, the purpose of energy saving is achieved, and meanwhile, as the working circuit of the power management chip starts to work, the power supply is provided.

Description

System of power management circuit

Technical Field

The invention belongs to the technical field of power management, and particularly relates to a system of a power management circuit.

Background

The power management chip is a chip which plays roles in electric energy conversion, distribution, detection and the like in various electronic equipment systems. The efficient power management chip can stably and continuously provide electric energy for each working module, has high working efficiency, reduces energy consumption and can improve the performance of the whole machine.

Traditional power management chip's starting circuit, it generally all adopts external resistance to realize getting from high pressure and accomplishes the start-up of step-down and chip, and the concrete principle is: the input alternating current firstly passes through a rectifier consisting of 4 diodes D1, is filtered by a filter capacitor C1 and is connected to a power management chip through a starting resistor R1. The power management chip obtains power through the starting resistor R1, then charges the starting capacitor C2, and when the starting capacitor C2 reaches the starting voltage, the power management chip starts to enter a working state.

The above prior art has a problem that after the power management chip starts to operate normally, the starting resistor R1 still consumes power, which is not favorable for the purpose of energy saving and consumption reduction.

Disclosure of Invention

To solve the problems set forth in the background art described above. The invention provides a power management chip and a device contained by the same, which have the characteristic of eliminating power supply of an external resistor to reduce power consumption.

In order to achieve the purpose, the invention provides the following technical scheme: a power management chip comprises a switch circuit, a voltage detection circuit, a starting capacitor C1, a voltage maintaining circuit and a working circuit, wherein one end of the switch circuit is connected with a power input end, the other end of the switch circuit is connected with a starting capacitor C1, the input end of the voltage detection circuit is connected with a starting capacitor C1 and used for detecting the voltage on the starting capacitor C1, the output end of the voltage detection circuit is connected with the switch circuit, when the voltage detection circuit detects that the voltage on the starting capacitor C1 reaches the starting voltage of the power management chip, the switch circuit is controlled to be disconnected, the voltage maintaining circuit is connected between the starting capacitor C1 and the working circuit and used for obtaining the voltage of the starting capacitor C1 from the working circuit of the power management chip and when the voltage of the starting capacitor C1 reaches the starting voltage of the power management chip, the voltage is detected by the voltage detection circuit, the voltage detection circuit can break the switch circuit, at this time, the external power supply can not continue to charge the starting capacitor C1, i.e. no extra power consumption is needed, and the purpose of energy saving is achieved, meanwhile, as the working circuit of the power management chip starts to work, the power supply supplies power, the voltage maintaining circuit obtains the voltage for maintaining the starting capacitor C1 from the working circuit, and therefore the normal work of the working circuit is guaranteed.

Further, in the present invention, the switch circuit includes a depletion NMOS1, a P-type junction field effect transistor PJFET, a resistor R1, a PMOS1, an NMOS2, an NMOS3, an NMOS4, and a diode D1, the drain of the depletion NMOS1 is connected to an input power terminal, the source of the depletion NMOS1 is connected to the drain of the PJFET, the gate of the depletion NMOS1 is connected to the source of the PJFET, the gate of the PJFET is connected to an output terminal of the voltage detection circuit, the source of the PJFET is simultaneously connected to a resistor R1, the source of the PMOS1, and the anode of the diode D1, the other end of the resistor R1 is connected to the drain of the NMOS2, the gate and the source of the NMOS2 are both connected to a ground terminal, the drain of the PMOS1 is connected to the drain of the NMOS3 and the gate of the NMOS4, the gate of the PMOS 4 is connected to the gate of the NMOS4, the drain of the NMOS4 is connected to the drain of the NMOS4, the drain of the diode 4 is connected to the drain of the NMOS4, and the NMOS4, the voltage detection circuit 4 is connected to the drain of the NMOS4 The starting capacitor C1 and the cathode of the diode D2 are connected at the same time, since the depletion type NMOS1 and the PJFET are both normally-on devices, current passes through the resistor R1, voltage drop is generated on two sides of the resistor R1, meanwhile, the NMOS2 is not turned on due to the fact that the grid is grounded, the capacitor is charged, accordingly, the PMOS1 and the NMOS3 of the next stage output a positive voltage to the grid of the NMOS4, at the moment, the NMOS4 is turned on and conducted, the current passes through the forward diode D1, then the NMOS4 charges the starting capacitor C1, and the voltage on the starting capacitor C1 is gradually increased.

In the invention, the input end of the voltage detection circuit is simultaneously connected with the source of the NMOS4 and the starting capacitor C1, the output end of the voltage detection circuit is connected with the gate of the PJFET in the switch circuit, and the other end of the voltage detection circuit is grounded.

Further, in the present invention, one end of the start capacitor C1 is connected to the source of the NMOS4, and the other end of the start capacitor C1 is grounded.

Further, the voltage maintaining circuit comprises a diode D2 and an inductor L1, the cathode of the diode D2 is connected to the upper plate of the starting capacitor C1, the anode of the diode D2 is connected to the inductor L1, and the other end of the inductor L1 is connected to the lower plate ground line of the starting capacitor C1.

Further in the present invention, the operating circuit is at the last stage of the overall circuit.

Another object of the present invention is to provide a system for power management circuit.

In the present invention, the power management circuit system further includes a switch circuit branch system composed of a depletion NMOS1, a P-type jfet, a resistor R1, a PMOS1, an NMOS2, an NMOS3, an NMOS4, and a diode D1, a voltage detection circuit branch system, and a voltage maintenance circuit branch system composed of a diode D2 and an inductor L1.

Further, the system of power management circuit of the present invention includes the following operation steps:

step one, when a power supply starts to be input, because depletion type NMOS1 and PJFET are normally-on devices, current can pass through, then the current passes through a resistor R1, voltage drop is generated on two sides of the resistor R1, meanwhile, the NMOS2 is not turned on due to the fact that a grid is grounded, and the capacitor is charged, so that the PMOS1 and the NMOS3 of the next stage output a positive voltage to the grid of an NMOS4, at the moment, the NMOS4 is turned on, the current passes through a forward diode D1 and then charges a starting capacitor C1 through an NMOS4, and the voltage on the starting capacitor C1 is gradually increased;

step two, as the voltage of the starting capacitor C1 rises to reach the starting voltage, the voltage detection circuit will output a signal to the gate of the PJFET, the signal is a high level (i.e. positive voltage), because the PJFET gate is applied with positive voltage, the inside of the PJFET starts to enter a turn-off process, during the turn-off process, the on-resistance of the PJFET starts to increase, causing the drain voltage of the PJFET to be far greater than the source voltage, meanwhile, because the source of the PJFET is connected with the gate of the depletion NMOS1, the drain of the PJFET is connected with the source of the depletion NMOS1, i.e. the gate voltage of the depletion NMOS1 is less than the source voltage, which is equivalent to applying a negative voltage to the gate of the depletion NMOS1, which causes the depletion NMOS1 to enter a turn-off process, i.e. the gate voltage of the PJFET tends to turn off the PJFET, and the gate voltage of the depletion NMOS1 also tends to turn off the depletion NMOS1, which affect each other and form a positive feedback process, the depletion type NMOS1 and the PJFET can be rapidly changed from an on state to an off state, and after the switch circuit is turned off, the charging process of the starting capacitor C1 is finished, so that the power consumption of the whole circuit is reduced;

and step three, then, the system starts to work, the voltage on the starting capacitor C1 starts to drop, and the inductor L1 is used for supplying energy to the starting capacitor C1.

Compared with the prior art, the invention has the beneficial effects that: when the voltage of the starting capacitor C1 reaches the starting voltage of the power management chip, the voltage is detected by the voltage detection circuit, the voltage detection circuit immediately opens the switch circuit, at the moment, the external power supply cannot continuously charge the starting capacitor C1, namely, the external power supply does not consume extra electric energy, and the purpose of energy saving is achieved.

Drawings

FIG. 1 is a circuit diagram of the present invention;

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Examples

Referring to fig. 1, the present invention provides the following technical solutions: a power management chip comprises a switch circuit, a voltage detection circuit, a starting capacitor C1, a voltage maintaining circuit and a working circuit, wherein one end of the switch circuit is connected with a power input end, the other end of the switch circuit is connected with a starting capacitor C1, the input end of the voltage detection circuit is connected with a starting capacitor C1 and is used for detecting the voltage on a starting capacitor C1, the output end of the voltage detection circuit is connected with the switch circuit, when the voltage detection circuit detects that the voltage on the starting capacitor C1 reaches the starting voltage of the power management chip, the switch circuit is controlled to be disconnected, the voltage maintaining circuit is connected between the starting capacitor C1 and the working circuit and is used for obtaining the voltage for maintaining the starting capacitor C1 from the working circuit of the power management chip, and when the voltage of the starting capacitor C1 reaches the starting voltage of the power management chip, the voltage is detected by the voltage detection circuit, the voltage detection circuit can break the switch circuit, at this time, the external power supply can not continue to charge the starting capacitor C1, i.e. no extra power consumption is needed, and the purpose of energy saving is achieved, meanwhile, as the working circuit of the power management chip starts to work, the power supply supplies power, the voltage maintaining circuit obtains the voltage for maintaining the starting capacitor C1 from the working circuit, and therefore the normal work of the working circuit is guaranteed.

Further, the switch circuit includes depletion type NMOS1, P-type junction field effect transistor PJFET, resistor R1, PMOS1, NMOS2, NMOS3, NMOS4 and diode D1, the drain of depletion type NMOS1 is connected to the input power terminal, the source of depletion type NMOS1 is connected to the drain of the PJFET, the gate of depletion type NMOS1 is connected to the source of the PJFET, the gate of the PJFET is connected to the output terminal of the voltage detection circuit, the source of the PJFET is connected to both resistor R1, the source of PMOS1 and the anode of diode D1, the other end of resistor R1 is connected to the drain of NMOS1, the gate and the source of NMOS1 are connected to ground, the drain of diode D1 is connected to the drain of NMOS1 and the gate of NMOS1, the gate of PMOS1 is connected to the gate of NMOS1 and the node between resistor R1 and NMOS1, the source of NMOS1 is connected to the drain of NMOS1, the drain of the PMOS1 is connected to the drain of the NMOS1, the drain of the diode 1 and the diode 1 is connected to the drain of the NMOS1, the diode 1 is connected to the NMOS1, the diode 1, the NMOS1 is connected to the diode 1, the diode 1 and the diode 1 is connected to the diode 1, and the diode 1 is connected to the diode 1, the diode 1 is connected to the diode 1, the diode 1 is connected to the diode 1, the diode 1 is connected to the diode 1, and the diode 1, the diode 1 is connected to the diode 1, the diode. The current is passed through the resistor R1, a voltage drop is generated across the resistor R1, meanwhile, the NMOS2 is not turned on because the gate is grounded, which is equivalent to the capacitor being charged, so that the PMOS1 and the NMOS3 of the next stage output a positive voltage to the gate of the NMOS4, at this time, the NMOS4 is turned on, the current passes through the forward diode D1 and then through the NMOS4 to charge the starting capacitor C1, and the voltage on the starting capacitor C1 is gradually increased.

Furthermore, the input end of the voltage detection circuit is simultaneously connected with the source of the NMOS4 and the starting capacitor C1, the output end of the voltage detection circuit is connected with the gate of the PJFET in the switch circuit, the other end of the voltage detection circuit is grounded, one end of the starting capacitor C1 is connected with the source of the NMOS4, the other end of the starting capacitor C1 is grounded, as the voltage of the starting capacitor C1 rises to reach the starting voltage, the voltage detection circuit outputs a signal to the gate of the PJFET, the signal is at a high level (namely positive voltage), the internal part of the PJFET starts to enter a turn-off process due to the positive voltage applied to the PJFET gate, the on-resistance of the PJFET starts to increase in the turn-off process, the drain voltage of the PJFET is far greater than the source voltage, meanwhile, the drain of the PJFET is connected with the gate of the depletion type NMOS1, the drain of the PJFET is connected with the source of the depletion type NMOS1, namely the gate voltage of the depletion type NMOS1 is less than the source voltage, the gate corresponding to depletion NMOS1 is applied with a negative voltage, which causes depletion NMOS1 to also enter the turn-off process. Namely, the gate voltage of the PJFET tends to turn off the PJFET, the gate voltage of the depletion NMOS1 also tends to turn off the depletion NMOS1, the two affect each other and form a positive feedback process, and the depletion NMOS1 and the PJFET can be rapidly changed from an on state to an off state. After the switch circuit is turned off, the charging process of the starting capacitor C1 is finished, and the power consumption of the whole circuit is reduced.

Further, the voltage maintaining circuit comprises a diode D2 and an inductor L1, a cathode of the diode D2 is connected to an upper plate of the starting capacitor C1, an anode of the diode D2 is connected to the inductor L1, and the other end of the inductor L1 is connected to a lower plate ground line of the starting capacitor C1, so that when the system starts to work, the voltage on the starting capacitor C1 starts to drop, and the inductor L1 is used for providing energy for the starting capacitor C1.

Further, the working circuit is at the last stage of the overall circuit.

Furthermore, the system of the power management circuit comprises a switch circuit branch system consisting of a depletion type NMOS1, a P type junction field effect transistor PJFET, a resistor R1, a PMOS1, an NMOS2, an NMOS3, an NMOS4 and a diode D1, a voltage detection circuit branch system, a voltage maintenance circuit branch system consisting of a diode D2 and an inductor L1, a starting capacitor C1 branch system and a working circuit branch system.

Further, the system of the power management circuit of the present invention comprises the following operation steps: step one, when a power supply starts to be input, because depletion type NMOS1 and PJFET are normally-on devices, current can pass through, then the current passes through a resistor R1, voltage drop is generated on two sides of the resistor R1, meanwhile, the NMOS2 is not turned on due to the fact that a grid is grounded, and the capacitor is charged, so that the PMOS1 and the NMOS3 of the next stage output a positive voltage to the grid of an NMOS4, at the moment, the NMOS4 is turned on, the current passes through a forward diode D1 and then charges a starting capacitor C1 through an NMOS4, and the voltage on the starting capacitor C1 is gradually increased;

step two, as the voltage of the starting capacitor C1 rises to reach the starting voltage, the voltage detection circuit will output a signal to the gate of the PJFET, the signal is a high level (i.e. positive voltage), as the positive voltage is applied to the gate of the PJFET, the inside of the PJFET starts to enter the turn-off process, during the turn-off process, the on-resistance of the PJFET starts to increase, causing the drain voltage of the PJFET to be much greater than the source voltage, meanwhile, as the source of the PJFET is connected with the gate of the depletion NMOS1 and the drain of the PJFET is connected with the source of the depletion NMOS1, i.e. the gate voltage of the depletion NMOS1 is less than the source voltage, which is equivalent to applying a negative voltage to the gate of the depletion NMOS1, which causes the depletion NMOS1 to enter the turn-off process, i.e. the gate voltage of the PJFET tends to turn off the PJFET, and the gate voltage of the depletion NMOS1 also tends to turn off the depletion NMOS1, which affect each other and form a positive feedback process, the depletion type NMOS1 and the PJFET can be rapidly changed from an on state to an off state, and after the switch circuit is turned off, the charging process of the starting capacitor C1 is finished, so that the power consumption of the whole circuit is reduced;

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A power management circuit, comprising: the power supply comprises a switch circuit, a voltage detection circuit, a starting capacitor C1, a voltage maintaining circuit and a working circuit, wherein one end of the switch circuit is connected with a power supply input end, the other end of the switch circuit is connected with a starting capacitor C1, the input end of the voltage detection circuit is connected with a starting capacitor C1, the output end of the voltage detection circuit is connected with the switch circuit, and the voltage maintaining circuit is connected between the starting capacitor C1 and the working circuit;

the switch circuit comprises a depletion type NMOS1, a P-type junction field effect transistor PJFET, a resistor R1, a PMOS1, an NMOS2, an NMOS3, an NMOS4 and a diode D1, wherein the drain of the depletion type NMOS1 is connected with an input power supply end, the source of the depletion type NMOS1 is connected with the drain of the PJFET, the gate of the depletion type NMOS1 is connected with the source of the PJFET, the gate of the PJFET is connected with an output end of a voltage detection circuit, the source of the PJFET is simultaneously connected with the resistor R1, the source of the PMOS1 and the anode of the diode D1, the other end of the resistor R1 is connected with the drain of the NMOS2, the gate and the source of the NMOS2 are connected with a ground terminal, the drain of the PMOS1 is connected with the drain of the NMOS3 and the gate of the NMOS4, the gate of the PMOS1 is connected with the gate of the NMOS3 and the middle node of the resistor R1 and the NMOS2, the drain of the NMOS3 is connected with the drain of the diode D1, the drain of the NMOS4 is connected with the source of the NMOS 39 4, and the NMOS 3929 of the NMOS detection circuit, The starting capacitor C1 and the cathode of the diode D2 are connected at the same time;

the input end of the voltage detection circuit is simultaneously connected with the source electrode of the NMOS4 and the starting capacitor C1, the output end of the voltage detection circuit is connected with the grid electrode of the PJFET in the switch circuit, and the other end of the voltage detection circuit is grounded; one end of the starting capacitor C1 is connected with the source of the NMOS4, and the other end of the starting capacitor C1 is grounded; the voltage maintaining circuit comprises a diode D2 and an inductor L1, the cathode of the diode D2 is connected with the upper plate of a starting capacitor C1, the anode of the diode D2 is connected with an inductor L1, and the other end of the inductor L1 is connected with the lower plate ground line of the starting capacitor C1; the working circuit is at the last stage of the overall circuit.

2. The system of claim 1, comprising a switch circuit branch system consisting of depletion type NMOS1, P-type JFET PJFET, resistor R1, PMOS1, NMOS2, NMOS3, NMOS4 and diode D1, a voltage detection circuit branch system, a voltage maintenance circuit branch system consisting of diode D2 and inductor L1, a starting capacitor C1 branch system and a working circuit branch system.

3. A system of power management circuits according to claim 2, wherein: the method comprises the following operation steps:

step two, as the voltage of the starting capacitor C1 rises to reach the starting voltage, the voltage detection circuit will output a signal to the gate of the PJFET, the signal is a high level positive voltage, because the PJFET gate is applied with a positive voltage, the inside of the PJFET starts to enter a turn-off process, in the turn-off process, the on-resistance of the PJFET starts to increase, causing the drain voltage of the PJFET to be far greater than the source voltage, meanwhile, because the source of the PJFET is connected with the gate of the depletion NMOS1, the drain of the jfet p is connected with the source of the depletion NMOS1, i.e., the gate voltage of the depletion NMOS1 is less than the source voltage, which is equivalent to the fact that the gate of the depletion NMOS1 is applied with a negative voltage, causing the depletion NMOS1 to enter a turn-off process, i.e., the gate voltage of the PJFET tends to turn off the PJFET, the gate voltage of the depletion NMOS1 also tends to turn off the depletion NMOS1, the depletion NMOS1 and the PJFET both tend to turn off from the turn-on state, after the switch circuit is turned off, the charging process of the starting capacitor C1 is finished, and the power consumption of the whole circuit is reduced;