CN113013261A - Nano silicon/amorphous silicon carbide heterojunction multi-potential-barrier variable capacitance diode and preparation method thereof - Google Patents

Nano silicon/amorphous silicon carbide heterojunction multi-potential-barrier variable capacitance diode and preparation method thereof Download PDF

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CN113013261A
CN113013261A CN202110203412.5A CN202110203412A CN113013261A CN 113013261 A CN113013261 A CN 113013261A CN 202110203412 A CN202110203412 A CN 202110203412A CN 113013261 A CN113013261 A CN 113013261A
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silicon
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韦文生
吴晓华
莫越达
王渊
熊愉可
何明昌
周迪
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Wenzhou University
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Abstract

The invention discloses a nano silicon/amorphous silicon carbide heterojunction multi-barrier varactor and a preparation method thereof, comprising N+Type-monocrystalline silicon substrate, N+An N-type nano-silicon modulation layer deposited on the type monocrystalline silicon substrate, an amorphous silicon carbide barrier layer deposited on the N-type nano-silicon modulation layer, and an N-type nano-silicon modulation layer deposited on the amorphous silicon carbide barrier layer; determining the growth cycle of a heterojunction formed by an N-type nano-silicon modulation layer, an amorphous silicon carbide barrier layer and an N-type nano-silicon modulation layer according to the requirements of withstand voltage and capacity; then depositing N+A nano-silicon contact layer; in N+The upper surfaces of the type monocrystalline silicon substrate and the nano silicon contact layer are respectively coated with gold aluminum electrodes by evaporation, the outer surface of the heterojunction is oxidized to generate a protective layer, and the outer surface of the heterojunction is coated with a light shielding layer to manufacture the heterojunction multi-barrier varactor. The heterojunction multi-potential barrier variable capacitance diode has the advantages of small capacitance, high variable capacitance ratio, high cut-off frequency and wide dynamic load modulation range, and is suitable for frequency multiplication, electric tuning, parameter amplification and the like.

Description

Nano silicon/amorphous silicon carbide heterojunction multi-potential-barrier variable capacitance diode and preparation method thereof
Technical Field
The invention belongs to the technical field of electronics, and relates to a semiconductor device, in particular to a nano silicon/amorphous silicon carbide heterojunction multi-barrier varactor and a preparation method thereof.
Background
A capacitor is a device that stores electric field energy, and a conventional capacitor is composed of two metal plates separated by a dielectric medium in a specific geometry. In the mechanical tuning capacitor used in the early days, the quality of the element itself is usually up to several thousand due to the high Q value; but the volume is large and the installation and the use are inconvenient. Over the course of development, part of the mechanical tuning capacitors has been replaced by varactors, the latter typically having a Q value of between tens and hundreds. PN junction varactors are semiconductor devices, also known as voltage-controlled varactors, that are made using the principle that the capacitance of the PN junction changes with reverse voltage when the diode is reverse biased, and its reverse breakdown voltage is related to the resistivity of the substrate material. Unlike the traditional metal plate capacitor or PN junction capacitor, in which the charges are accumulated in the polar plate or P, N region, in the nano-silicon/amorphous silicon carbide heterojunction multi-barrier varactor of the invention, the nano-silicon with narrow band gap is used as a potential well to store the charges, and the amorphous silicon carbide with wide band gap is used as a barrier medium; each heterojunction formed by doped nano silicon/amorphous silicon carbide/doped nano silicon is used as a barrier capacitor, a plurality of capacitors are connected in series to form a heterojunction barrier varactor, the equivalent capacitance of the heterojunction barrier varactor is reduced, the terminal voltage is increased, and the heterojunction barrier varactor is suitable for the high-frequency and high-voltage fields.
By way of search, the following main documents reflect the varactor diode in the prior art. The method specifically comprises the following steps:
document 1[ AEU-International Journal of Electronics and Communications, vol.110, No.10(2019):152823-1-13 ], the varactor can replace a mechanical tuning capacitor, has a smaller volume, improves the reliability of a circuit, is widely used in electronic information fields such as harmonic generation, frequency multiplication, low noise amplification, microwave receiving tuners, active filters, switches, phase shifting, pulse generation and pulse shaping, optical detection and the like, and the power consumption of a capacitive optical detection sensor is smaller than the corresponding value of other traditional optical detectors. Epitaxial and diffusion techniques are commonly used to fabricate compound semiconductor varactors such as silicon single crystals or gallium arsenide. Its category includes electrically tuned varactors (usable in resonant circuits, etc.), parametric amplification varactors (usable for frequency doubling, electrical tuning, signal parametric amplification, etc.), power step varactors (usable for medium frequency doubling, phase shifting, etc. of solid power sources).
Document 2[ Critical design subsystems for high-power GaN _ AlGaN anti-serial Schottky resistor frequency triplers, Microelectronics Journal, Vol.43, No.6(2012): 410-: metal-semiconductor-metal-two-dimensional electron gas (MSM-2DEG) type varactor, anti-series Schottky varactor (ASV), Heterojunction Barrier Varactor (HBV). The first two exhibit lower leakage current because the potential barrier is higher; MSM-2DEG devices generally employ a lateral structure; the latter two (ASV, HBV) generally adopt a vertical structure, a semiconductor layer can be thickened so as to improve the breakdown electric field intensity, the high-power processing capability is realized, a symmetrical capacitance-voltage relation and an antisymmetric current-voltage relation can be formed, a current bias and an even harmonic no-load circuit when the current bias is used as a frequency tripler are not required to be arranged, and the conversion efficiency of the third harmonic is improved. By utilizing the nonlinear semiconductor varactor, high-frequency harmonic waves can be generated from low-frequency pumping, and the method is an effective way for obtaining a terahertz wave source. The loss of a semiconductor varactor as a varactor is as small as possible, i.e., the diffusion capacitance is as small as possible, because the charge and discharge currents of the diffusion capacitance cause losses in the circuit. Then, the barrier capacitance of the semiconductor varactor is fully utilized to operate in the whole reverse bias voltage range between 0 bias voltage and breakdown. On the premise of ensuring the reliability of the highest reverse working voltage and the like, a feasible process is selected to manufacture the varactor polar plate and the dielectric medium which are as thin as possible, but the material quality is ensured, and the method is environment-friendly and energy-saving.
Document 3[ Materials, Vol.13, No.1(2020):4956-1-16.]By electron beam evaporation on Si/GaN/Al0.26Ga0.74GaN growth Ga of cap layer of N/GaN structure2O3And reducing interface defects by high-temperature annealing, oxidizing the substrate Si, and plating metal electrodes on two sides to form the metal-oxide-semiconductor-oxide-metal (MOSOM) type capacitance-variable diode. Analysis and comparison of the electrical characteristics of the MOSOM and the MSM varactor without the oxide layer show that the MOSOM varactor has asymmetric threshold voltage delay and voltage-capacitance relationship, and an appropriate annealing process can be used for eliminating the asymmetry of the voltage-capacitance relationship of the MOSOM varactor, improving the influence of polarization effect and heterojunction stress, reducing the maximum capacitance of the device, improving breakdown voltage and being beneficial to resisting harmful electromagnetic pulses.
Document 4[ Journal of Applied Physics, Vol.121, No.1(2017):214504-1-7.]Discloses the sequential growth of SiO on Si using Atomic Layer Deposition (ALD) techniques2、SrF2、HfO2The film is prepared into a metal-insulator-semiconductor (MIS) type light-operated variable capacitance diode, and the device shows extremely low secondary voltage-capacitance coefficient. Wherein SrF2The Fe or Co nano-particles embedded in the layer can induce the bipolar trap electricity of electron type polarizationThe charge improves the photon-generated minority carrier density, the inversion layer becomes thin, and the energy band bending of the semiconductor side is increased. The device overcomes the defect that the capacitor in the traditional MIS type capacitance-variable diode is insensitive to voltage, and can be used for radio frequency/analog signal mixing, optoelectronic circuits and the like in the remote sensing technology.
Document 5[ Applied Physics Letters, Vol.77, No.1(2000): 103-.]Solving Schrodinger Poisson equation through numerical value and experimental research on (n) Si/SiO2/(n) Si heterojunction varactor discovery, because of SiO2The potential barrier height and the electron effective mass are very large, so the reverse leakage current is very small; can be prepared by adjusting SiO2The barrier height of (a) changes the shape of the capacitance-voltage relationship curve; the difference between the theoretical prediction and the measured values for the bonding process prepared samples is due to boron compensating phosphorus at the heterojunction interface.
Document 6[ Microelectronics Reliability, Vol.78, No.1(2017):243- > 248.]Al is grown by Metal Organic Chemical Vapor Deposition (MOCVD) technology0.25Ga0.75N/GaN heterojunction, and evaporation coating NbTiAlNiAu alloy ohmic electrode by electron beam evaporation technique to form MSM type electrode/AlGaN/GaN/electrode-heterojunction barrier varactor, and metal-insulator-semiconductor-metal (MISM) type electrode/Al2O3The comparison analysis shows that the voltage-capacitance relation of the two devices is symmetrical about 0 bias voltage; for the MSM type variable capacitance diode without a dielectric layer, the transition voltage is the sum of the threshold voltage of the diode reversely biased in the MSM structure and the voltage of the diode forward biased, and is mainly determined by the voltage of the diode reverse biased, the voltage of the diode forward biased can be ignored, the higher the Schottky barrier is, the larger the rectification ratio is; for the MISM type capacitance-variable diode with the dielectric layer, the reverse current and the forward current are lower, the voltage of the forward biased diode cannot be ignored, and the transition voltage is the sum of the threshold voltage of the reverse biased diode and the voltage of the forward biased diode in the MSM structure.
Document 7[ IEEE Transactions on Electron Devices, vol.54, No.9(2007): 2570-; compared with a junction type varactor, the N-channel MOS varactor has a higher capacitance tuning ratio, can be improved by the compromise of channel length and Q factor, and is easier to match in capacitance because the process is less fluctuant; the low-frequency noise of the N-channel MOS varactor working in the accumulation mode is more obvious, is caused by grid leakage current and is related to grid voltage; the figure of merit (FOM) is an important factor in the preference for varactors when considering VCO phase noise performance.
Document 8[ semiconductor device, varactor, and method for forming the same, patent No. 201110172457.7 ] discloses a varactor having a MOS structure prepared using semiconductor single crystal silicon, silicon germanium, or gallium arsenide, and when the voltage of an N-type well region varies within a range of 5.0V to 20.0V, the capacitance of the varactor varies slowly and over a relatively large range, that is, the capacitance can be finely tuned within the voltage range, thereby overcoming the defect of capacitance fine tuning in the prior art.
Document 9[1999Symposium on High Performance Electron Devices for Microwave and Optoelectronic Applications (EDMO), London, UK, nov.23-23,1999: 301-; the former can work at higher temperature and output higher power.
In document 10[ semiconductor science and report, vol.26, No.4(2005): 745-.
Document 11[ nano silicon varactor and its processing method, application No. 2008100242039 ] proposes a nano silicon varactor, which uses P-type or N-type low-resistance single crystal silicon as a substrate, grows an epitaxial layer on the substrate, adopts a semiconductor planar process on the epitaxial layer, grows a doped nano silicon thin film as a working layer of a device, then forms electrodes on a nano silicon layer and under the single crystal silicon substrate by sputtering or evaporation, then forms an upper surface passivation film, and finally slices and packages to form a product. The nano silicon variable capacitance diode takes a quantum tunneling mechanism as a main conduction mechanism, reverse leakage current is in the nanoampere (nA) magnitude, and the temperature stability is excellent.
Document 12[ a method for producing a silicon epitaxial material for a varactor, patent No. 2008100242039.]A process for preparing silicon epitaxial material for varactor diode by controlling hydrochloric acid (HCl) and hydrogen (H)2) The impurities in the wafer manufacturing process are etched by H through three times of HCl in-situ etching2Taking away, reducing self-doping in the silicon material epitaxy process, obtaining the silicon epitaxy material with the thickness uniformity of less than 2 percent, the in-chip resistivity uniformity of less than 5 percent and the transition region between the edge and the middle in the range of 0.7-0.9 micron, so that the effective thickness consistency of the silicon epitaxy layer is good, the in-chip resistivity uniformity is good, and the requirements of the variable capacitance diode are met.
Document 13[ varactor with heterostructure, application No. 2015102496364 ] designs a GaAs/AlGaAs (or InGaP) heterojunction varactor in the base-collector junction of a bipolar transistor to increase the withstand voltage, tuning range, and improve the intermodulation performance.
Document 14[ a method for manufacturing a photosensitive capacitor, patent No. 201510465303.5 ] proposes a flat photosensitive capacitor having a structure of conductive glass/conductive silver paste/photosensitive dielectric material/conductive silver paste/conductive glass, in which when light is irradiated on the photosensitive dielectric material through the conductive glass and the conductive silver paste coating, the dielectric constant changes, and the capacitance value of the capacitor can be adjusted by the illumination intensity, which is different from the present invention in principle.
Document 15[ Microelectronics Reliability, vol.53, No.12(2013):1886-1890 ] numerical simulation shows that the quantum volume effect of the nano silicon crystal grain has an influence on the threshold voltage of the nano silicon thin film transistor, the band gap of the nano silicon is narrowed along with the increase of the crystal grain, the dielectric constant is reduced along with the increase of the crystal grain, the threshold voltage is reduced along with the increase of the crystal grain, and the quantum volume effect is very obvious when the diameter of the nano silicon crystal grain is less than 20 nanometers; in addition, the contribution of the defect density of the grain boundary to the threshold voltage is more significant than the concentration of the active impurity.
Document 16[ Solar Energy Materials and Solar Cells, Vol.182, No.9(2018): 220-. The ratio of methane to silane is gradually increased, the Si-C bond density is increased, and the p-nc-SiC: H thin film is gradually and completely disordered. When the p-nc-SiC H thin film is used for replacing a p-nc-Si H window layer of the original flexible nano silicon thin film solar cell, because the band gap of the p-nc-SiC H thin film is wider, the open-circuit voltage of the cell is improved, the quantum efficiency of the 350-550nm waveband is improved, and the conversion efficiency of the flexible cell is improved from 6.37% to 7.89%; after the highly doped p-nc-Si H layer is inserted between the low doped p-nc-Si H layer and the ITO window layer, the conversion efficiency is further improved to 9.18 percent; when the p-nc-SiC H thin film is used for replacing a p-nc-Si H window layer of the original semitransparent nano silicon thin film solar cell, the conversion efficiency of the semitransparent cell is improved from 3.66% to 4.33%.
The technical scheme which is the same as or similar to the technical scheme of the invention or is inspired by the invention is not found.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a nano silicon/amorphous silicon carbide heterojunction multi-barrier varactor which is different from the prior literature and adopts a new mechanism and a preparation method thereof. The varactor comprises a plurality of periodic heterojunctions, a nano-silicon modulation layer with a narrow band gap is used as a potential well for storing charges, and amorphous silicon carbide with a wide band gap is used as a potential barrier dielectric layer. With the gradual increase of the voltage, the charges in different potential wells are gradually exhausted, the capacitance is reduced, and the capacitance is adjusted by changing the area of the capacitor and changing the charges in the P region and the N region of the PN junction diode, which is different from the traditional metal plate capacitor. According to the nano silicon/amorphous silicon carbide heterojunction multi-barrier variable capacitance diode, each heterojunction is used as a capacitor, all the heterojunction capacitors are connected in series, the equivalent capacitance of the whole variable capacitance diode is reduced, and the terminal voltage of the variable capacitance diode is increased. Therefore, the heterojunction multi-barrier varactor disclosed by the invention is small in capacitance, high in withstand voltage and suitable for the fields of high frequency and high power. During manufacturing, the advantages of silicon and silicon carbide materials maturity and compatible process technology are exerted, and a novel microwave electronic device is provided and can be used as a frequency multiplier, a tuner, a parameter amplifier and the like.
The reason why the hydrogenated nano silicon film (abbreviated as our nano silicon) and the hydrogenated amorphous silicon carbide film (abbreviated as amorphous silicon carbide) are 2 materials selected by the invention is that the two materials can be prepared by adopting the Plasma Enhanced Chemical Vapor Deposition (PECVD) technology, only the components are different, the process has compatibility, the components and the structure can be changed by controlling the process parameters, and the band gaps of the 2 materials are adjusted to meet the design requirements. Amorphous silicon is abandoned because of high resistance and high preparation temperature of nano silicon carbide; the nano silicon does not contain silicon carbide, and the amorphous silicon carbide does not contain nano silicon crystal grains.
In order to achieve the purpose, the technical scheme of the invention is that the nano silicon/amorphous silicon carbide heterojunction multi-barrier varactor comprises N+Type-monocrystalline silicon substrate, N+An N-type nano-silicon modulation layer deposited on the type monocrystalline silicon substrate, an amorphous silicon carbide barrier layer deposited on the N-type nano-silicon modulation layer, and an N-type nano-silicon modulation layer deposited on the amorphous silicon carbide barrier layer;
the heterojunction formed by the N-type nano-silicon modulation layer, the amorphous silicon carbide barrier layer and the N-type nano-silicon modulation layer can grow periodically to form a plurality of periodically distributed heterojunctions; the N-type nano-silicon modulation layer with the narrow band gap is used as a potential well for storing charges, and the amorphous silicon carbide with the wide band gap is used as a potential barrier dielectric layer;
depositing N on the finally prepared N-type nano-silicon modulation layer+A nano-silicon contact layer;
said N+Type-monocrystalline silicon substrate, N+The upper surfaces of the nanometer silicon contact layers are provided with connecting electrodes; oxidizing the outside of the heterojunction formed by the N-type nano silicon/amorphous silicon carbide/N-type nano silicon to generate a silicon dioxide protective layer, and coating a shading layer outside the silicon dioxide protective layer;
to form an electrode/N+Type monocrystalline silicon/N type nano silicon/amorphous silicon carbide/N type nano silicon/N+Nano silicon/electrode-heterojunction multi-potential barrier varactor.
In addition, the invention also provides a nano silicon/amorphous silicon carbide heterojunction multi-barrier varactor which is characterized in that: comprises P+Type-silicon single crystal substrate, P+A P-type nano-silicon modulation layer deposited on the type monocrystalline silicon substrate, an amorphous silicon carbide barrier layer deposited on the P-type nano-silicon modulation layer, and a P-type nano-silicon modulation layer deposited on the amorphous silicon carbide barrier layer;
the heterojunction formed by the P-type nano-silicon modulation layer, the amorphous silicon carbide barrier layer and the P-type nano-silicon modulation layer grows periodically to form a plurality of periodically distributed heterojunctions; in the heterojunction, a P-type nano-silicon modulation layer with a narrow band gap is used as a potential well, and amorphous silicon carbide with a wide band gap is used as a potential barrier;
depositing P on the P-type nanometer silicon modulation layer+A nano-silicon contact layer;
said P+Type-silicon single crystal substrate, P+And the upper surfaces of the nanometer silicon contact layers are connected with electrodes, the outer surfaces of the heterojunction are oxidized to generate a silicon dioxide protective layer, and the outer surface of the silicon dioxide protective layer is coated with a light shielding layer.
Make an electrode/P+Type monocrystalline silicon/P type nano silicon/amorphous silicon carbide/P type nano silicon/P+Nano silicon/electrode-heterojunction multi-potential barrier varactor.
The invention provides a preparation method of a nano silicon/amorphous silicon carbide heterojunction multi-barrier varactor, which comprises the following steps:
(1) selecting N+Model sheetThe crystal plane of the crystalline silicon substrate is one of (100), (110) and (111), the surface is one of positive axis and off-axis, and the carrier concentration range is 5.0 × 1024—9.0×1025Rice and its production process-3Thickness of about 2.0X 10-4Rice, said N+Doping of the type monocrystalline silicon substrate is phosphorus doping;
(2) etching off N with etching liquid at room temperature+Oxidizing the surface of the monocrystalline silicon substrate, and then cleaning and drying;
(3) the method adopts a Plasma Enhanced Chemical Vapor Deposition (PECVD) method to prepare Silane (SiH)4) As a reaction source gas, Phosphine (PH)3) As a dopant gas, hydrogen (H)2) For diluting the carrier gas, the cleaned N is+Placing the type monocrystalline silicon substrate into a reaction chamber of a PECVD system in N+Depositing a phosphorus-doped N-type nano-silicon modulation layer on the polished surface of the type monocrystalline silicon substrate, wherein the carrier concentration range is 1.0 multiplied by 1022—9.0×1023Rice and its production process-3Thickness range of 5.0X 10-8—5.0×10-7The rice has the following technological parameters:
limiting vacuum degree of reaction chamber of PECVD system: not higher than 1.0X 10-4Pa；
Volume ratio of silane to hydrogen: 1.0-1.5: 100;
phosphine to silane doping ratio: 0.5-10.0: 100;
frequency range of Radio Frequency (RF) source used during growth: f is more than or equal to 13.59 and less than or equal to 95.13 MHz;
radio Frequency (RF) power density at growth: 3.0-8.0X 103W.m-2；
Substrate temperature during growth: ts 420-620K;
negative dc bias during growth: vb＝-50—-250V；
Reaction gas pressure during growth: 1.0X 102Pa；
(4) By PECVD using Silane (SiH)4) And methane (CH)4) For mixing the reaction source gases, hydrogen (H)2) Depositing amorphous silicon carbide barrier layer with thickness of 2.0 × 10 on the N-type nanometer silicon modulation layer for diluting carrier gas-8—2.0×10-7Rice and its production processThe parameters are:
limiting vacuum degree of reaction chamber of PECVD system: not higher than 1.0X 10-4Pa；
Frequency range of Radio Frequency (RF) source used during growth: f is more than or equal to 13.59 and less than or equal to 95.13 MHz;
radio Frequency (RF) power density at growth: 3.0-8.0X 103W.m-2；
Substrate temperature during growth: ts 420-620K;
negative dc bias during growth: vb＝-50—-250V；
Reaction gas pressure during growth: 1.0X 102Pa；
Volume ratio of silane to hydrogen: 10.0-15.0: 100;
volume ratio of silane to methane: SiH4/CH4＝1:1；
(5) Depositing a phosphorus-doped N-type nano silicon modulation layer on the amorphous silicon carbide barrier layer obtained in the step (4) by using the process parameters of the step (3), wherein the carrier concentration range is 1.0 multiplied by 1022—9.0×1023Rice and its production process-3Thickness range of 5.0X 10-8—5.0×10-7Rice; a heterojunction constituting one period;
each time the steps (3), (4) and (5) are repeated, heterojunction with one period can be added, and the total period is 2-20;
(6) depositing phosphorus-doped N on the finally deposited N-type nano-silicon modulation layer by adopting a PECVD method and taking silane reaction source gas, phosphine as doping gas and hydrogen as dilution carrier gas+Nano-silicon contact layer with carrier concentration range of 5.0 × 1024—9.0×1025Rice and its production process-3Thickness range of 5.0X 10-7—2.0×10-4The rice has the following technological parameters:
limiting vacuum degree of reaction chamber of PECVD system: not higher than 1.0X 10-4Pa；
Volume ratio of silane to hydrogen: 1-1.5: 100;
phosphine to silane doping ratio: 9.0-15.0: 100;
frequency range of Radio Frequency (RF) source used during growth: f is more than or equal to 13.59 and less than or equal to 95.13 MHz;
radio Frequency (RF) power density at growth: 3.0-8.0X 103W.m-2；
Substrate temperature during growth: ts 420-620K;
negative dc bias during growth: vb＝-50—-250V；
Reaction gas pressure during growth: 1.0X 102Pa；
(7) Etching off N+Type-monocrystalline silicon substrate, N+Cleaning and drying the oxide layer on the upper surface of the nano silicon contact layer; selecting gold-aluminum alloy as raw material, and respectively performing N-phase oxidation and N-phase oxidation by electron beam evaporation+Type-monocrystalline silicon substrate, N+Depositing an aluminum alloy film on the upper surface of the nano silicon contact layer to form ohmic electrodes respectively, wherein the technological parameters are as follows:
ultimate vacuum degree of the electron beam evaporation chamber: not less than 1.0X 10-4Pa；
Filament direct current: i ═ 5-10A;
substrate temperature: ts 420-620K;
thickness of electrode thin film: 5.0-1.0X 10-6Rice;
(8) oxidizing the surface of the heterojunction by adopting a thermal oxidation process to generate a silicon dioxide protective layer;
(9) coating opaque, non-conductive and corrosion-resistant resin outside the silicon dioxide protective layer of the heterojunction to form a light shielding layer;
(10) making into electrode/N+Type monocrystalline silicon/N type nano silicon/amorphous silicon carbide/N type nano silicon/N+Nano silicon/electrode-heterojunction multi-potential barrier varactor.
Advantageous effects of the invention
The embodiment of the invention provides a nano silicon/amorphous silicon carbide heterojunction barrier varactor and a preparation method thereof, and discloses a PECVD method for preparing the nano silicon/amorphous silicon carbide heterojunction barrier varactor, which is compatible with the microelectronic technology, wherein the temperatures for depositing nano silicon, amorphous silicon carbide and alloy electrodes are controlled below 350 ℃, impurity diffusion pollution caused by high temperature in the processes of first processing and later processing is avoided, the quality is ensured, and single-chip integration can be realized by selecting a monocrystalline silicon substrate. The heterojunction barrier varactor prepared by the method has the advantages of small leakage current, small inherent resistance, small capacitance, high capacitance change ratio, high cut-off frequency, high withstand voltage, wide dynamic load modulation range, capacitance change index close to 1 and the like, can be applied to frequency doubling, electric tuning, parameter amplification and the like, and can approximately perform linear frequency modulation. See the data of the examples in particular.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is within the scope of the present invention for those skilled in the art to obtain other drawings based on the drawings without inventive exercise.
Fig. 1 is a schematic diagram of a nano-silicon/amorphous silicon carbide heterojunction multi-barrier varactor and a manufacturing method thereof according to an embodiment of the present invention, where (a) is N+Of a type of single crystal silicon substrate, (b) is P+A type monocrystalline silicon substrate;
fig. 2 is a schematic diagram of an energy band structure and an equivalent capacitor series circuit of the nano-silicon/amorphous silicon carbide heterojunction multi-barrier varactor prepared in the embodiment of the present invention, wherein the energy band structure of the (middle) heterojunction multi-barrier and the (upper) nano-silicon/amorphous silicon carbide/nano-silicon heterojunction barrier equivalent capacitor series circuit are shown;
fig. 3 is a graph of experimental measurement of capacitance-voltage (C-V) relationship of the 2 and 4 periodic heterojunction nano-si/amorphous sic heterojunction multi-barrier varactor provided in the first embodiment of the present invention;
fig. 4 is a graph for measuring the current-voltage (I-V) relationship of the 2 and 4 periodic heterojunction nano-si/amorphous sic heterojunction multi-barrier varactor provided in the first embodiment of the present invention;
fig. 5 is a High Resolution Transmission Electron Microscope (HRTEM) image of a cross section of a single crystal silicon/nano silicon/amorphous silicon carbide portion of a heterojunction multi-barrier varactor provided by an embodiment of the invention;
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.
Example 1
This example 1 provides an electrode/N having a structure as shown in FIG. 1(a) of the specification+Type monocrystalline silicon/N type nano silicon/amorphous silicon carbide/N type nano silicon/N+The nanometer silicon/electrode-heterojunction multi-potential barrier varactor and its preparation method, the said method includes the following steps:
a1, selecting N+A single crystal silicon substrate having a crystal plane of one of (100), (110) and (111), a surface of one of a positive axis and an off-axis, and a carrier concentration in a range of 5.0X 1024—9.0×1025Rice and its production process-3Thickness of about 2.0X 10-4Rice, said N+The doping of the type monocrystalline silicon substrate is phosphorus doping.
A2 at N+Depositing a phosphorus-doped N-type nano-silicon modulation layer on the polished surface of the type monocrystalline silicon substrate, wherein the carrier concentration range is 1.0 multiplied by 1022—9.0×1023Rice and its production process-3Thickness range of 5.0X 10-8—5.0×10-7Rice;
the method for growing the N-type nano silicon modulation layer by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method comprises the following process flows:
(1) selecting N+The crystal plane of the substrate is one of (100), (110) and (111), the surface is one of positive axis and off-axis, and the carrier concentration range is 5.0 × 1024—9.0×1025Rice and its production process-3Thickness of about 2.0X 10-4Rice, said N+Doping of the type monocrystalline silicon substrate is phosphorus doping;
(2) etching off N with etching liquid at room temperature+Oxidizing the surface of the monocrystalline silicon substrate, and then cleaning and drying;
(3) by PECVD using Silane (SiH)4) As a reaction source gas, Phosphine (PH)3) For mixing gas, hydrogen is carried by dilutionGas, the cleaned N+Placing the type monocrystalline silicon substrate into a reaction chamber of a PECVD system in N+Depositing a phosphorus-doped N-type nano-silicon modulation layer on the polished surface of the type monocrystalline silicon substrate, wherein the carrier concentration range is 1.0 multiplied by 1022—9.0×1023Rice and its production process-3Thickness range of 5.0X 10-8—5.0×10-7The rice has the following technological parameters:
limiting vacuum degree of reaction chamber of PECVD system: not higher than 1.0X 10-4Pa；
Volume ratio of silane to hydrogen: 1.0-1.5: 100;
phosphine to silane doping ratio: 0.5-10.0: 100;
frequency range of Radio Frequency (RF) source used during growth: f is more than or equal to 13.59 and less than or equal to 95.13 MHz;
radio Frequency (RF) power density at growth: 3.0-8.0X 103W.m-2；
Substrate temperature during growth: ts 420-620K;
negative dc bias during growth: vb＝-50—-250V；
Reaction gas pressure during growth: 1.0X 102Pa；
(4) By PECVD using Silane (SiH)4) And methane (CH)4) For mixing the reaction source gases, hydrogen (H)2) Depositing amorphous silicon carbide barrier layer with thickness of 2.0 × 10 on the N-type nanometer silicon modulation layer for diluting carrier gas-8—2.0×10-7The rice has the following technological parameters:
limiting vacuum degree of reaction chamber of PECVD system: not higher than 1.0X 10-4Pa；
Frequency range of Radio Frequency (RF) source used during growth: f is more than or equal to 13.59 and less than or equal to 95.13 MHz;
radio Frequency (RF) power density at growth: 3.0-8.0X 103W.m-2；
Substrate temperature during growth: ts 420-620K;
negative dc bias during growth: vb＝-50—-250V；
Reaction gas pressure during growth: 1.0X 102Pa；
Volume ratio of silane to hydrogen: 10.0-15.0: 100;
volume ratio of silane to methane: SiH4/CH4＝1:1；
(5) Depositing a phosphorus-doped N-type nano silicon modulation layer on the amorphous silicon carbide barrier layer by using the process parameters in the step (3), wherein the carrier concentration range is 1.0 multiplied by 1022—9.0×1023Rice and its production process-3Thickness range of 5.0X 10-8—5.0×10-7Rice; a heterojunction constituting one period;
each time the steps (3), (4) and (5) are repeated, heterojunction with one period can be added, and the total period is 2-20;
(6) by PECVD using Silane (SiH)4) Source gas of reaction with Phosphane (PH)3) As a dopant gas, hydrogen (H)2) Depositing P-doped N on the finally deposited N-type nano-silicon modulation layer for diluting carrier gas+Nano-silicon contact layer with carrier concentration range of 5.0 × 1024—9.0×1025Rice and its production process-3Thickness range of 5.0X 10-7—2.0×10-4The rice has the following technological parameters:
limiting vacuum degree of reaction chamber of PECVD system: not higher than 1.0X 10-4Pa；
Volume ratio of silane to hydrogen: 1-1.5: 100;
phosphine to silane doping ratio: 9.0-15.0: 100;
frequency range of Radio Frequency (RF) source used during growth: f is more than or equal to 13.59 and less than or equal to 95.13 MHz;
radio Frequency (RF) power density at growth: 3.0-8.0X 103W.m-2；
Substrate temperature during growth: ts 420-620K;
negative dc bias during growth: vb＝-50—-250V；
Reaction gas pressure during growth: 1.0X 102Pa；
(7) Etching off N+Type-monocrystalline silicon substrate, N+Cleaning and drying the oxide layer on the upper surface of the nano silicon contact layer; gold-aluminum (AuAl) alloy is selected as raw material, electron beam evaporation technology can be used, and N is respectively used+Type-monocrystalline silicon substrate, N+Depositing an aluminum alloy film on the upper surface of the nano silicon contact layer to form ohmic electrodes respectively, wherein the technological parameters are as follows:
ultimate vacuum degree of the electron beam evaporation chamber: not less than 1.0X 10-4Pa；
Filament direct current: i ═ 5-10A;
substrate temperature: ts 420-620K;
thickness of electrode thin film: 5.0-1.0X 10-6Rice;
(8) oxidizing the surface of the heterojunction by adopting a thermal oxidation process to generate a silicon dioxide protective layer;
(9) coating opaque, non-conductive and corrosion-resistant resin outside the silicon dioxide protective layer of the heterojunction to form a light shielding layer;
completing the above nine steps to obtain electrode/N+Type monocrystalline silicon/N type nano silicon/amorphous silicon carbide/N type nano silicon/N+Nano silicon/electrode-heterojunction multi-potential barrier varactor.
In embodiment 1 of the present invention, a wide bandgap amorphous silicon carbide is used as a barrier dielectric layer, and a narrow bandgap N-type nano-silicon is used as a potential well layer. According to the comparability of the preparation method and the material structure, the band gap width E of the amorphous silicon carbide and the N-type nano silicongAre respectively Eg3C-SiC＝3.50eV、Eg-nc-Si＝1.95eV[Solar Energy Materials and Solar Cells,Vol.182,No.9(2018):220-227.]. The N-type nano-silicon/amorphous silicon carbide/N-type nano-silicon in one period form a heterojunction barrier varactor, and the structure is shown in the attached figure 1 in the specification. The capacitance of each heterojunction can be calculated according to the capacitance formula C ═ S/d of the parallel plate capacitor. In the invention, 2 and 4 periods of electrode/N were prepared in example 1+Type monocrystalline silicon/N type nano silicon/amorphous silicon carbide/N type nano silicon/N+Nano silicon/electrode-heterojunction multi-potential barrier varactor, where N+Type monocrystalline silicon substrate carrier concentration 2 x 1025Rice and its production process-3200 microns thick; carrier concentration of N-type nano silicon layer modulation layer 2X 1022Rice and its production process-350nm in thickness; thickness of amorphous silicon carbide layer 25 nm; last layer N+Carrier concentration of nano silicon contact layer is 2X 1025Rice and its production process-3500 nm in thickness; radius of heterojunction barrier varactor 4.0 × 10-4400 microns. The heterojunction multi-barrier varactor with 2 periods and 4 periods is taken as an equivalent capacitor with 2 capacitors and 4 capacitors connected in series, as shown in the attached figure 2 in the specification, wherein a P-type nano silicon layer with a narrow band gap is taken as a potential well, and an amorphous silicon carbide layer with a wide band gap is taken as a potential barrier. When the heterojunction multi-barrier varactor is loaded with voltage, charges are separated in different potential wells by different barriers, which is equivalent to that capacitors are connected in series, as shown in fig. 2. As the voltage is increased step by step, the charges of the different potential wells are depleted step by step. Because each heterojunction barrier capacitor is connected in series, the total capacitance value of the equivalent capacitor is smaller than that of a single capacitor, so that the capacitance value of the varactor containing 4 periodic heterojunctions is smaller than that of the varactor containing 2 periodic heterojunctions, as shown in the attached figure 3 of the specification. That is, the more the heterojunction period, the smaller the total capacitance value of the equivalent capacitor of the heterojunction varactor, the higher the varactor ratio, the larger the amplitude of the modulation signal can be, and the wider the dynamic load modulation range.
However, the more the period of the heterojunction is, the better. Since the amorphous silicon carbide serving as the barrier is not doped, the resistivity thereof is higher than that of the N-type nano silicon. Then, the more cycles of the heterojunction, the larger the total resistance value of the equivalent capacitor, and the slower the forward current through it rises with the forward voltage, as shown in fig. 4, the current of the varactor diode of 4 periodic heterojunction is lower than that of the varactor diode of 2 periodic heterojunction. Because of N+Type-monocrystalline silicon substrate, N+Due to the difference between the nano-silicon contact layers, the capacitance-voltage (C-V) and current-voltage (I-V) relationship curves of the nano-silicon/amorphous silicon carbide heterojunction multi-barrier varactor provided in the first embodiment of the present invention are slightly asymmetric, as shown in fig. 3 and 4, respectively.
When data of the capacitance-voltage (C-V) relationship obtained by testing the varactor diode provided in example 1 of the present invention was simulated, it was found that the data was related to the capacitance-voltage (C-V) relationship of the following varactor diodeJunction capacitance (C)J) The voltage (V) relationship is well matched,
Figure BDA0002948823840000151
in the formula CJ0Junction capacitance at 0 bias, VbiIs the built-in potential of the junction and gamma is the capacitance change index. The capacitance change index gamma of the multi-barrier varactor with 4 periodic nano-silicon/amorphous silicon carbide heterojunction is 1.108, and the gamma of the multi-barrier varactor with 4 periodic nano-silicon/amorphous silicon carbide heterojunction is 1.266. It can be seen that the value of γ is close to 1, and this varactor can approximately achieve chirp in the case of small frequency offsets.
Calculated according to the following formula of the static cut-off frequency,
Figure BDA0002948823840000152
the static cutoff frequency of the 4-period heterojunction multi-barrier varactor provided in example 1 of the present invention is about 0.3THz at 0 bias.
Calculated according to the following formula of the dynamic cut-off frequency,
Figure BDA0002948823840000153
the dynamic cut-off frequency of the varactor provided in embodiment 1 of the present invention is about 5.7 THz. It can be seen that the varactor diode provided in embodiment 1 of the present invention can be applied to the THz field.
When the applied voltage is relatively low (-1-0V, 0-1V), as shown in the area (1) in fig. 4, the current-voltage (I-V) data obtained by experiment is assumed to be simulated, and the current at this time mainly follows the multi-step tunneling capture-emission (MTCE) mechanism,
Figure BDA0002948823840000154
in the formula,. DELTA.EafA is a constant independent of temperature and voltage, kBAnd T is Boltzmann constant and thermodynamic temperature, respectively. The defect states in the nano silicon and the amorphous silicon carbide provide multi-step tunnel channels for carriers to form current. As the applied voltage increases, the current increases, as shown in region (2) — 2 — -1V, 1-2V in fig. 5, and the current at this time is subject to a coincidence mechanism, as predicted by simulation from experimentally measured current-voltage (I-V) data. As the applied voltage continues to rise, the current increases rapidly, as predicted by simulation from experimentally determined current-voltage (I-V) data in region (3) (-2.5- — 2V, 2-2.5V) of FIG. 5, where the current mainly follows the diffusion mechanism. When the applied voltage is further increased, such as the region (3) (-3- — 2.5V, 2.5-3V) in fig. 5, the current increases more slowly, and the current is mainly affected by the diode resistance, which is estimated from the experimentally measured current-voltage data simulation.
According to the current-voltage (I-V) data simulation conjecture measured by experiments, the mass-junction multi-barrier variable capacitance diode provided by the embodiment 1 of the invention has no rectification characteristic and is not a traditional PN junction diode.
N provided in example 1 of the present invention+A High Resolution Transmission Electron Microscope (HRTEM) image of a type monocrystalline silicon substrate/N type nano-silicon modulation layer/amorphous silicon carbide barrier layer structure is shown in figure 5 of the specification.
Example 2
This example 2 provides an electrode/P having a structure as shown in FIG. 1(b) of the specification+Type monocrystalline silicon/P type nano silicon/amorphous silicon carbide/P type nano silicon/P+The nanometer silicon/electrode-heterojunction multi-potential barrier varactor and its preparation method, the said method includes the following steps:
b1, selecting P+The crystal plane of the substrate is one of (100), (110) and (111), the surface is one of positive axis and off-axis, and the carrier concentration range is 5.0 × 1024—9.0×1025Rice and its production process-3Thickness of about 2.0X 10-4Rice, said P+The doping of the type monocrystalline silicon substrate is boron doping.
B2 at P+Type monocrystalline siliconDepositing a boron-doped P-type nano-silicon modulation layer on the polished surface of the substrate, wherein the carrier concentration range is 1.0 multiplied by 1022—9.0×1023Rice and its production process-3Thickness range of 5.0X 10-8—5.0×10-7Rice;
adopting a plasma chemical vapor deposition (PECVD) method to grow a P-type nano silicon modulation layer, comprising the following process flows of:
(1) selecting P+The crystal plane of the substrate is one of (100), (110) and (111), the surface is one of positive axis and off-axis, and the carrier concentration range is 5.0 × 1024—9.0×1025Rice and its production process-3Thickness of about 2.0X 10-4Rice, said P+The doping of the type monocrystalline silicon substrate is boron doping;
(2) etching off P with etching liquid at room temperature+Oxidizing the surface of the monocrystalline silicon substrate, and then cleaning and drying;
(3) the method adopts a Plasma Enhanced Chemical Vapor Deposition (PECVD) method to prepare Silane (SiH)4) Diborane (B) is used as a reaction source gas2H6) As a dopant gas, hydrogen (H)2) For diluting the carrier gas, the cleaned P is+Placing the type monocrystalline silicon substrate into a reaction chamber of a PECVD system in P+Depositing a boron-doped P-type nano-silicon modulation layer on the polished surface of the type monocrystalline silicon substrate, wherein the carrier concentration range is 1.0 multiplied by 1022—9.0×1023Rice and its production process-3Thickness range of 5.0X 10-8—5.0×10-7The rice has the following technological parameters:
limiting vacuum degree of reaction chamber of PECVD system: not higher than 1.0X 10-4Pa；
Volume ratio of silane to hydrogen: 1.0-1.5: 100;
diborane to silane doping ratio: 0.5-10.0: 100;
frequency range of Radio Frequency (RF) source used during growth: f is more than or equal to 13.59 and less than or equal to 95.13 MHz;
radio Frequency (RF) power density at growth: 3.0-8.0X 103W.m-2；
Substrate temperature during growth: ts 420-620K;
negative dc bias during growthPressing: vb＝-50—-250V；
Reaction gas pressure during growth: 1.0X 102Pa；
(4) By PECVD using Silane (SiH)4) And methane (CH)4) For mixing the reaction source gases, hydrogen (H)2) Depositing amorphous silicon carbide barrier layer with thickness of 2.0 × 10 on the P-type nanometer silicon modulation layer for diluting carrier gas-8—2.0×10-7The rice has the following technological parameters:
limiting vacuum degree of reaction chamber of PECVD system: not higher than 1.0X 10-4Pa；
Frequency range of Radio Frequency (RF) source used during growth: f is more than or equal to 13.59 and less than or equal to 95.13 MHz;
radio Frequency (RF) power density at growth: 3.0-8.0X 103W.m-2；
Substrate temperature during growth: ts 420-620K;
negative dc bias during growth: vb＝-50—-250V；
Reaction gas pressure during growth: 1.0X 102Pa；
Volume ratio of silane to hydrogen: 10.0-15.0: 100;
volume ratio of silane to methane: SiH4/CH4＝1:1；
(5) Depositing a boron-doped P-type nano-silicon modulation layer on the amorphous silicon carbide barrier layer by using the process parameters in the step (3), wherein the carrier concentration range is 1.0 multiplied by 1022—9.0×1023Rice and its production process-3Thickness range of 5.0X 10-8—5.0×10-7Rice; a heterojunction constituting one period;
each time the steps (3), (4) and (5) are repeated, heterojunction with one period can be added, and the total period is 2-20;
(6) by PECVD using Silane (SiH)4) Diborane (B) is used as a reaction source gas2H6) As a dopant gas, hydrogen (H)2) In order to dilute the carrier gas, the boron-doped P is deposited on the P-type nano-silicon modulation layer deposited finally+Nano-silicon contact layer with carrier concentration range of 5.0 × 1024—9.0×1025Rice and its production process-3Thickness range of 5.0X 10-7—2.0×10-4The rice has the following technological parameters:
limiting vacuum degree of reaction chamber of PECVD system: not higher than 1.0X 10-4Pa；
Volume ratio of silane to hydrogen: 1-1.5: 100;
diborane to silane doping ratio: 9.0-15.0: 100;
frequency range of Radio Frequency (RF) source used during growth: f is more than or equal to 13.59 and less than or equal to 95.13 MHz;
radio Frequency (RF) power density at growth: 3.0-8.0X 103W.m-2；
Substrate temperature during growth: ts 420-620K;
negative dc bias during growth: vb＝-50—-250V；
Reaction gas pressure during growth: 1.0X 102Pa；
(7) Etching off P+Type-silicon single crystal substrate, P+Cleaning and drying the oxide layer on the upper surface of the nano silicon contact layer; selecting gold-aluminum alloy as raw material, and respectively performing P-phase oxidation and P-phase oxidation by electron beam evaporation+Type-silicon single crystal substrate, P+Depositing an aluminum alloy film on the upper surface of the nano silicon contact layer to form ohmic electrodes respectively, wherein the technological parameters are as follows:
ultimate vacuum degree of the electron beam evaporation chamber: not less than 1.0X 10-4Pa；
Filament direct current: i ═ 5-10A;
substrate temperature: ts 420-620K;
thickness of electrode thin film: 5.0-1.0X 10-6Rice;
(8) oxidizing the surface of the heterojunction by adopting a thermal oxidation process to generate a silicon dioxide protective layer;
(9) coating opaque, non-conductive and corrosion-resistant resin outside the silicon dioxide protective layer of the heterojunction to form a light shielding layer;
completing the above nine steps to form electrode/P+Type monocrystalline silicon/P type nano silicon/amorphous silicon carbide/P type nano silicon/P+Nano silicon/electricityPole-heterojunction multi-barrier varactor.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and it is therefore to be understood that the invention is not limited by the scope of the appended claims.

Claims (9)

1. A nanometer silicon/amorphous silicon carbide heterojunction multi-barrier varactor is characterized in that: comprising N+Type-monocrystalline silicon substrate, N+An N-type nano-silicon modulation layer deposited on the type monocrystalline silicon substrate, an amorphous silicon carbide barrier layer deposited on the N-type nano-silicon modulation layer, and an N-type nano-silicon modulation layer deposited on the amorphous silicon carbide barrier layer;
the heterojunction formed by the N-type nano-silicon modulation layer, the amorphous silicon carbide barrier layer and the N-type nano-silicon modulation layer grows periodically to form a plurality of periodically distributed heterojunctions; in the heterojunction, the N-type nano-silicon modulation layer with narrow band gap is used as a potential well, and the amorphous silicon carbide with wide band gap is used as a potential barrier;
depositing N on the finally prepared N-type nano-silicon modulation layer+A nano-silicon contact layer;
said N+Type-monocrystalline silicon substrate, N+The upper surfaces of the type nanometer silicon contact layers are all connected with electrodes, a silicon dioxide protective layer is generated by oxidizing the outer surface of a heterojunction formed by the N type nanometer silicon modulation layer, the amorphous silicon carbide barrier layer and the N type nanometer silicon modulation layer, and a light shielding layer is coated outside the heterojunction.
2. The nano-silicon/amorphous silicon carbide heterojunction multi-barrier varactor of claim 1, wherein: the electrode is a gold-aluminum alloy ohmic electrode.
3. The nano-silicon/amorphous silicon carbide heterojunction multi-barrier varactor of claim 1, wherein: said N is+The crystal plane of the single crystal silicon substrate is one of (100) crystal plane, (110) crystal plane and (111) crystal plane, the surface is one of positive axis and off-axis, and the carrier concentration range is 5.0 × 1024—9.0×1025Rice and its production process-3Thickness of about 2.0X 10-4Rice, said N+The doping of the type monocrystalline silicon substrate is phosphorus doping.
4. The nano-silicon/amorphous silicon carbide heterojunction multi-barrier varactor of claim 1, wherein: said N is+N-type nano-silicon modulation layer deposited on type monocrystalline silicon substrate and having carrier concentration range of 1.0 × 1022—9.0×1023Rice and its production process-3Thickness range of 5.0X 10-8—5.0×10-7And the doping of the N-type nano silicon modulation layer is phosphorus doping.
5. The nano-silicon/amorphous silicon carbide heterojunction multi-barrier varactor of claim 1, wherein: the amorphous silicon carbide barrier layer deposited on the N-type nano-silicon modulation layer has a thickness of 2.0 x 10-8—2.0×10-7And m, the amorphous silicon carbide barrier layer is not intentionally doped.
6. The nano-silicon/amorphous silicon carbide heterojunction multi-barrier varactor of claim 1, wherein: the heterojunction formed by the N-type nano-silicon modulation layer, the amorphous silicon carbide barrier layer and the N-type nano-silicon modulation layer has 2-20 periods.
7. The nano-silicon/amorphous silicon carbide heterojunction multi-barrier varactor of claim 1, wherein: depositing N on the finally prepared N-type nano-silicon modulation layer+Nano-silicon contact layer with carrier concentration range of 5.0 × 1024—9.0×1025Rice and its production process-3Thickness range of 5.0X 10-7—2.0×10-4Rice, said N+The doping of the nano silicon contact layer is phosphorus doping.
8. The preparation method of the nano-silicon/amorphous silicon carbide heterojunction multi-barrier varactor according to claim 1, characterized by comprising the following steps:
(1) selecting N+The crystal plane of the substrate is one of (100), (110) and (111), the surface is one of positive axis and off-axis, and the carrier concentration range is 5.0 × 1024—9.0×1025Rice and its production process-3Thickness of about 2.0X 10-4Rice, said N+Doping of the type monocrystalline silicon substrate is phosphorus doping;
(2) etching off N with etching liquid at room temperature+Oxidizing the surface of the monocrystalline silicon substrate, and then cleaning and drying;
(3) adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, taking silane as reaction source gas, taking phosphine as doping gas and taking hydrogen as dilution carrier gas, and cleaning N+Placing the type monocrystalline silicon substrate into a reaction chamber of a PECVD system in N+Depositing a phosphorus-doped N-type nano-silicon modulation layer on the polished surface of the type monocrystalline silicon substrate, wherein the carrier concentration range is 1.0 multiplied by 1022—9.0×1023Rice and its production process-3Thickness range of 5.0X 10-8—5.0×10-7The rice has the following technological parameters:
limiting vacuum degree of reaction chamber of PECVD system: not higher than 1.0X 10-4Pa；
Volume ratio of silane to hydrogen: 1.0-1.5: 100;
phosphine to silane doping ratio: 0.5-10.0: 100;
frequency range of Radio Frequency (RF) source used during growth: f is more than or equal to 13.59 and less than or equal to 95.13 MHz;
radio Frequency (RF) power density at growth: 3.0-8.0X 103W.m-2；
Substrate temperature during growth: ts 420-620K;
negative dc bias during growth: vb＝-50—-250V；
Reaction gas pressure during growth: 1.0X 102Pa；
(4) Depositing an amorphous silicon carbide barrier layer with the thickness range of 2.0 multiplied by 10 on the N-type nano-silicon modulation layer by adopting a PECVD method and taking silane and methane as mixed reaction source gas and hydrogen as diluted carrier gas-8—2.0×10-7The rice has the following technological parameters:
PECVD system reaction chamber poleLimiting the vacuum degree: not higher than 1.0X 10-4Pa；
Frequency range of Radio Frequency (RF) source used during growth: f is more than or equal to 13.59 and less than or equal to 95.13 MHz;
radio Frequency (RF) power density at growth: 3.0-8.0X 103W.m-2；
Substrate temperature during growth: ts 420-620K;
negative dc bias during growth: vb＝-50—-250V；
Reaction gas pressure during growth: 1.0X 102Pa；
Volume ratio of silane to hydrogen: 10.0-15.0: 100;
volume ratio of silane to methane: SiH4/CH4＝1:1；
(5) Depositing a phosphorus-doped N-type nano silicon modulation layer on the amorphous silicon carbide barrier layer by using the process parameters in the step (3), wherein the carrier concentration range is 1.0 multiplied by 1022—9.0×1023Rice and its production process-3Thickness range of 5.0X 10-8—5.0×10-7Rice; the N-type nano-silicon modulation layer, the amorphous silicon carbide barrier layer and the N-type nano-silicon modulation layer form a periodic heterojunction;
each time the steps (3), (4) and (5) are repeated, heterojunction with one period can be added, and the total period is 2-20;
(6) depositing phosphorus-doped N on the finally prepared N-type nano-silicon modulation layer by adopting a PECVD method and taking silane reaction source gas, phosphine as doping gas and hydrogen as dilution carrier gas+Nano-silicon contact layer with carrier concentration range of 5.0 × 1024—9.0×1025Rice and its production process-3Thickness range of 5.0X 10-7—2.0×10-4The rice has the following technological parameters:
limiting vacuum degree of reaction chamber of PECVD system: not higher than 1.0X 10-4Pa；
Volume ratio of silane to hydrogen: 1-1.5: 100;
phosphine to silane doping ratio: 9.0-15.0: 100;
frequency range of Radio Frequency (RF) source used during growth: f is more than or equal to 13.59 and less than or equal to 95.13 MHz;
radio Frequency (RF) power during growthDensity: 3.0-8.0X 103W.m-2；
Substrate temperature during growth: ts 420-620K;
negative dc bias during growth: vb＝-50—-250V；
Reaction gas pressure during growth: 1.0X 102Pa；
(7) Etching off N+Type-monocrystalline silicon substrate, N+Cleaning and drying the oxide layer on the upper surface of the nano silicon contact layer; selecting gold-aluminum alloy as raw material, and respectively performing N-phase oxidation and N-phase oxidation by electron beam evaporation+Type-monocrystalline silicon substrate, N+Depositing an aluminum alloy film on the upper surface of the nano silicon contact layer to form ohmic electrodes respectively, wherein the technological parameters are as follows:
ultimate vacuum degree of the electron beam evaporation chamber: not less than 1.0X 10-4Pa；
Filament direct current: i ═ 5-10A;
substrate temperature: ts 420-620K;
thickness of electrode thin film: 5.0-1.0X 10-6Rice;
(8) oxidizing the surface of the heterojunction by using a thermal oxidation process to generate a silicon dioxide protective layer;
(9) coating opaque, non-conductive and corrosion-resistant resin outside the silicon dioxide protective layer of the heterojunction to form a light shielding layer;
(10) making into electrode/N+Type monocrystalline silicon/N type nano silicon/amorphous silicon carbide/N type nano silicon/N+Nano silicon/electrode-heterojunction multi-potential barrier varactor.
9. A nanometer silicon/amorphous silicon carbide heterojunction multi-barrier varactor is characterized in that: including P+Type-silicon single crystal substrate, P+A P-type nano-silicon modulation layer deposited on the type monocrystalline silicon substrate, an amorphous silicon carbide barrier layer deposited on the P-type nano-silicon modulation layer, and a P-type nano-silicon modulation layer deposited on the amorphous silicon carbide barrier layer;
the heterojunction formed by the P-type nano-silicon modulation layer, the amorphous silicon carbide barrier layer and the P-type nano-silicon modulation layer grows periodically to form a plurality of periodically distributed heterojunctions; in the heterojunction, a P-type nano-silicon modulation layer with a narrow band gap is used as a potential well, and amorphous silicon carbide with a wide band gap is used as a potential barrier;
depositing P on the P-type nanometer silicon modulation layer+A nano-silicon contact layer;
said P+Type-silicon single crystal substrate, P+And the upper surfaces of the nanometer silicon contact layers are connected with electrodes, the outer surfaces of the heterojunction are oxidized to generate a silicon dioxide protective layer, and the outer surface of the silicon dioxide protective layer is coated with a light shielding layer. Make an electrode/P+Type monocrystalline silicon/P type nano silicon/amorphous silicon carbide/P type nano silicon/P+Nano silicon/electrode-heterojunction multi-potential barrier varactor.
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