CN113009425B

CN113009425B - Pulse compression structure based on SiC DSRD device

Info

Publication number: CN113009425B
Application number: CN202110199288.XA
Authority: CN
Inventors: 陈万军; 张柯楠; 孙瑞泽; 夏云
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2021-02-23
Filing date: 2021-02-23
Publication date: 2022-08-05
Anticipated expiration: 2041-02-23
Also published as: CN113009425A

Abstract

The invention relates to power semiconductor technology, in particular to a pulse compression structure for a SiC DSRD device. The pulse compression structure based on the SIC DSRD device comprises a basic signal generator, a pulse compression technology and pulse output, wherein the pulse compression technology comprises a multi-path parallel structure and a multi-stage series structure, the pulse compression of the DSRD device is realized through multi-path parallel and multi-stage series, and the pulse output peak value can be greatly increased and the pulse leading edge can be greatly shortened. The invention overcomes the defects of low pulse output, slow pulse leading edge and low frequency characteristic of the traditional pulse output method of the SiC DSRD device.

Description

Pulse compression structure based on SiC DSRD device

Technical Field

The invention belongs to the technical field of power semiconductors, and particularly relates to a pulse compression structure based on a SIC DSRD device.

Background

The SiC DSRD device is an all-solid-state, high-speed, small and high-power advanced semiconductor switch, the excellent performance of the SiC DSRD device has remarkable advantages in the radar field, and a pulse output method of the conventional SiC DSRD device is used for simply outputting pulses based on the principle of the DSRD device, as shown in figure 1, but the potential of the DSRD device in the application field is inhibited due to the low pulse output, the long pulse leading edge, the poor high-frequency characteristic and the like.

Disclosure of Invention

The invention aims to solve the problems and provides a pulse compression structure based on a SiC DSRD device.

The technical scheme of the invention is as follows: a pulse compression structure based on a SiC DSRD device comprises a pulse emission source, a pulse compression structure and a pulse output, wherein the pulse emission source comprises a pulse generation device and a driving device which are connected, and the pulse compression structure is characterized by comprising a plurality of pulse compression units, wherein each pulse compression unit comprises a power supply, a first inductor L3, a second inductor L4, a third inductor L5, a first capacitor C3, a second capacitor C4, a third capacitor C5, a switching MOS (metal oxide semiconductor) tube, a first resistor R4, a second resistor R5, a first SiC DSRD device DSRD1 and a second SiC DSRD device DSRD 2; the power supply is connected with the drain electrode of the switch MOS tube through the first inductor L3, the grid electrode of the switch MOS tube is connected with the output end of the driving device, and the source electrode of the switch MOS tube is grounded; the connection point of the first inductor L3 and the drain electrode of the switch MOS tube is grounded through a first capacitor C3, the connection point of the first inductor L3 and the drain electrode of the switch MOS tube is grounded through a second inductor L4 and then connected with the cathode of a first SiC DSRD device DSRD1, and the anode of the first SiC DSRD device DSRD1 is grounded through a second capacitor C4; the connection point of the first SiC DSRD device DSRD1 and the second capacitor C4 is connected with a power supply through a first capacitor R4; the connection point of the second inductor L4 and the first SiC DSRD device DSRD1 is connected with one end of a third inductor L5, the other end of the third inductor L5 is connected with the cathode of a second SiC DSRD device DSRD2, and the anode of the second SiC DSRD device DSRD2 is grounded after passing through a third capacitor C5; the connection point of the second SiC DSRD device DSRD2 and the third capacitor C5 is connected with a power supply through a second capacitor R5;

the pulse compression units are connected in parallel to form a parallel branch, and in the pulse compression units, a first inductor L3, a switching MOS (metal oxide semiconductor) tube, a second inductor L4, a first capacitor C3, a first SiC DSRD device DSRD1, a second capacitor C4 and a first resistor R4 form a preceding stage structure; the third inductor L5, the second SiC DSRD device DSRD2, the third capacitor C5 and the second resistor R5 form a rear-stage structure, the rear-stage structure can be stacked in series, the series connection mode is that the connection point of the third inductor L5 and the second SiC DSRD device DSRD2 is used as an output end and is connected with the inductor of the next rear-stage structure, the connection point of the inductor of the last rear-stage structure and the SiC DSRD device is used as the output end of the series branch, and the output ends of all the series branches are connected to be output as final pulse.

The invention has the beneficial effects that the multi-path parallel and multi-stage series structure can be used for compressing the pulse output of the SiC DSRD device by carrying out a plurality of superpositions. The pulse output of the DSRD device can be obviously increased, the pulse output limit of the device can be reached, and compared with the pulse output of the existing DSRD device, the peak value is increased and the pulse front edge is compressed.

Drawings

FIG. 1 is a conventional DSRD device pulse circuit diagram;

FIG. 2 is a schematic diagram of a pulse compression architecture for a SiC DSRD device of the present invention;

FIG. 3 is a circuit schematic of a compression architecture;

FIG. 4 is a functional diagram of a DSRD device;

FIG. 5 is a graph of test results;

Detailed Description

The invention is described in detail below with reference to the attached drawing

Fig. 2 is a schematic diagram of a pulse compression structure for a SiC DSRD device according to the present invention. The working principle is as follows: as shown in fig. 4, the basic DSRD device works according to the principle that the DSRD device is positively injected with plasma in the forward conduction stage, the power supply stores energy in the energy storage element in the circuit, the switching tube is turned off, the plasma in the DSRD device is extracted, the plasma is evacuated, and the depletion region is rapidly expanded, so that ultra-rapid blocking is realized, and high pulse output is generated. The main purpose of the technology is to compress the previous process, wherein the multiple paths are connected in parallel to increase the current during forward injection, the multiple paths are connected in parallel to achieve the purpose, the current is increased, the peak value of pulse output is increased, as shown in fig. 3, the power supply is turned on, the energy storage element is charged, the DSRD device forward process is achieved, then the signal source is turned on, a pulse signal is given, the switching tube is turned on, the capacitor discharges at the moment, the plasma of the DSRD device is extracted, the DSRD device blocking process is achieved, and the forward process can be optimized through the multiple paths. When the multi-stage series connection is used for blocking the reverse direction, the speed of the reverse extraction is increased, and di/dt is increased, so that the purpose of outputting compressed pulses is achieved, as shown in 3 in fig. 3, at the beginning, the switching tube is closed, the power supply is turned on, each DSRD device is in a forward state, after the charging is finished, the signal source provides a pulse signal, at the moment, the DSRD enters a blocking stage, because the DSRD device at the previous stage is blocked in one step, the pulse output generated by the DSRD is output, at the moment, the plasma of the DSRD at the later stage is also extracted, the extraction process at the later stage is accelerated, i.e. di/dt in the DSRD blocking process is increased, so that the compressed pulse output is achieved. Experimental test results as shown in fig. 5, the test uses a 4-way 2-stage compression technique, and it can be seen that the output of the rear stage DSRD V2 is 3.42 times that of the front stage DSRD V1. Compare in traditional DSRD pulse output circuit, the pulse current of the available DSRD output of forward in-process superposes rather than only carrying out the forward injection to DSRD with energy storage element, blocks the in-process, and the pulse current of the available DSRD output extracts fast, and traditional electric capacity discharge speed is showing the output pulse that is less than DSRD to reach and show the effect that promotes the pulse peak value, and the compression pulse forward edge.

Claims

1. A pulse compression structure based on a SiC DSRD device comprises a pulse emission source, a pulse compression structure and a pulse output, wherein the pulse emission source comprises a pulse generation device and a driving device which are connected, and the pulse compression structure is characterized by comprising a plurality of pulse compression units, wherein each pulse compression unit comprises a power supply, a first inductor L3, a second inductor L4, a third inductor L5, a first capacitor C3, a second capacitor C4, a third capacitor C5, a switching MOS (metal oxide semiconductor) tube, a first resistor R4, a second resistor R5, a first SiC DSRD device DSRD1 and a second SiC DSRD device DSRD 2; the power supply is connected with the drain electrode of the switch MOS tube through the first inductor L3, the grid electrode of the switch MOS tube is connected with the output end of the driving device, and the source electrode of the switch MOS tube is grounded; the connection point of the first inductor L3 and the drain electrode of the switch MOS tube is grounded through a first capacitor C3, the connection point of the first inductor L3 and the drain electrode of the switch MOS tube is grounded through a second inductor L4 and then connected with the cathode of a first SiC DSRD device DSRD1, and the anode of the first SiC DSRD device DSRD1 is grounded through a second capacitor C4; the connection point of the first SiC DSRD device DSRD1 and the second capacitor C4 is connected with a power supply through a first capacitor R4; the connection point of the second inductor L4 and the first SiC DSRD device DSRD1 is connected with one end of a third inductor L5, the other end of the third inductor L5 is connected with the cathode of a second SiC DSRD device DSRD2, and the anode of the second SiC DSRD device DSRD2 is grounded after passing through a third capacitor C5; the connection point of the second SiC DSRD device DSRD2 and the third capacitor C5 is connected with a power supply through a second capacitor R5;

the front-stage structures of a plurality of pulse compression units are connected in parallel to form a parallel branch, and in the pulse compression units, a first inductor L3, a switch MOS (metal oxide semiconductor) tube, a second inductor L4, a first capacitor C3, a first SiC DSRD device DSRD1, a second capacitor C4 and a first resistor R4 form the front-stage structures; and the third inductor L5, the second SiC DSRD device DSRD2, the third capacitor C5 and the second resistor R5 form a rear-stage structure, the rear-stage structure is superposed in series, the series connection mode is that the connection point of the third inductor L5 and the second SiC DSRD device DSRD2 is used as an output end and is connected with the inductor of the next rear-stage structure, the connection point of the inductor of the last rear-stage structure and the SiC DSRD device is used as the output end of the series branch, and the output ends of all the series branches are connected to be output as final pulse.