CN112998720B - Intelligent early-warning wearable heart rate monitoring circuit and control method thereof - Google Patents
Intelligent early-warning wearable heart rate monitoring circuit and control method thereof Download PDFInfo
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Abstract
The invention provides an intelligent early warning wearable heart rate monitoring circuit and a control method thereof, wherein the input end of a characteristic acquisition circuit is connected with the output end of an external sensor, four branches are arranged in the characteristic acquisition circuit, transmission gate circuits electrically connected with a controller are correspondingly arranged on each branch, voltage setting thresholds of the transmission gate circuits are respectively VsetP, vsetR, vsetT and VsetU for correspondingly separating P waves, R waves, T waves and U waves, the output end of the characteristic acquisition circuit is connected with a multi-layer learning circuit, the output end of the multi-layer learning circuit is respectively connected with the controller and is used for transmitting the P waves, the R waves, the T waves and the U waves after noise removal of the multi-layer learning circuit, an alarm structure is a plurality of led lamps respectively corresponding to the P waves, the R waves, the T waves and the U waves, and the led lamps are respectively connected with control pins of the controller. To extend the endurance of the wearable device.
Description
Technical Field
The invention relates to the technical field of extraction of physiological electric signals, in particular to an intelligent early-warning wearable heart rate monitoring circuit and a control method thereof.
Background
The physiological signals comprise heart rate signals, pulse signals and other weak signals, the wearable device needs to detect the physiological signals of a wearer in a multi-state complex measuring environment, and meanwhile, the physiological signals detected by the wearable device are mixed with very strong part of background noise.
Each cardiac cycle in the conventional heart rate physiological electrical signal ECG signal is composed of a series of regular waveform signals, wherein the waveform signals comprise P-waves, R-waves, T-waves and U-waves, and the starting points, the ending points, the peaks, the troughs and the intervals of the waveforms record the detailed information of the heart activity state respectively, so that an important analysis basis is provided for diagnosing heart diseases.
Thus, if the waveform characteristics of the physiological electrical signal are extracted accurately, the waveform characteristics play a critical role in the subsequent analysis of the physiological electrical signal. For the traditional physiological electric signal characteristic extraction, time-frequency analysis is generally adopted to classify signal waveforms, then extraction operation is needed through software calculation in a controller, a large amount of calculation is needed to be carried out on the physiological electric signal in the software calculation to obtain each waveform in the physiological electric signal, and the controller needs long-time calculation to separate each waveform, so that a large amount of electric quantity of the wearable device is consumed by the calculation of the controller, and the endurance time of the wearable device is reduced.
Disclosure of Invention
The invention aims to provide an intelligent early-warning wearable heart rate monitoring circuit and a control method thereof, which are used for reducing the operation quantity in a controller in the physiological electric signal characteristic extraction process, so as to reduce the electric quantity loss of wearable equipment and prolong the endurance time of the wearable equipment.
Therefore, the intelligent early-warning wearable heart rate monitoring circuit comprises a controller, a characteristic acquisition circuit, an alarm structure and a multi-layer learning circuit, wherein the input end of the characteristic acquisition circuit is connected with the output end of an external sensor, the external sensor is used for acquiring human physiological electric signals, four branches are arranged in the characteristic acquisition circuit, the input ends of all branches are connected with the input end of the characteristic acquisition circuit, a transmission gate circuit electrically connected with the controller is correspondingly arranged on each branch, the voltage setting threshold value of each transmission gate circuit is respectively voltage VsetP, voltage VsetR, voltage VsetT and voltage VsetU, each transmission gate circuit is respectively corresponding to and separating P wave, R wave, T wave and U wave, the output end of the characteristic acquisition circuit is provided with four pins which are respectively connected with the multi-layer learning circuit, the four output ends of the multi-layer learning circuit are respectively connected with the four pins of the controller, the P wave, the R wave, the T wave and the U wave are correspondingly arranged on each branch, the alarm structure is respectively corresponding to the P wave, the R wave, the T wave and the U wave, and the LED lamp are respectively connected with the controller.
Further, the structure of any one of the transmission gates is as follows: the transmission gate circuit comprises a memristor, two CMOS transmission gates and two diodes, the G pole of a PMOS tube in the CMOS1 transmission gate is connected with the P pole of a diode J1, the N pole of the diode J1 is connected with the G pole of an NMOS tube in the CMOS1 transmission gate, the G pole of an NMOS tube in the CMOS2 transmission gate is connected with the P pole of a diode J2, the N pole of the diode J2 is connected with the G pole of the PMOS tube in the CMOS2 transmission gate, the input end of the CMOS1 transmission gate is used as the input end of the characteristic acquisition circuit, the output end of the CMOS1 transmission gate is connected with the input end of the memristor, the output end of the memristor is used as four waveform signals of P wave, R wave, T wave and U wave which are output by the output end of the characteristic acquisition circuit, and the two ends of the memristor are respectively connected with a power supply to obtain small current.
Further, the multi-layer learning circuit comprises a first neural network layer and a second neural network layer, wherein the first neural network layer comprises a feedback regulation module and a feedforward calculation module, the second neural network layer comprises a sampling holder, an error calculation circuit, a feedback regulation module and a feedforward calculation module, the input end of the feedforward calculation module in the first neural network layer is connected with the output end of the feedback regulation module of the feedforward calculation module in the first neural network layer, the output end of the feedforward calculation module in the first neural network layer is connected with the input end of the feedforward calculation module in the second neural network layer, the output end of the feedforward calculation module in the second neural network layer is divided into two branches, one branch is connected with the input end of the second neural network layer by adopting the holder, the other branch is connected with the input end of the amplifier after being connected with a resistor in series, the output end of the amplifier is connected with the input end of the I/O end of the controller so as to output voltage V0, the output end of the sampling holder 3 in the second neural network layer is connected with the input end of the error calculation circuit, the output end of the error calculation circuit in the second neural network layer is connected with the input end of the feedback regulation module, the output end of the feedback regulation module in the second neural network layer is divided into two branches, and the output end of the feedback regulation module in the second neural network layer is connected with the other branch is connected with the input end of the feedback regulation module.
Further, the second neural network layer includes a sample holder, an error calculation circuit, a feedback adjustment module, and a feedforward calculation module, where the feedforward calculation module is composed of multiple memristive synapse modules and an activation module, each memristive synapse module is provided with an input end and two output ends for converting an input voltage into two different currents, the input end of each memristive synapse module is connected with each sensor for detecting a biological function signal through an electric control switch Fi of an electric connection controller to collect a voltage Vi converted by the biological function signal, the activation module is provided with two input ends and an output end, the two input ends of the activation module are connected with the two output ends of each memristive synapse module, and the activation module uses pure mode electricity to perform algorithmw i V i The output end of the activation module is connected with the input end of the sampling holder to sample and hold the voltage Vg, and the output end of the sampling holder is connected with the I/O end of the controller to output the voltage V0; the error calculation circuit is provided with an input end, a voltage expected input end and two output ends, the input ends of the error calculation circuit are connected to a connecting circuit of the sampling holder and the controller to collect voltage V0, one pin of the controller is connected to the voltage expected input end of the error calculation circuit to transmit expected voltage VT, the error calculation circuit obtains errors +DeltaV and-DeltaV in a pure analog electricity mode through an algorithm DeltaV=a (VT-V0), a is a proportionality coefficient, a=R2/R1 and is respectively output through the two output ends of the error calculation circuit, a feedback regulation module is provided with a plurality of pairs of switch branches corresponding to a plurality of memristive synaptic modules, each pair of switch branches comprises a Pmos tube and an Nmos tube with a common G pole, the D pole and the G pole of any pair of Pmos tubes are connected together to form the output end of the corresponding switch branch, the voltage Vpi after being filtered by the voltage Pmos tube or the Nmos tube is used for outputting the voltage Vpi after being subjected to the voltage filtration, the polarity of the voltage Vi and the voltage i are the polarity of the error is the same on a circuit of the error +DeltaV, and the polarity of the voltage Vi is the voltage Vpi is opposite to the voltage Vpi To, the output end of each pair of switch branch circuits is connected with the input end of the memristive synaptic module corresponding to the switch branch circuits to transmit the voltage Vpi, and an electric control switch Si electrically connected with the controller is connected in series on the connecting line, the S pole of each Pmos tube is connected with one output end of the error calculation circuit to receive +DeltaV, the S pole of each Nmos tube is connected with the other output end of the error calculation circuit to receive-DeltaV, the error calculation circuit, the feedback regulation module, the feedforward calculation module and the controller are respectively connected with a power supply to take electricity, and i=1, 2 and 3 … n.
Further, each memristive synaptic module is provided with a memristor GI+ and a memristor GI-, wherein the anode of the memristor GI+ is connected with the cathode of the memristor GI-, and the voltage input end of the memristor synaptic module is connected on the connecting line of the anode of the memristor GI+ and the memristor GI-, so as to transmit the detection value of the sensor.
Further, two input ends of the activation module are I-, I+ ends respectively, a negative electrode of the memristor GI+ is connected with the I+ end of the activation module, a positive electrode of the memristor GI-is connected with the I-end of the activation module, and the activation module carries out operational amplification on current input by the I-, I+ to obtain voltage Vg, and the voltage Vg is transmitted to the acquisition retainer.
Further, the sample holder includes voltage receiving end, resistance R10, automatically controlled switch Fi, electric capacity C1, buffer amplifier A, and resistance R10's one end is connected with voltage receiving end, and the other end is connected with common C utmost point buffer amplifier A's input, and automatically controlled switch Fi sets up on resistance R10 and buffer amplifier A's connecting wire, and electric capacity C1's one end sets up on automatically controlled switch Fi has buffer amplifier A's connecting wire, and electric control switch Fi is connected with the controller electricity.
Further, the error calculation circuit comprises a resistor, a Zi structure formed by two PMOS with G electrode interconnection, and a Ki structure formed by two NMOS with G electrode interconnection, wherein the resistor, the Zi structure and the Ki structure are respectively provided with four, vcc is the positive voltage of a power supply, vss is the negative voltage of the power supply, a PMOS tube P1 and an NMOS tube N1 are sequentially connected in series between Vcc and Vss, the G electrode and the D electrode of the PMOS tube P1 are connected together and then are connected with Vcc to be powered on, and the S electrode of the PMOS tube P1 and the D electrode of the NMOS tube N1 are connectedThe voltage-DeltaV on the connecting pipeline is collected by the controller, the S pole of the NMOS tube N1 is connected with the Vss, the G pole of the NMOS tube N1 is suspended, the voltage measuring pin of the controller is connected on the connecting line of the Kb end of the structure K6 and the Zb end of the structure Z6, one end of the resistor R1 is connected on the connecting line of the Kd end of the structure K6 and the Zd end of the structure Z6, and the controller is connected with the other end of the resistor R1 to collect the expected voltage V T The Kc end of the structure K6 is connected with the Za end of the structure Z5, the Ka end of the structure K6 is connected with the Zb end and the Zd end of the structure Z5 together after being connected with the resistor R4 in series, the Zc end of the structure Z6 is connected with the Ka end of the structure K5, the Za end of the structure Z6 is connected with the Vcc after being connected with the Kb end and the Kd end of the structure K5 together after being connected with the resistor R3 in series, the Kc end of the structure K5 is connected with the Zc end of the structure Z5, the G electrode of the NMOS tube N1 is connected on the circuit, the controller collects the voltage +DeltaV between the Kc end of the structure K5 and the Zc end of the structure Z5, one end of the R2 is connected on the circuit, and the other end is grounded.
Further, the activation module comprises a resistor, a Zi structure formed by two PMOS with G-pole interconnection, a Ki structure formed by two NMOS with G-pole interconnection, the structures Ki and Zi are respectively provided with four, the resistor is provided with five, vcc is the positive voltage of the power supply, vss is the negative voltage of the power supply, the Zb and the Zd ends of the structure Z4 are respectively connected with the Kb and the Kd ends of the structure K4 correspondingly, the current between the Zd end of the structure Z4 and the Kd end of the structure K4 is I+, the Za end of the structure Z4 is connected with Vcc after being connected with a series resistor R5, the Ka end of the structure K4 is connected with Vss after being connected with a series resistor R6, the Zc end of the structure Z4 is connected with the Ka end of the structure K3, the Kb and the Kc ends of the structure K3 are respectively connected with Vcc ends of the structure K3, the Zb and the Zd ends of the structure Z3 are respectively connected with Vss, the Za end resistor R7 of the Za end of the structure Z2 is connected with Vcc in series, the Ka end of the structure K2 is connected with the Vss after being connected with the resistor R8 in series, the Zb end of the structure Z2 is connected with the Kb end of the structure K2 together and then grounded, the controller collects the Zb end of the structure Z2 and the Kd end of the structure K2 together and then connects the Zc end of the structure Z3 in parallel, the current I-on the connecting line of the Kc end of the structure K3, the Za end of the structure Z2 is connected with the Vcc after being connected with the resistor R7, the Za end of the structure Z2 is connected with the Vss after being connected with the resistor R8, the Kb end of the structure Z2 and the Kd end of the structure K1 are connected with the Vcc end of the structure K1 together, the Zb end of the structure Z1 and the Zd end of the structure Z1 are connected with the Vss after being connected together, and the other end of the resistor R9 is grounded.
The control method applied to the intelligent early warning wearable heart rate monitoring circuit is characterized by comprising the following steps 1 to 4 to reduce the electric quantity loss of the wearable device during denoising:
step 1, comparing each waveform signal with a corresponding set threshold value, if any waveform signal is larger than the corresponding set threshold value, turning on the led lamp corresponding to the waveform signal, otherwise, turning to step 2;
step 2, all electric control switches Si are disconnected, and voltage Vi is collected to obtain voltage Vg, i=1, 2 and 3 … n;
step 3, sampling and holding the voltage Vg and outputting the voltage Vg as a voltage V0;
step 4, inputting the expected voltage V T 。
The beneficial effects are that:
the invention provides an intelligent early-warning wearable heart rate monitoring circuit, which is characterized in that a characteristic acquisition circuit is arranged to acquire human physiological electric signals and separate four waveform signals of P wave, R wave, T wave and U wave, the input end of the characteristic acquisition circuit extends out of four branches, each branch is connected with a transmission gate circuit, and the structure of any transmission gate circuit is as follows: the transmission gate circuit comprises a memristor, two CMOS transmission gates and two diodes, the G pole of a PMOS tube in the CMOS1 transmission gate is connected with the P pole of a diode J1, the N pole of the diode J1 is connected with the G pole of an NMOS tube in the CMOS1 transmission gate, the G pole of the NMOS tube in the CMOS2 transmission gate is connected with the P pole of a diode J2, the N pole of the diode J2 is connected with the G pole of the PMOS tube in the CMOS2 transmission gate, the input end of the CMOS1 transmission gate is used as the input end of the characteristic acquisition circuit, the output end of the CMOS1 transmission gate is connected with the input end of the memristor, the output end of the memristor is used as four waveform signals of P wave, R wave, T wave and U wave respectively, so that the operation quantity in the controller in the physiological electric signal characteristic extraction process is reduced, the loss of the wearable equipment is further reduced, and the duration of the wearable equipment is prolonged.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a schematic diagram of a feature acquisition circuit of the present invention;
FIG. 2 is a schematic diagram of a multi-layer learning circuit according to the present invention;
FIG. 3 is a schematic diagram of an error calculation circuit according to the present invention;
FIG. 4 is a schematic diagram of an activation module according to the present invention;
FIG. 5 is a schematic diagram of an electronic device according to the present invention;
fig. 6 is a schematic structural view of a computer readable storage medium of the present invention.
Reference numerals illustrate: 1-an activation module; 2-an error calculation circuit; 3-a sample holder; 4-a feedback adjustment module; a 21-processor; 22-memory; 23-storage space; 24-program code; 31-program code.
Detailed Description
The invention will be further described with reference to the following examples.
The intelligent early warning wearable heart rate monitoring circuit comprises a controller, a characteristic acquisition circuit, an alarm structure and a multi-layer learning circuit, wherein the input end of the characteristic acquisition circuit is connected with the output end of an external sensor, the external sensor is used for acquiring human physiological electric signals, the output end of the characteristic acquisition circuit is provided with four, the four output ends of the characteristic acquisition circuit are respectively connected with the four input ends of the multi-layer learning circuit and are used for transmitting four waveform signals separated by the characteristic acquisition circuit, the four output ends of the multi-layer learning circuit are respectively connected with four pins of the controller and are used for transmitting the four waveform signals after denoising by the multi-layer learning circuit to obtain four more accurate waveform signals, the controller compares the acquired four waveform signals with thresholds corresponding to all the waveform signals, if any one waveform signal exceeds the threshold, the alarm structure is a led lamp, the input pins of the led lamp corresponds to the output pins of the controller, and when any waveform signal exceeds the threshold, the controller lights the led lamp corresponding to the heart signal, and the controller is used for wearing a wearer.
Referring to fig. 1, the feature collection circuit includes an input end for receiving physiological electric signals, the input end extends out of four branches, each branch is connected with a transmission gate circuit, wherein the structure of any one transmission gate circuit is as follows: the high-voltage power supply circuit comprises a memristor, two CMOS transmission gates and two diodes, wherein the G pole of a PMOS tube in the CMOS1 transmission gate is connected with the P pole of a diode J1, the N pole of the diode J1 is connected with the G pole of an NMOS tube in the CMOS1 transmission gate, the G pole of an NMOS tube in the CMOS2 transmission gate is connected with the P pole of a diode J2, the N pole of the diode J2 is connected with the G pole of the PMOS tube in the CMOS2 transmission gate, the input end of the CMOS1 transmission gate is used as the input end of a characteristic acquisition circuit, the output end of the CMOS1 transmission gate is connected with the input end of the CMOS2 transmission gate, the output end of the memristor is used as the output end of the characteristic acquisition circuit, and the two ends of the memristor are respectively connected with a power supply to take small current so as to convert the resistance change of the memristor into a voltage value and output waveform signals.
According to the characteristic of the ECG signal, the ECG signal is input through the input end of the characteristic acquisition circuit, voltage VsetP, vsetR, vsetT, vsetU is firstly introduced into four branches to serve as threshold values of two CMOS transmission gates in each branch, in one ECG signal period, the physiological electric signal ECG signal is divided into P wave, R wave, T wave and U wave after passing through the characteristic acquisition circuit, wherein the P wave, R wave, T wave and U wave signals are extracted and obtained by VP, VR, VT and VU, MP, MR, MT and MU are memristors corresponding to the P wave, R wave, T wave and U wave, and VoP, voR, voT and VoU are the memristors and are converted into voltage output.
Because the change of the resistance of the memristor is in direct proportion to the magnetic flux flowing through two ends of the memristor, the change of the resistance of the memristor MP, MR, MT and MU can be recorded sequentially, for example, the larger the amplitude of the voltage is, the larger the change of the resistance of the memristor is, the wider the voltage width is, the larger the change of the resistance of the memristor is, and thus, the voltage waveform information can be recorded through each resistance state change of the memristor.
Referring to fig. 2, the multi-layer learning circuit comprises a first neural network layer and a second neural network layer, the first neural network layer comprises a feedback regulation module 4 and a feedforward calculation module, the second neural network layer comprises a sampling holder 3, an error calculation circuit 2, the feedback regulation module 4 and the feedforward calculation module, wherein the input end of the feedforward calculation module in the first neural network layer is connected with the output end of the feedback regulation module 4, the output end of the feedforward calculation module in the first neural network layer is connected with the input end of the feedforward calculation module in the second neural network layer, the output end of the feedforward calculation module in the second neural network layer is divided into two branches, one branch is connected with the input end of the second neural network layer adopting the holder 3, the other branch is connected with the input end of the amplifier after being connected with a resistor in series, the output end of the amplifier is connected with the input end of the controller so as to output voltage V0, the output end of the sampling holder 3 in the second neural network layer is connected with the input end of the error calculation circuit 2, the output end of the error calculation circuit 2 in the second neural network layer is connected with the input end of the feedback regulation module 4, the output end of the feedforward calculation module in the second neural network layer is divided into two branches, and the other branch is connected with the input end of the feedback regulation module in the second neural network layer.
The feedforward calculation module consists of a plurality of memristor synapse modules and an activation module 1, wherein any memristor synapse module consists of a memristor GI+ and a memristor GI-connected in series, the positive electrode of the memristor GI+ is connected with the negative electrode of the memristor GI-, voltage Vi is input from a connecting line of the positive electrode of the memristor GI+ and the memristor GI-, the negative electrode of the memristor GI+ is connected with the I+ end of the activation module 1, the positive electrode of the memristor GI+ is connected with the I-end of the activation module 1, the voltage Vi is the voltage Vi (i=1, 2 and 3 … K) converted from a biological function signal detected by a sensor for detecting a biological function signal, the activation module 1 plays a role of an amplifier, and the activation module 1 carries out operational amplification on currents input by I and I+ to obtain the voltage Vg.
The active module 1 shown in fig. 4 is composed of five resistors, four structures K and four structures Z, wherein the Zb and Zd ends of the structure Z4 are respectively connected with the Kb and Kd ends of the structure K4, the current between the Zd end of the structure Z4 and the Kd end of the structure K4 is i+, the Za end series resistor R5 of the structure Z4 is then connected with Vcc to obtain power, the Ka end series resistor R6 of the structure K4 is then connected with Vss, the Zc end of the structure Z4 is connected with the Ka end of the structure K3, the Kb and Kc ends of the structure K3 are respectively connected with Vcc, the Za and Zd ends of the structure Z3 are respectively connected with Vss, the Za end series resistor R7 of the structure Z2 is then connected with Vcc, the Ka end series resistor R8 of the structure K2 is then connected with Vss, the Kb end of the structure Z2 is then connected to the same node rear ground, the control structure Z2 is connected with the Ka end of the structure K2 to the same node, the Zc end of the structure Z2 is connected with the Zc end of the structure 1, the Zc end of the structure 2 is connected with the Zc end of the structure 2 in parallel, the Zc end of the structure 1 is connected with the Zc end of the structure 1, the Zc end of the structure is connected with the Zc end of the structure 2.
The activation module 1 is connected with the input end of the sampling holder 3, the output end of the sampling holder 3 is connected with the voltage input end of the error calculation circuit 2, and the sampling is adoptedThe voltage V0 is collected, the other pin of the controller is connected with the voltage expected input end of the error calculation circuit 2 to transmit the expected voltage V T Voltage V0 and desired voltage V T After the operation of the error calculation circuit 2, the voltage +DeltaV and-DeltaV are respectively output through two output ends of the error calculation circuit 2, the two output ends of the error calculation circuit 2 are respectively connected with a plurality of double mos tubes, any one double mos tube comprises a common G-pole Pmos tube and an Nmos tube, the D poles of the Pmos tube and the Nmos tube are respectively connected together and then collect the voltage Vi of any memristive synaptic module, the S pole of the Pmos tube is connected with the output end of the error calculation circuit 2, the output voltage of the Pmos tube is +DeltaV, an electric control switch Si is connected in series between the S pole of the Pmos tube and the output end of the error calculation circuit 2, the electric control switch Si is electrically connected with a controller, the S pole of the Nmos tube is also connected with the output end of the error calculation circuit 2 in series, and the electric control switch Si is electrically connected with the controller.
The feedback regulation module 4 is provided with a plurality of pairs of switch branches corresponding to the memristor synapse modules one by one, each pair of switch branches comprises a Pmos tube and an Nmos tube with a common G pole, and the D pole and the G pole of any pair of the Pmos tubes and the Nmos tube are connected together to form an output end of the corresponding switch branch, so as to output voltage Vpi after being filtered by the Pmos tube or the Nmos tube, and the voltage Vpi is on a line with an error of +DeltaV.
The sample holder 3 is a conventional sample holder 3 for holding a voltage. The sampling holder 3 comprises a voltage receiving end, a resistor R10, an electric control switch Fi, a capacitor C1 and a buffer amplifier A, one end of the resistor R10 is connected with the voltage receiving end, the other end of the resistor R10 is connected with the input end of the buffer amplifier A sharing the C electrode, the electric control switch Fi is arranged on a connecting line of the resistor R10 and the buffer amplifier A, one end of the capacitor C1 is arranged on a connecting line of the electric control switch Fi with the buffer amplifier A, the other end of the capacitor C1 is grounded, and the electric control switch Fi is electrically connected with the controller.
The following circuit has a plurality of structures Ki and Zi, where i=1, 2, 3 … … n. Each structure Ki comprises two NMOS tubes with G electrodes interconnected, wherein the D electrode and the G electrode of any one NMOS tube are connected to the same node to form a Ka end, the end point of the S electrode of the NMOS tube is taken as a Kb end, the end point of the D electrode of the other NMOS tube is taken as a Kc end, and the end point of the S electrode of the NMOS tube is taken as a Kd end. Each structure Zi comprises two PMOS tubes with G poles interconnected, wherein the D pole and the G pole of any one PMOS tube are connected to the same node to form a Za end, the endpoint of the S pole of the PMOS tube is taken as a Zb end, the endpoint of the D pole of the other PMOS tube is taken as a Zc end, and the endpoint of the S pole of the PMOS tube is taken as a Zd end.
Referring to fig. 3, the error calculation circuit 2 is respectively provided with four resistors, a Z structure and a K structure, a PMOS tube P1 and an NMOS tube N1 are sequentially connected in series between Vcc and Vss, the G pole and the D pole of the PMOS tube P1 are commonly connected at the same node and are connected with Vcc to power, the S pole of the PMOS tube P1 is connected with the D pole of the NMOS tube N1, a controller collects voltage-DeltaV on the connecting line, the S pole of the NMOS tube N1 is connected with Vss, the G pole of the NMOS tube N1 is suspended, a voltage measurement pin of the controller is connected on the connecting line of the Kb end of the structure K6 and the Zb end of the structure Z6, one end of the resistor R1 is connected on the connecting line of the Kd end of the structure K6 and the Zd end of the structure Z6, and the controller is connected with the other end of the resistor R1 to collect a desired voltage V T The Kc end of the structure K6 is connected with the Za end of the structure Z5, the Ka end of the structure K6 is connected with the Zb end and the Zd end of the structure Z5 after being connected to the same node, the Zc end of the structure Z6 is connected with the Ka end of the structure K5, the Za end of the structure Z6 is connected with the Vcc after being connected with the Kb end and the Kd end of the structure K5 after being connected to the same node, the Kc end of the structure K5 is connected with the Zc end of the structure Z5, the G electrode of the NMOS tube N1 is connected on the circuit, the controller collects the voltage +DeltaV between the Kc end of the structure K5 and the Zc end of the structure Z5, one end of the R2 is connected on the circuit, and the other end is grounded.
Based on the physiological electric signal filtering denoising circuit of the memristor, the steps 1-3 are executed to reduce the loss of electric quantity:
step 1, all Si is disconnected, and voltage Vi is acquired to obtain voltage Vg;
specifically, the controller controls the electric control switch Fi to be closed and the electric control switch Si to be opened, and the voltage Vi outputs memristive values I-and I+ respectively after passing through the memristive synaptic module and is transmitted to the activation module 1, and the activation module 1 obtains the voltage Vg after operation.
Step 2, sampling and holding voltage Vg to obtain voltage V0;
step 3, closing the electric control switch Si, opening the electric control switch Fi, collecting the voltage V0 and inputting the expected output voltage V T Calculating an error Δv between a desired output desired voltage VT and a voltage V0;
specifically, the controller controls the electric control switch Si to be closed or opened, and the error DeltaV before the expected voltage VT and the voltage V0 is obtained through the following algorithm:
ΔV＝a(V T -V 0 )
where a is a proportionality coefficient, a=r2/R1.
Step 4, collecting errors-delta V and delta V, inputting the errors-delta V and delta V into a feedback regulation module 4, and solving a programming voltage Vpi for regulating a memristive synaptic module;
specifically, the reverse voltage with error- Δv being +Δv is determined by the input and error together according to the LMS algorithm, and the weight adjustment amount for each training period. In the error calculation circuit 2, the program voltage Vpi is obtained from the errors +Δv, - Δv, and the voltage Vi in the error calculation circuit 2, and the algorithm is as follows:
Where sgn (Vi) is a sign function, i.e. if Vi >0, sgn (Vi) =1; if vi=0, sgn (Vi) =0; if Vi <0, sgn (Vi) = -1. According to the algorithm, each voltage Vpi can be calculated respectively, each calculated voltage Vpi is put into the error calculation circuit 2, the structure Zi or the structure Ki is controlled to be closed or opened, if the input voltage Vi is positive, the PMOS tube in the error calculation circuit 2 is closed and the NMOS tube is opened, and conversely, if the input voltage Vi is negative, the NMOS tube is closed and the PMOS tube is opened so as to ensure the conduction of a part of circuits in the error calculation circuit 2, and the synaptic weight between memristors GI and GI-is calibrated, so that the finally output voltage V0 is a value after denoising the voltage Vi.
S5, specifically comprising the following steps of A-E, adjusting the synaptic weight of the memristor GI+ and the memristor GI-within the time tp:
step A, voltage V pi Compared with the threshold voltage of the memristor, if the voltage V pi If the voltage is larger than or equal to the threshold voltage of the memristor, stopping the test, otherwise, jumping to the step B, wherein the threshold voltage of the memristor is a set value of the memristor and is a fixed value;
step B, collecting the voltage VPi and solving the error e between the voltage V0 and the expected voltage VT through the following algorithm: v (V) pi ＝e·sgn(V i )；
Step C, obtaining the expected voltage V according to the following algorithm T ：e＝a(V T -V 0 ) Where a is a proportionality coefficient, a=r2/R1;
step D, calculating the synaptic weight w between the memristors GI+ and GI-according to the following algorithm i And put into a memristive synaptic module for modulation:wherein w is i ＝G i+ -G i- 。
Specifically, see table 1 below:
| ΔV | Vi | Vpi | Gi+ | Gi- | wi | Voi |
| + | + | + | increase in size | Reduction of | Increase in size | Increase in size |
| + | - | - | Reduction of | Increase in size | Reduction of | Increase in size |
| - | + | - | Reduction of | Increase in size | Reduction of | Reduction of |
| - | - | + | Increase in size | Reduction of | Increase in size | Reduction of |
Wherein, the sign+ represents positive voltage, the sign-represents negative voltage, when DeltaV is positive, the voltage Vi and the voltage Vpi are both in the same direction, namely the voltage values of the voltage Vi and the voltage Vpi are both positive values or both negative values, at the moment, the output voltage Voi can be increased by adjusting memristive synaptic weight, and DeltaV is further reduced. Conversely, when Δv is negative, the voltages Vi and Vpi are reversed, i.e., the voltages Vi and Vpi are positive or negative, respectively, and at this time, adjusting the memristive synaptic weights can reduce the output voltage V0, so that the absolute value of Δv is also reduced. When Δv is below the memristive threshold voltage, the adjustment will stop.
In addition, before step S1, an activating step is further included, specifically including the following operation steps, to input an initial value V0 to the feedback adjustment module 4;
(1) In the case of R9 (i+ -I-) < Vss, v0=vss;
(2) V0=r9 (i+ -I-), with vss+.r9 (i+ -I-) +.ltoreq.vcc;
(3) In the case of R9 (i+ -I-) > Vcc, v0=vcc.
By the activation step, an initial value is input to the feedback adjustment module 4.
The beneficial effects of this embodiment are:
1. the structure of the sampling holder, the error calculation circuit, the feedback regulation module 4, the feedforward calculation module and the controller is controlled by the controller, the hardware structure is used for denoising the voltage Vi converted by the biological function signal, and the electric quantity consumed by the controller when the controller performs software denoising is reduced;
2. the error calculation circuit ensures accurate output of V0;
3. the activation module ensures that the method in this embodiment can operate.
It should be noted that:
the method according to the present embodiment can be implemented by being transferred to a program step and a device that can be stored in a computer storage medium, and being called and executed by a controller.
The algorithms and displays presented herein are not inherently related to any particular computer, virtual machine, or other apparatus for the purpose of disclosing the best mode of practicing the invention.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiments. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments.
Various component embodiments of the invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that some or all of the functions of some or all of the components in an apparatus for detecting the wearing state of an electronic device according to an embodiment of the present invention may be implemented in practice using a microprocessor or Digital Signal Processor (DSP). The present invention can also be implemented as an apparatus or device program (e.g., a computer program and a computer program product) for performing a portion or all of the methods described herein. Such a program embodying the present invention may be stored on a computer readable medium, or may have the form of one or more signals. Such signals may be downloaded from an internet website, provided on a carrier signal, or provided in any other form.
For example, fig. 5 shows a schematic structural diagram of an electronic device according to an embodiment of the present invention. The electronic device conventionally comprises a processor 21 and a memory 22 arranged to store computer executable instructions (program code). The memory 22 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. The memory 22 has a memory space 23 storing program code 24 for performing any of the method steps in the embodiments. For example, the memory space 23 for the program code may include individual program code 24 for implementing the various steps in the above method, respectively. The program code can be read from or written to one or more computer program products. These computer program products comprise a program code carrier such as a hard disk, a Compact Disc (CD), a memory card or a floppy disk. Such a computer program product is typically a computer readable storage medium as described for example in fig. 6. The computer readable storage medium may have memory segments, memory spaces, etc. arranged similarly to the memory 22 in the electronic device of fig. 5. The program code may be compressed, for example, in a suitable form. Typically, the memory unit stores program code 31 for performing the method steps according to the invention, i.e. program code readable by a processor such as 21, which when run by an electronic device causes the electronic device to perform the steps in the method described above.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.
Claims (2)
1. The intelligent early warning wearable heart rate monitoring circuit is characterized by comprising a controller, a characteristic acquisition circuit, an alarm structure and a multi-layer learning circuit, wherein the input end of the characteristic acquisition circuit is connected with the output end of an external sensor, the external sensor is used for acquiring human physiological electric signals, four branches are arranged in the characteristic acquisition circuit, the input end of each branch is connected with the input end of the characteristic acquisition circuit, a transmission gate circuit electrically connected with the controller is correspondingly arranged on each branch, the voltage setting threshold value of each transmission gate circuit is respectively voltage VsetP, voltage VsetR, voltage VsetT and voltage VsetU, each transmission gate circuit is respectively corresponding to and separated from P wave, R wave, T wave and U wave, the output end of the characteristic acquisition circuit is respectively connected with the four input ends of the multi-layer learning circuit, the four output ends of the multi-layer learning circuit are respectively connected with four pins of the controller and are used for transmitting P wave, R wave, T wave and U wave which are denoised by the multi-layer learning circuit, and the alarm structure is respectively connected with a plurality of LED lamps of controllers;
The structure of any one transmission gate circuit is as follows: the power supply comprises a memristor, two CMOS transmission gates and two diodes, wherein the G pole of a PMOS tube in the CMOS1 transmission gate is connected with the P pole of a diode J1, the N pole of the diode J1 is connected with the G pole of an NMOS tube in the CMOS1 transmission gate, the G pole of an NMOS tube in the CMOS2 transmission gate is connected with the P pole of a diode J2, the N pole of the diode J2 is connected with the G pole of the PMOS tube in the CMOS2 transmission gate, the input end of the CMOS1 transmission gate is used as the input end of a characteristic acquisition circuit, the output end of the CMOS1 transmission gate is connected with the input end of the memristor, the output end of the memristor is used as the output end of the characteristic acquisition circuit to output voltage VoP, voltage VoR, voltage VoT and voltage VoU which respectively correspond to four waveform signals of P wave, R wave, T wave and U wave, and the two ends of the memristor are respectively connected with a power supply to take current;
the multi-layer learning circuit comprises a first neural network layer and a second neural network layer, wherein the first neural network layer comprises a feedback regulation module and a feedforward calculation module, the second neural network layer comprises a sampling holder, an error calculation circuit, a feedback regulation module and a feedforward calculation module, the input end of the feedforward calculation module in the first neural network layer is connected with the output end of the feedback regulation module of the second neural network layer, the output end of the feedforward calculation module in the first neural network layer is connected with the input end of the feedforward calculation module in the second neural network layer, the output end of the feedforward calculation module in the second neural network layer is divided into two branches, one branch is connected with the input end of the second neural network layer by adopting the holder, the other branch is connected with the input end of the amplifier after being connected with a resistor in series, the output end of the amplifier is connected with the I/O end of the controller so as to output voltage V0, the output end of the sampling holder in the second neural network layer is connected with the input end of the error calculation circuit, the output end of the error calculation circuit in the second neural network layer is connected with the input end of the feedback regulation module, the output end of the feedback regulation module in the second neural network layer is divided into two branches, and the other branch is connected with the input end of the feedforward calculation module in the second neural network layer;
The second neural network layer comprises a sampling holder, an error calculation circuit, a feedback regulation module and a feedforward calculation module, wherein the feedforward calculation module consists of a plurality of memristive synapse modules and an activation module, each memristive synapse module is provided with an input end and two output ends for converting input voltage into two different currents, the input end of each memristive synapse module is respectively connected with each sensor for detecting biological function signals through an electric control switch Fi electrically connected with a controller to collect voltage Vi converted by the biological function signals, the activation module is provided with two input ends and one output end, the two input ends of the activation module are respectively connected with the two output ends of each memristive synapse module, and the activation module passes through an algorithm in a pure mode electricity modeThe voltage Vg, wi is the synaptic weight between the memristors GI+ and GI-, R is one grounding resistor in the activation module, the output end of the activation module is connected with the input end of the sampling holder to sample and hold the voltage Vg, and the output end of the sampling holder is connected with the I/O end of the controller to output the voltage V0; the error calculation circuit is provided with an input end, a voltage expected input end and two output ends, the input end of the error calculation circuit is connected to a connecting circuit of the sampling holder and the controller to collect voltage V0, one pin of the controller is connected to the voltage expected input end of the error calculation circuit to transmit expected voltage VT, the error calculation circuit obtains errors +DeltaV and-DeltaV in a pure analog power mode through an algorithm DeltaV=a (VT-V0), a is a proportionality coefficient, a=R2/R1 is respectively output through the two output ends of the error calculation circuit, a feedback regulation module is provided with a plurality of pairs of switch branches corresponding to a plurality of memristive synaptic modules one by one, each pair of switch branches comprises a Pmos tube and an Nmos tube with a common G pole, the D pole and the G pole of any pair of Pmos tubes are connected together to form the output end of the corresponding switch branch to output the voltage Vpi after being filtered by the Pmos tube or the Nmos tube, and the voltage Vi are on a circuit of the error +DeltaV The polarity of the Vpi is the same direction, on the line of error-delta V, the polarity of the voltage Vi and the polarity of the voltage Vpi are opposite, the output ends of each pair of switch branches are connected with the input ends of the corresponding memristive synaptic modules to transmit the voltage Vpi, an electric control switch Si electrically connected with a controller is connected in series on the connecting line, the S pole of each Pmos tube is connected with one output end of an error calculation circuit to receive +delta V, the S pole of each Nmos tube is connected with the other output end of the error calculation circuit to receive-delta V, the error calculation circuit, a feedback regulation module, a feedforward calculation module and the controller are respectively connected with a power supply to take electricity, and i=1, 2 and 3 … m;
each memristive synaptic module is provided with a memristor GI+ and a memristor GI-, wherein the memristor GI+ and the memristor GI-, the positive electrode of the memristor GI+ is connected with the negative electrode of the memristor GI-, and the voltage input end of the memristor synaptic module is connected with the connecting line of the positive electrode of the memristor GI+ and the memristor GI-, so as to transmit the detection value of the sensor;
the two input ends of the activation module are I-, I+ ends respectively, the negative electrode of the memristor GI+ is connected with the I+ end of the activation module, the positive electrode of the memristor GI-is connected with the I-end of the activation module, and the activation module carries out operational amplification on the current input by the I-, I+ to obtain voltage Vg and transmits the voltage Vg to the acquisition retainer;
The sampling holder comprises a voltage receiving end, a resistor R10, an electric control switch Fi, a capacitor C1 and a buffer amplifier A, wherein one end of the resistor R10 is connected with the voltage receiving end, the other end of the resistor R10 is connected with the input end of the buffer amplifier A sharing the C electrode, the electric control switch Fi is arranged on a connecting line of the resistor R10 and the buffer amplifier A, one end of the capacitor C1 is arranged on a connecting line of the electric control switch Fi with the buffer amplifier A, the other end of the capacitor C1 is grounded, and the electric control switch Fi is electrically connected with the controller;
the error calculation circuit comprises a resistor, a Zi structure formed by two PMOS with G electrode interconnection, and a Ki structure formed by two NMOS with G electrode interconnection, wherein the resistor, the Zi structure and the Ki structure are respectively provided with four, vcc is the positive voltage of a power supply, vss is the negative voltage of the power supply, a PMOS tube P1 and an NMOS tube N1 are sequentially connected in series between Vcc and Vss, the G electrode and the D electrode of the PMOS tube P1 are connected together in a common way and then are connected with Vcc to be powered on, and the S electrode of the PMOS tube P1The voltage-DeltaV on the connecting line is collected by a controller, the S electrode of the NMOS tube N1 is connected with Vss, the G electrode of the NMOS tube N1 is suspended, a voltage measuring pin of the controller is connected on the connecting line of the Kb end of the structure K6 and the Zb end of the structure Z6, one end of the resistor R1 is connected on the connecting line of the Kd end of the structure K6 and the Zd end of the structure Z6, and the other end of the controller and the resistor R1 are connected to collect the expected voltage V T The Kc end of the structure K6 is connected with the Za end of the structure Z5, the Ka end of the structure K6 is connected with the Zb end and the Zd end of the structure Z5 together after being connected with a resistor R4 in series, the Zc end of the structure Z6 is connected with the Ka end of the structure K5, the Za end of the structure Z6 is connected with the Vcc after being connected with the Kb end and the Kd end of the structure K5 together after being connected with a resistor R3 in series, the Kc end of the structure K5 is connected with the Zc end of the structure Z5, the G electrode of the NMOS tube N1 is connected on the circuit, a controller collects voltage +DeltaV between the Kc end of the structure K5 and the Zc end of the structure Z5, one end of the R2 is connected on the circuit, and the other end is grounded;
each structure Ki comprises two NMOS tubes with G electrodes connected with each other, wherein the D electrode and the G electrode of any one NMOS tube are connected to the same node to form a Ka end, the end point of the S electrode of the NMOS tube is taken as a Kb end, the end point of the D electrode of the other NMOS tube is taken as a Kc end, and the end point of the S electrode of the NMOS tube is taken as a Kd;
each structure Zi comprises two PMOS tubes with G electrodes connected with each other, wherein the D electrode and the G electrode of any one PMOS tube are connected to the same node to form a Za end, the endpoint of the S electrode of the PMOS tube is taken as a Zb end, the endpoint of the D electrode of the other PMOS tube is taken as a Zc end, and the endpoint of the S electrode of the PMOS tube is taken as a Zd end;
the activation module comprises a resistor, a Zi structure formed by two PMOS interconnected with G electrode, a Ki structure formed by two NMOS interconnected with G electrode, the structures Ki and Zi are respectively provided with four, the resistor is provided with five, vcc is the positive voltage of the power supply, vss is the negative voltage of the power supply, the Zb and the Zd ends of the structure Z4 are respectively connected with the Kb and the Kd ends of the structure K3 correspondingly, the current between the Zd end of the structure Z4 and the Kd end of the structure K3 is I+, the Za end of the structure Z4 is connected with Vcc after being connected with a resistor R5 to be electrified, the Ka end of the structure K3 is connected with Vss after being connected with a resistor R6, the Zc end of the structure Z4 is connected with the Ka end of the structure K4, the Kb and the Kd ends of the structure K4 are respectively connected with Vcc, the Zb and the Zd ends of the structure Z3 are respectively connected with Vss, the Za end series resistor R7 of the structure Z1 is connected with Vcc after the Ka end series resistor R8 of the structure K2 is connected with Vss, the Zb end of the structure Z1 is connected with the Kb end of the structure K2 together and then grounded, the controller collects current I-connected in parallel on the connecting lines of the Zc end of the structure Z3 and the Kc end of the structure K4 after the Zd end of the structure Z1 is connected with the Kc end of the structure K1, the Ka end series resistor R8 of the structure K2 is connected with Vss after the Zc end of the structure Z2 is connected with the Kc end of the structure K1, the Kb end and the Kd end of the structure K1 are connected with Vcc after the Kc end of the structure K2 is connected with the Za end of the structure Z2 together, the Zb end and the Zd end of the structure Z2 are connected with Vss after the Kc end of the structure K1 is connected with the Zc end of the structure Z2 together, and the other end of the resistor R9 is grounded.
2. The control method applied to the intelligent early warning wearable heart rate monitoring circuit of claim 1 is characterized in that the following steps 1 to 4 are operated to reduce the electric quantity loss of the wearable device during denoising:
step 1, comparing each waveform signal with a voltage set threshold corresponding to the waveform signal, if any waveform signal is larger than the set threshold corresponding to the waveform signal, turning on the led lamp corresponding to the waveform signal, otherwise, turning to step 2;
step 2, all electric control switches Si are disconnected, and voltage Vi is collected to obtain voltage Vg, i=1, 2 and 3 … n;
step 3, sampling and holding the voltage Vg and outputting the voltage Vg as a voltage V0;
step 4, inputting the expected voltage V T 。
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