CN112994689A - Loop tuning voltage preset clamping circuit for phase-locked loop circuit - Google Patents
Loop tuning voltage preset clamping circuit for phase-locked loop circuit Download PDFInfo
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- CN112994689A CN112994689A CN202110237964.8A CN202110237964A CN112994689A CN 112994689 A CN112994689 A CN 112994689A CN 202110237964 A CN202110237964 A CN 202110237964A CN 112994689 A CN112994689 A CN 112994689A
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- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 13
- 238000013461 design Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- 230000001419 dependent effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Abstract
The invention discloses a loop tuning voltage preset clamping circuit for a phase-locked loop circuit, which comprises a reference voltage generation module, a first comparator, a second comparator, a first diode and a second diode, wherein the output end of the first comparator is connected with the cathode of the first diode, the output end of the second comparator is connected with the anode of the second diode, and one input end of the first comparator, one input end of the second comparator, the anode of the first diode and the cathode of the second diode are connected with loop tuning voltage; the reference voltage generation module generates a higher first reference voltage and a lower second reference voltage according to the control signal; the first comparator outputs a low level when the loop tuning voltage is higher than the first reference voltage, otherwise outputs a high level; the second comparator outputs a high level when the loop tuning voltage is lower than the second reference voltage, and otherwise outputs a low level. The invention can clamp the tuning voltage of the loop in advance, prevent the phase-locked loop from being locked wrongly and improve the locking speed of the loop.
Description
Technical Field
The invention relates to the technical field of phase-locked loops, in particular to a loop tuning voltage preset clamping circuit for a phase-locked loop circuit.
Background
The phase-locked loop technology is one of the core units in the current communication system, radar system, electronic warfare system and measurement system. With the development of technology, higher requirements are put on power consumption, size, performance and the like of the VCO, and especially in a large number of application scenarios sensitive to power consumption, the VCO (voltage controlled oscillator) is used in a large number as a frequency device with lower power than the YTO (current mode tuned oscillator).
However, the VCO as a voltage control device has characteristics dependent on a voltage control varactor, and when the control voltage tends to the extreme of its tuning curve, the tuning sensitivity Kv linearity and the oscillation characteristics become poor, and in such extreme cases, an unrecoverable phenomenon such as a loop losing lock or a stop of oscillation easily occurs. Meanwhile, especially for some broadband VCOs, the low end of a tuning curve is particularly close to the ground potential, and the traditional design usually adopts a positive and negative double-supply design in order to ensure that a loop can effectively lock the low-end frequency, but the design is extremely easy to generate output low voltage when the wide-range frequency switching is carried out, so that the VCO stops oscillation or the loop loses the lock.
For multi-loop design, particularly, the high-performance offset loop often adopts sampling phase discrimination, harmonic mixing or shock line and other technologies to directly acquire intermediate frequency for phase discrimination, and in the process, due to limited intervals among intermediate frequency signals, certain active tuning needs to be applied to the loop to ensure correct locking. The traditional tuning circuit has the disadvantages of complex tuning code generation, difficult calibration, temperature drift, phase noise deterioration and multiple increase of application cost.
Disclosure of Invention
The invention mainly solves the technical problem of providing a loop tuning voltage preset clamping circuit for a phase-locked loop circuit, which can carry out preset clamping on the loop tuning voltage, prevent the phase-locked loop from being locked wrongly and improve the loop locking speed.
In order to solve the technical problems, the invention adopts a technical scheme that: the loop tuning voltage preset clamping circuit for the phase-locked loop circuit comprises a reference voltage generation module, a first comparator, a second comparator, a first diode and a second diode, wherein the output end of the first comparator is connected with the cathode of the first diode, the output end of the second comparator is connected with the anode of the second diode, and one input end of the first comparator, one input end of the second comparator, the anode of the first diode and the cathode of the second diode are used for being connected with loop tuning voltage;
the reference voltage generation module is used for receiving a control signal, generating a first reference voltage and a second reference voltage according to the control signal, inputting the first reference voltage to the other input end of the first comparator, and inputting the second reference voltage to the other input end of the second comparator, wherein the first reference voltage is higher than the second reference voltage;
the first comparator is used for outputting a low level when the loop tuning voltage is higher than a first reference voltage, and outputting a high level when the loop tuning voltage is lower than the first reference voltage;
the second comparator is used for outputting a high level when the loop tuning voltage is lower than the second reference voltage, and outputting a low level when the loop tuning voltage is higher than the second reference voltage.
Preferably, the inverting input terminal of the first comparator and the inverting input terminal of the second comparator are used for connecting a loop tuning voltage; the reference voltage generation module inputs the first reference voltage to a non-inverting input terminal of a first comparator, and inputs a second reference voltage to a non-inverting input terminal of a second comparator.
Preferably, the reference voltage generating module is a digital-to-analog conversion circuit, and the control signal is a serial signal or a parallel signal.
Different from the prior art, the invention has the beneficial effects that: the loop tuning voltage is dynamically limited between the first reference voltage and the second reference voltage by setting the first reference voltage and the second reference voltage through the two comparators, so that the loop tuning voltage can be clamped, the phase-locked loop is prevented from being locked wrongly and wrongly, the loop locking speed can be improved, the phenomenon that the VCO stops vibrating or the loop is unlocked when the integrator enters the limit of a power supply rail or the VCO enters a limit nonlinear area and the like to influence the locking condition is avoided, meanwhile, the output range of the loop integrator is limited by presetting the voltage interval formed by the first reference voltage and the second reference voltage so as to effectively reduce the locking time of the phase-locked loop, and the loop is locked quickly.
Drawings
Fig. 1 is a schematic diagram of a loop tuning voltage preset clamp circuit for a phase locked loop circuit according to an embodiment of the present invention.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic diagram of a loop tuning voltage preset clamp circuit for a phase-locked loop circuit according to an embodiment of the present invention. The loop tuning voltage preset clamp circuit comprises a reference voltage generation module 1, a first comparator A, a second comparator B, a first diode D1 and a second diode D2. The output end of the first comparator A is connected with the cathode of a first diode D1, the output end of the second comparator B is connected with the anode of a second diode D2, and one input end of the first comparator A, one input end of the second comparator B, the anode of a first diode D1 and the cathode of a second diode D2 are used for connecting a loop tuning voltage.
The reference voltage generating module 1 is configured to receive a control signal, generate a first reference voltage and a second reference voltage according to the control signal, input the first reference voltage to another input terminal of the first comparator a, and input the second reference voltage to another input terminal of the second comparator B, where the first reference voltage is higher than the second reference voltage.
The first comparator A is used for outputting a low level when the loop tuning voltage is higher than the first reference voltage, and outputting a high level when the loop tuning voltage is lower than the first reference voltage.
The second comparator B is configured to output a high level when the loop tuning voltage is lower than the second reference voltage, and output a low level when the loop tuning voltage is higher than the second reference voltage.
The working process of the loop tuning voltage preset clamp circuit of the embodiment is as follows:
a loop tuning voltage and a first reference voltage are respectively input to two input ends of the first comparator A, if the loop tuning voltage is higher than the first reference voltage, an output end of the first comparator A outputs a low level, at the moment, the first diode D1 is conducted, and the loop tuning voltage is conducted to the output end of the first comparator A through the first diode D1; at this time, the second comparator B outputs a low level, and the second diode D2 is turned off and does not participate in the clamping process. Since the first comparator a outputs a low level, the loop tuning voltage follows to a low level. When the loop tuning voltage changes to a low level, the loop tuning voltage is lower than the first reference voltage, the output of the first comparator a is inverted to a high level, the first diode D1 is turned off, the loop tuning voltage changes to a high level along with the integrator again, and the first diode D1 is turned on again. Thus, during the on-off-on process of the first diode D1, the loop tuning voltage is dynamically limited to about the first reference voltage, thereby ensuring that the loop tuning voltage does not follow the integrator to rise to the limit power rail or the VCO limit non-linear region to cause the loop to lose lock.
A loop tuning voltage and a second reference voltage are respectively input to two input ends of the second comparator B, if the loop tuning voltage is lower than the second reference voltage, an output end of the second comparator B outputs a high level, at this time, the second diode D2 is turned on, and the loop tuning voltage is turned on to the output end of the second comparator B by the second diode D2; at this time, the first comparator a outputs a high level, and the first diode D1 is turned off and does not participate in the clamping process. Since the second comparator B outputs a high level, the loop tuning voltage follows to become a high level. When the loop tuning voltage changes to the high level, it is higher than the second reference voltage, the output of the second comparator B is turned to the low level again, at this time, the second diode D2 is turned off, the loop tuning voltage changes to the low level again along with the integrator, and the second diode D2 is turned on again. Therefore, in the process of conducting-cutting-conducting of the second diode D2, the loop tuning voltage can be dynamically limited to be about the second reference voltage, so that the loop tuning voltage is ensured not to fall to the limit power supply rail or the VCO limit non-linear area along with the integrator to cause the loop to lose lock.
If the loop tuning voltage is lower than the first reference voltage and higher than the second reference voltage, the first comparator a outputs a high level and the second comparator B outputs a low level, so that the first diode D1 and the second diode D2 are both in a cut-off state, and the loop tuning voltage is not affected.
In this embodiment, the input end of the first comparator a and the input end of the second comparator B, which are connected with the loop tuning voltage, are inverted input ends; the reference voltage generation module 1 inputs a first reference voltage to a non-inverting input terminal of the first comparator a, and inputs a second reference voltage to a non-inverting input terminal of the second comparator B. The reference voltage generating module 1 may be a digital-to-analog conversion circuit, and the control signal is a serial signal or a parallel signal. In specific implementation, the first reference voltage and the second reference voltage can be changed by changing the control signal, so that a proper voltage range (namely, the second reference voltage to the first reference voltage) is obtained, the loop tuning voltage is preset and clamped in the voltage range, and the phase-locked loop circuit can be quickly and accurately locked to the set frequency without error locking and mislocking.
Through the mode, the loop tuning voltage preset clamping circuit for the phase-locked loop circuit provided by the embodiment of the invention can be used for dynamically limiting the loop tuning voltage between the first reference voltage and the second reference voltage by setting the first reference voltage and the second reference voltage and utilizing the two comparators and the two diodes, so that the loop tuning voltage can be preset clamped, the phase-locked loop is prevented from being locked wrongly and wrongly, the loop locking speed can be improved, the VCO is prevented from being stopped or locked or the loop is not locked when the integrator enters the limit of a power supply rail or the VCO enters a limit nonlinear area and the like to influence locking, meanwhile, the output range of the integrator is limited by presetting the voltage interval formed by the first reference voltage and the second reference voltage, and the loop locking speed can be effectively improved.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (3)
1. A loop tuning voltage preset clamping circuit for a phase-locked loop circuit is characterized by comprising a reference voltage generation module, a first comparator, a second comparator, a first diode and a second diode, wherein the output end of the first comparator is connected with the cathode of the first diode, the output end of the second comparator is connected with the anode of the second diode, and one input end of the first comparator, one input end of the second comparator, the anode of the first diode and the cathode of the second diode are used for being connected with a loop tuning voltage;
the reference voltage generation module is used for receiving a control signal, generating a first reference voltage and a second reference voltage according to the control signal, inputting the first reference voltage to the other input end of the first comparator, and inputting the second reference voltage to the other input end of the second comparator, wherein the first reference voltage is higher than the second reference voltage;
the first comparator is used for outputting a low level when the loop tuning voltage is higher than a first reference voltage, and outputting a high level when the loop tuning voltage is lower than the first reference voltage;
the second comparator is used for outputting a high level when the loop tuning voltage is lower than the second reference voltage, and outputting a low level when the loop tuning voltage is higher than the second reference voltage.
2. The loop tuning voltage preset clamp circuit for the phase-locked loop circuit according to claim 1, wherein the inverting input terminal of the first comparator and the inverting input terminal of the second comparator are used for connecting the loop tuning voltage; the reference voltage generation module inputs the first reference voltage to a non-inverting input terminal of a first comparator, and inputs a second reference voltage to a non-inverting input terminal of a second comparator.
3. The loop tuning voltage preset clamp circuit for a phase-locked loop circuit of claim 1, wherein the reference voltage generating module is a digital-to-analog conversion circuit, and the control signal is a serial signal or a parallel signal.
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102522985A (en) * | 2011-12-31 | 2012-06-27 | 杭州士兰微电子股份有限公司 | Locking-phase ring and voltage-controlled oscillator thereof |
CN102812640A (en) * | 2010-03-17 | 2012-12-05 | 德州仪器公司 | Phase Locked Loop (PLL) With Analog And Digital Feedback Controls |
CN103368563A (en) * | 2012-03-30 | 2013-10-23 | 安凯(广州)微电子技术有限公司 | Device and method for tuning frequency of phase-locked loop |
CN205664933U (en) * | 2016-06-07 | 2016-10-26 | 哈尔滨国力电气有限公司 | Be applicable to IEPE type vibrational acceleration sensor operating condition indicating circuit |
CN110048367A (en) * | 2019-03-14 | 2019-07-23 | 西安联飞智能装备研究院有限责任公司 | A kind of overvoltage crowbar and rear end receiving device based on operational amplifier |
-
2021
- 2021-03-04 CN CN202110237964.8A patent/CN112994689A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102812640A (en) * | 2010-03-17 | 2012-12-05 | 德州仪器公司 | Phase Locked Loop (PLL) With Analog And Digital Feedback Controls |
CN102522985A (en) * | 2011-12-31 | 2012-06-27 | 杭州士兰微电子股份有限公司 | Locking-phase ring and voltage-controlled oscillator thereof |
CN103368563A (en) * | 2012-03-30 | 2013-10-23 | 安凯(广州)微电子技术有限公司 | Device and method for tuning frequency of phase-locked loop |
CN205664933U (en) * | 2016-06-07 | 2016-10-26 | 哈尔滨国力电气有限公司 | Be applicable to IEPE type vibrational acceleration sensor operating condition indicating circuit |
CN110048367A (en) * | 2019-03-14 | 2019-07-23 | 西安联飞智能装备研究院有限责任公司 | A kind of overvoltage crowbar and rear end receiving device based on operational amplifier |
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