CN112992961A

CN112992961A - Telescopic display device

Info

Publication number: CN112992961A
Application number: CN202011418503.2A
Authority: CN
Inventors: S·金; 郑贤主
Original assignee: LG Display Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2019-12-12
Filing date: 2020-12-07
Publication date: 2021-06-18
Anticipated expiration: 2040-12-07
Also published as: KR20210074627A; US20210183962A1; US11751459B2; CN112992961B

Abstract

A retractable display device. According to an aspect of the present disclosure, a scalable display device includes: a lower substrate on which a display region displaying an image and a non-display region adjacent to the display region are disposed; a plurality of pixel substrates disposed in the display region; a plurality of outer substrates disposed in the non-display region; a plurality of pixels disposed on the plurality of pixel substrates; and a plurality of gate drivers disposed on the plurality of outer substrates and outputting gate voltages to the plurality of pixels; and at least one blocking layer overlapping the plurality of gate drivers. Therefore, it is possible to prevent the occurrence of image defects in the retractable display device due to external static electricity.

Description

Telescopic display device

Cross Reference to Related Applications

This application claims priority rights to korean patent application No. 10-2019-0165499 filed in the korean intellectual property office at 12.12.2019, the disclosure of which is incorporated herein by reference.

Technical Field

The present disclosure relates to a retractable display device, and more particularly, to a retractable display device capable of preventing damage caused by static electricity.

Background

Display devices for computer monitors, TVs, mobile phones, etc. include Organic Light Emitting Displays (OLEDs) that emit light by themselves, Liquid Crystal Displays (LCDs) that require a separate light source, etc.

Such display devices are being applied to more and more various fields including not only computer monitors and TVs but also personal mobile devices, and thus, display devices having a reduced volume and weight while having a wide display area are being researched.

Recently, a retractable display device manufactured to be retractable in a specific direction and changeable into various shapes by forming a display unit, a wire, or the like on a flexible substrate such as plastic as a flexible material has received considerable attention as a next-generation display device.

Disclosure of Invention

An object to be achieved by the present disclosure is to provide a scalable display device including a gate driver capable of outputting a gate voltage when the scalable display device is scaled.

Another object to be achieved by the present disclosure is to provide a retractable display device capable of protecting internal elements from static electricity.

The object of the present disclosure is not limited to the above-mentioned object, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present disclosure, a scalable display device includes: a lower substrate on which a display region displaying an image and a non-display region adjacent to the display region are disposed; a plurality of pixel substrates disposed in the display region; a plurality of outer substrates disposed in the non-display region; a plurality of pixels disposed on the plurality of pixel substrates; and a plurality of gate drivers disposed on the plurality of outer substrates and outputting gate voltages to the plurality of pixels; and at least one blocking layer overlapping the plurality of gate drivers. Therefore, it is possible to prevent the occurrence of image defects in the retractable display device due to external static electricity.

According to another aspect of the present disclosure, a scalable display device includes: a stretchable substrate on which a display area displaying an image and a non-display area adjacent to the display area are provided; a plurality of first rigid substrates disposed in the display area; a plurality of second rigid substrates disposed in the non-display area; a plurality of pixels disposed on the plurality of first rigid substrates; a plurality of gate drivers disposed on the plurality of second rigid substrates and including at least one gate transistor; and at least one blocking layer disposed above and below the at least one gate transistor to prevent introduction of external static electricity. Therefore, it is possible to prevent the gate driver of the scalable display device from being damaged by external static electricity.

Other details of the exemplary embodiments are included in the detailed description and the accompanying drawings.

According to the present disclosure, a scalable gate driver and a power supply unit can be provided to thereby drive pixels of a scalable display device.

According to the present disclosure, it is possible to reduce the size of a bezel area by overlapping the power supply unit and the gate driver.

According to the present disclosure, it is possible to prevent the gate driver from being damaged due to external static electricity by overlapping a blocking layer with the gate driver.

According to the present disclosure, it is possible to effectively discharge static electricity by electrically connecting the barrier layer to a pixel connection line supplying a constant voltage.

The effects according to the present disclosure are not limited to the above-exemplified ones, and more various effects are included in the present specification.

Drawings

The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic plan view of a retractable display apparatus according to an exemplary embodiment of the present disclosure;

FIG. 2 is an enlarged plan view of region X illustrated in FIG. 1;

FIG. 3 is a sectional view taken along line III-III' of FIG. 2;

fig. 4 is a block diagram for illustrating driving of a gate driver according to an exemplary embodiment of the present disclosure;

fig. 5A and 5B are enlarged plan views of the region Y illustrated in fig. 1;

FIG. 6 is a sectional view taken along line VI-VI' of FIG. 5A;

fig. 7 is an enlarged plan view of a non-display area of a scalable display device according to another exemplary embodiment of the present disclosure;

FIG. 8 is a cross-sectional view taken along line VIII-VIII' of FIG. 7;

FIG. 9 is a sectional view taken along line IX-IX' of FIG. 7;

fig. 10 is a cross-sectional view of a non-display area of a retractable display apparatus according to still another exemplary embodiment of the present disclosure; and

fig. 11 is a graph illustrating a relationship between a gate voltage and a drain current of a gate transistor of a scalable display device according to another embodiment of the present disclosure.

Detailed Description

Advantages and features of the present disclosure and methods of accomplishing the same will become apparent by reference to the exemplary embodiments and the accompanying drawings, which are described in detail below. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be embodied in various forms. The exemplary embodiments are provided only as examples so that those skilled in the art can sufficiently understand the disclosure of the present disclosure and the scope of the present disclosure. Accordingly, the disclosure is to be limited only by the scope of the following claims.

Shapes, sizes, ratios, angles, numbers, and the like, which are used to describe exemplary embodiments of the present disclosure, are illustrated in the drawings only as examples, and the present disclosure is not limited thereto. Like reference numerals generally refer to like elements throughout the specification. Furthermore, in the following description of the present disclosure, detailed descriptions of known related art may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including," having, "and" consisting of …, "as used herein, are generally intended to allow for the addition of other components, unless these terms are used with the term" only. Any reference to the singular may include the plural unless explicitly stated otherwise.

Even if not explicitly stated, the components are to be interpreted as including a common error range.

When terms such as "on …," "above …," "below …," and "next to" are used to describe a positional relationship between two parts, one or more parts may be positioned between two parts unless these terms are used with the terms "immediately" or "directly".

When an element or layer is referred to as being "on" another element or layer, it can be directly on or between the other element or layer.

Although the terms "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, in the technical idea of the present disclosure, the first component to be mentioned below may be the second component.

Like reference numerals generally refer to like elements throughout the specification.

The size and thickness of each component illustrated in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the illustrated components.

The features of the various embodiments of the present disclosure can be partially or fully adhered to or combined with each other and can be interlocked and operated in a technically different manner, and the embodiments can be performed independently or in association with each other.

Hereinafter, a retractable display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

< retractable display device >

A scalable display device may refer to a display device capable of displaying an image even if it is bent or scaled. The retractable display device may have higher flexibility than a typical display device. Therefore, the shape of the retractable display device can be freely deformed by manipulation of the user, such as bending or extension of the retractable display device. For example, when a user grasps one end of the retractable display device and pulls the retractable display device, the retractable display device can be retracted by the force of the user. If a user places the retractable display device on an uneven wall surface, the retractable display device can be curved according to the shape of the wall surface. When the force applied by the user is removed, the retractable display device can return to its original shape, or maintain its deformed shape. In addition, the shape of the stretchable display device may be bent, stretched, or extended to the extent that the stretchable display device and its various components retain their original features and functions or reach a threshold value. When the force applied by the user exceeds this threshold, the display device may break and may not return to its original or contracted shape. Furthermore, the retractable display device does not perform its original features and functions when it finally breaks.

Fig. 1 is a schematic plan view of a scalable display device according to an exemplary embodiment of the present disclosure.

Referring to fig. 1, the scalable display device 100 includes a lower substrate 110a, a plurality of pixel substrates 111, a plurality of outer substrates 121, a plurality of connection supports 120, a COF (chip on film) 130, and a printed circuit board 140.

The lower substrate 110a serves to protect and support various components of the retractable display device 100. The lower substrate 110a is a flexible substrate and may be formed of a bendable or stretchable insulating material. For example, the lower substrate 110a may be formed of silicon rubber such as Polydimethylsiloxane (PDMS) and elastomer such as Polyurethane (PU), Polytetrafluoroethylene (PTFE), and the like. Accordingly, the lower substrate 110a may have flexibility. However, the material of the lower substrate 110a is not limited thereto.

The lower substrate 110 is a flexible substrate so as to reversibly expand and contract. In addition, the elastic modulus of the lower substrate 110 may be several MPa to several hundred MPa, for example, 0.7MPa to 1 MPa. In addition, the ductile fracture rate of the lower substrate 110 may be 100% or more. Here, the ductile fracture ratio refers to an extension distance at which the object to be stretched is fractured or cracked. That is, the ductile fracture ratio is defined as the percentage of the length of the original object to the length of the stretched object when the object is sufficiently stretched such that it is considered to be fractured. For example, if the length of the object (e.g., the lower substrate 110) is 100cm when the object is not stretched, and reaches 110cm when the object has been stretched enough to crack or break it, it is stretched to 110% of its original length. In this case, the ductile fracture ratio of the object is 110%. This number can therefore also be referred to as ductile fracture ratio, since it is the ratio of the tensile length as a numerator to the denominator of the original length as a denominator at which a fracture occurs.

When the object can no longer work properly in the structure or circuit, the object is considered damaged. For example, a line of conductor is considered to be broken when the ability of the line to carry current is sufficiently reduced to fail to operate within the circuit specification. Thus, in some embodiments, it may not be necessary to completely break the wire to make it deemed broken, and a minor stress at the connection end, minor crack, slight shift in the position of the wire, or other movement that causes it to no longer function within the desired function will be deemed broken. An insulator is considered damaged if it is stretched sufficiently that it no longer provides the amount of insulation needed for the structure or circuit. In some embodiments, breaking will also include inelastic stretching, wherein the object has been stretched sufficiently so that it does not return to its original length and/or shape when no longer stretched.

The thickness of the lower substrate 110a may be 10 μm to 1mm, but is not limited thereto.

Meanwhile, the lower substrate 110a may include a display area AA and a non-display area NA surrounding the display area AA.

The display area AA refers to an area where an image is displayed in the scalable display device 100. In the display area AA, a light emitting element and various driving elements for driving the light emitting element are provided. The display area AA includes a plurality of pixels, each of which includes a plurality of sub-pixels. A plurality of pixels are disposed in the display area AA and include a plurality of light emitting devices. Each of the plurality of sub-pixels may be connected to a respective line. For example, each of the plurality of sub-pixels may be connected to a respective line such as a gate line, a data line, a high-potential pixel driving voltage line, a low-potential pixel driving voltage line, a reference voltage line, and the like.

The non-display area NA refers to an area adjacent to the display area AA. The non-display area NA is adjacent to and surrounds the display area AA. In the non-display area NA, an image is not displayed, and lines and circuits may be provided. For example, a plurality of pads may be disposed in the non-display area NA, and each pad may be connected to each of a plurality of sub-pixels disposed in the display area AA.

On the lower substrate 110a, a plurality of pixel substrates 111 and a plurality of outer substrates 121 are disposed. A plurality of pixel substrates 111 may be disposed in the display area AA of the lower substrate 110a, and a plurality of outer substrates 121 may be disposed in the non-display area NA of the lower substrate 110 a. Fig. 1 illustrates that a plurality of external substrates 121 in the non-display area NA are disposed at upper and lower sides and left sides of the display area AA. However, the present disclosure is not limited thereto. The plurality of external substrates 121 may be disposed in any region of the non-display region NA.

The plurality of pixel substrates 111 and the plurality of outer substrates 121 are rigid substrates and are independently disposed to be spaced apart from each other on the lower substrate 110 a. That is, the pixel substrate 111 may be referred to as a first rigid substrate, and the outer substrate 121 may be referred to as a second rigid substrate. The plurality of pixel substrates 111 and the plurality of outer substrates 121 may be more rigid than the lower substrate 110 a. That is, the lower substrate 110a may be more ductile than the plurality of pixel substrates 111 and the plurality of outer substrates 121, and the plurality of pixel substrates 111 and the plurality of outer substrates 121 may be more rigid than the lower substrate 110 a.

Each of the plurality of pixel substrates 111 and the plurality of outer substrates 121, which are a plurality of rigid substrates, may be formed of a plastic material having flexibility. The plurality of pixel substrates 111 and the plurality of outer substrates 121 may be formed of, for example, Polyimide (PI), polyacrylate, polyacetate, etc., but are not limited thereto. The plurality of pixel substrates 111 and the plurality of outer substrates 121 may be formed of a material different from the above-described material. In this case, the plurality of pixel substrates 111 may be formed of the same material as the plurality of outer substrates 121, but is not limited thereto. The pixel substrate 111 may be formed of a different material from the plurality of outer substrates 121.

The plurality of pixel substrates 111 and the plurality of outer substrates 121 may have a modulus higher than that of the lower substrate 110 a. Here, the modulus refers to an elastic modulus showing a ratio of deformation of the substrate to stress applied to the substrate, and when the modulus is relatively high, the hardness may be relatively high. Accordingly, the plurality of pixel substrates 111 and the plurality of outer substrates 121 may be a plurality of rigid substrates having higher rigidity than the lower substrate 110 a. The modulus of the plurality of pixel substrates 111 and the plurality of outer substrates 121 may be 1000 times or more of the modulus of the lower substrate 110a, but is not limited thereto. For example, the elastic modulus of the pixel substrate 111 may be 2GPa to 9GPa depending on its transparency. More specifically, when the pixel substrate 111 is transparent, the elastic modulus is 2GPa, and when the pixel substrate 111 is opaque, the elastic modulus is 9 GPa.

In some exemplary embodiments, the lower substrate 110a may be defined to include a plurality of first and second lower patterns. The plurality of first lower patterns may be disposed in regions of the lower substrate 110a overlapping the plurality of pixel substrates 111 and the plurality of outer substrates 121. In addition, the second lower pattern may be disposed in an area except an area where the plurality of pixel substrates 111 and the plurality of outer substrates 121 are disposed. In addition to this, the second lower pattern may be disposed in the entire area of the retractable display apparatus 100.

In this case, the plurality of first lower patterns may have a modulus higher than that of the second lower patterns. For example, the plurality of first lower patterns may be formed of the same material as the plurality of pixel substrates 111. The second lower pattern may be formed of a material having a modulus lower than that of the plurality of pixel substrates 111.

The COF 130 is a flexible film formed by placing various components on the ductile base film 131 and is a component for supplying signals to a plurality of sub-pixels in the display area AA. The COF 130 may be coupled to a plurality of pads disposed in the non-display area NA and supply a data voltage or the like to a plurality of corresponding sub-pixels through the pads. The COF 130 may supply a pixel driving voltage, a gate clock voltage, and a gate driving voltage to the power supply unit PS and the gate driver GD in the non-display area NA. The COF 130 may include a base film 131 and a driving IC 132 and may further include various components. The power supply circuit PS (which may be referred to herein as a power supply unit PS) may include any circuit, feature, component, collection of electronic components, etc., configured to perform various operations of the power supply features described herein. In some embodiments, the power supply unit PS may be included in or implemented by a processing circuit such as a microprocessor, microcontroller, integrated circuit, chip, microchip, or the like.

The base film 131 serves to support the driving IC 132 of the COF 130. The base film 131 may be formed of an insulating material. For example, the base film 131 may be formed of an insulating material having flexibility.

The driving IC 132 is configured to process data for displaying an image and a driving signal for processing the data. Fig. 1 illustrates the mounting of the driving IC 132 by the method of the COF 130, but is not limited thereto. The driving ICs 132 may also be mounted by a Chip On Glass (COG) method, a Tape Carrier Package (TCP) method, or the like.

Fig. 1 illustrates that one external substrate 121 is disposed in the non-display area NA on the display area AA side so as to correspond to the pixel substrates 111 disposed in one row in the display area AA, and one COF 130 is disposed for one external substrate 121. However, the present disclosure is not limited thereto. That is, one external substrate 121 and one COF 130 may be disposed to correspond to the pixel substrates 111 in a plurality of rows.

In the printed circuit board 140, a control unit (control circuit) such as an IC chip, a circuit, or the like may be mounted. Further, a memory, a processor, and the like may be mounted on the printed circuit board 140. The printed circuit board 140 is configured to transfer a signal for driving the light emitting element from the control unit to the light emitting element. Although fig. 1 illustrates the use of three printed circuit boards 140, the number of printed circuit boards 140 is not limited thereto.

Hereinafter, the retractable display apparatus 100 according to an exemplary embodiment of the present disclosure will be described in more detail with reference to fig. 2 to 3.

< planar and sectional structures >

Fig. 2 is an enlarged plan view of the region X illustrated in fig. 1. Fig. 3 is a sectional view taken along line III-III' of fig. 2.

Referring to fig. 1 and 2, a plurality of pixel substrates 111 are disposed on the lower substrate 110a in the display area AA. A plurality of pixel substrates 111 are disposed on the lower substrate 110a to be spaced apart from each other. For example, a plurality of pixel substrates 111 may be disposed on the lower substrate 110a in a matrix form as shown in fig. 1 and 2, but is not limited thereto.

Referring to fig. 1 and 2, a plurality of sub-pixels SPX constituting a plurality of pixels PX may be disposed in a plurality of pixel substrates 111. In addition, the gate driver GD and the power supply unit PS may be mounted on the outer substrate 121 located at both sides in the X-axis direction among the plurality of outer substrates 121.

The gate driver GD may be formed on the outer substrate 121 in a gate-in-panel (GIP) manner. More specifically, one stage of the gate driver GD may be disposed on each of the plurality of external substrates 121. Accordingly, various circuit components such as various transistors, capacitors, lines, and the like, which constitute one stage of the gate driver GD, may be disposed on the plurality of external substrates 121.

In addition, the respective stages of the gate driver GD formed on the external substrate 121 may be electrically connected to each other. That is, the respective stages of the gate driver GD formed on the outer substrate 121 are electrically connected to each other to thereby transfer the gate voltage output from any one stage to another stage connected to the one stage. A specific driving method of the gate driver GD will be described later with reference to fig. 4.

However, the gate driver GD is not limited to be mounted in a gate-in-panel (GIP) manner, and the gate driver GD may be mounted in a chip-on-film (COF) manner.

In addition, the power supply unit PS may be formed on the outer substrate 121. In other words, the power supply unit PS may be formed on the outer substrate 121 adjacent to the gate driver GD.

In addition, the power supply unit PS is connected to the gate driver GD to supply a gate driving voltage and a gate clock voltage. In addition, the power supply unit PS is connected to the plurality of pixels PX to supply a pixel driving voltage to each of the plurality of pixels PX.

In addition, the respective power supply units PS formed on the plurality of outer substrates 121 may be electrically connected to each other. That is, the plurality of power supply units PS formed on the plurality of outer substrates 121 may be connected to each other through the gate power connection lines and the pixel power connection lines. Accordingly, each of the plurality of power supply units PS may supply the gate driving voltage, the gate clock voltage, and the pixel driving voltage through the gate power link and the pixel power link.

Specific connection relationships of the power supply unit PS will be described later with reference to fig. 5 to 7.

Meanwhile, referring to fig. 1, the plurality of outer substrates 121 may have a size greater than that of the plurality of pixel substrates 111. Specifically, the size of each of the plurality of outer substrates 121 may be larger than the size of each of the plurality of pixel substrates 111. As described above, the gate driver GD and the power supply unit PS are disposed on each of the plurality of external substrates 121. Accordingly, since the area occupied by the gate driver GD and the power supply unit PS is relatively larger than the area of the pixel substrate 111 on which the pixels PX are disposed, the size of each of the plurality of outer substrates 121 may be larger than the size of each of the plurality of pixel substrates 111.

Referring to fig. 1 and 2, a plurality of connection supporters 120 may be disposed between the plurality of pixel substrates 111 or between the plurality of outer substrates 121. Otherwise, the plurality of connection supporters 120 may be disposed between the plurality of pixel substrates 111 and the plurality of outer substrates 121. The plurality of connection supporters 120 serve to connect the pixel substrates 111 adjacent to each other, the outer substrates 121 adjacent to each other, or the pixel substrates 111 and the outer substrates 121 to each other. The plurality of connection supports 120 may be formed of the same material as the pixel substrate 111 or the outer substrate 121 and may be simultaneously integrally formed with the pixel substrate 111 or the outer substrate 121. However, the present disclosure is not limited thereto.

Referring to fig. 2, the plurality of connection supports 120 have their curved shapes. For example, as shown in fig. 2, the plurality of connection supports 120 may have a sine wave shape. However, the shape of the plurality of connection supports 120 is not limited thereto. The plurality of connection supports 120 may be shaped differently. For example, the plurality of connection supports 120 may extend in a zigzag manner, or a plurality of diamond-shaped substrates may extend by being connected to each other at the apexes thereof. The number and shape of the plurality of connecting supports 120 shown in fig. 2 are provided by way of example. The number and shape of the plurality of connection supports 120 may vary depending on the design thereof.

Referring to fig. 3, a plurality of inorganic insulating layers are disposed on a plurality of pixel substrates 111. For example, the plurality of inorganic insulating layers may include the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114, but is not limited thereto. Various inorganic insulating layers may be additionally disposed on the plurality of pixel substrates 111, or one or more of the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114 may be omitted.

Referring to fig. 3, the buffer layer 112 is disposed on the plurality of pixel substrates 111. A buffer layer 112 is formed on the plurality of pixel substrates 111 to protect various components of the scalable display device 100 from moisture (H)₂O), oxygen (O)₂) Etc. from the outside of the lower substrate 110a and the plurality of pixel substrates 111. The buffer layer 112 may be formed of an insulating material. For example, the buffer layer 112 may be formed of a single inorganic layer or a plurality of inorganic layers of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or the like. However, the buffer layer 112 may be omitted depending on the structure or characteristics of the scalable display device 100.

In this case, the buffer layer 112 may be formed only in a region overlapping the plurality of pixel substrates 111 and the plurality of outer substrates 121. As described above, the buffer layer 112 may be formed of an inorganic material. Therefore, while the retractable display device 100 is being retracted, the buffer layer 112 may be easily damaged, e.g., may be easily broken. Accordingly, the buffer layer 112 may not be formed in a region between the plurality of pixel substrates 111 and the plurality of outer substrates 121. The buffer layer 112 may be patterned in the shape of the plurality of pixel substrates 111 and the plurality of outer substrates 121 and formed only in the upper portions of the plurality of pixel substrates 111 and the plurality of outer substrates 121. Therefore, in the scalable display device 100 according to the exemplary embodiment of the present disclosure, the buffer layer 112 is formed only in a region overlapping with the plurality of pixel substrates 111 and the plurality of outer substrates 121 as the rigid substrate. Therefore, it is possible to prevent damage to the buffer layer 112 even when the retractable display device 100 is deformed such as bent or extended.

Referring to fig. 3, the driving transistor 150 including the gate electrode 151, the active layer 152, the source electrode 153, and the drain electrode 154 is formed on the buffer layer 112.

First, referring to fig. 3, the active layer 152 is disposed on the buffer layer 112. For example, the active layer 152 may be formed of an oxide semiconductor or may be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), an organic semiconductor, or the like.

The gate insulating layer 113 is disposed on the active layer 152. The gate insulating layer 113 serves as a layer for electrically insulating the gate electrode 151 and the active layer 152 and may be formed of an insulating material. For example, the gate insulating layer 113 may be formed of a single layer or a plurality of layers of silicon nitride (SiNx) or silicon oxide (SiOx) as an inorganic material, but is not limited thereto.

The gate electrode 151 is disposed on the buffer layer 112. The gate electrode 151 is disposed to overlap the active layer 152. The gate electrode 151 may be formed of any one of various metal materials, such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of two or more thereof, or a multi-layer thereof, but is not limited thereto.

An interlayer insulating layer 114 is disposed on the gate electrode 151. The interlayer insulating layer 114 serves to insulate the gate electrode 151 from the source electrode 153 and insulate the gate electrode 151 from the drain electrode 154 and may be formed of an inorganic material like the buffer layer 112. For example, the interlayer insulating layer 114 may be formed of a single layer or a plurality of layers of silicon nitride (SiNx) or silicon oxide (SiOx) as an inorganic material, but is not limited thereto.

A source electrode 153 and a drain electrode 154, which are in contact with the active layer 152, are disposed on the interlayer insulating layer 114. The source electrode 153 and the drain electrode 154 are disposed on the same layer to be spaced apart from each other. The source electrode 153 and the drain electrode 154 may be electrically connected to the active layer 152 to contact the active layer 152. The source electrode 153 and the drain electrode 154 may be formed of one of various metal materials, such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of two or more thereof, or a multilayer thereof.

In addition, the gate insulating layer 113 and the interlayer insulating layer 114 may be patterned and formed only in a region overlapping the plurality of pixel substrates 111. The gate insulating layer 113 and the interlayer insulating layer 114 may also be formed of an inorganic material like the buffer layer 112. Therefore, while the scalable display device 100 is scalable, the gate insulating layer 113 and the interlayer insulating layer 114 may be easily damaged, for example, may be easily broken. Accordingly, the gate insulating layer 113 and the interlayer insulating layer 114 may not be formed in a region between the plurality of pixel substrates 111. The gate insulating layer 113 and the interlayer insulating layer 114 may be patterned in the shape of the plurality of pixel substrates 111 and formed only on the plurality of pixel substrates 111.

For convenience of explanation, fig. 3 illustrates only a driving transistor among various transistors that can be included in the scalable display device 100. However, a switching transistor, a capacitor, or the like can also be included in the scalable display device. Further, in the present disclosure, the driving transistor 150 is described as having a coplanar structure, but various types of transistors having a staggered structure or the like may also be used.

Referring to fig. 3, a plurality of pads 170 are disposed on the interlayer insulating layer 114. Specifically, the gate pad 171 among the plurality of pads 170 is disposed on the interlayer insulating layer 114. The gate pad 171 serves to transfer a gate voltage to the plurality of subpixels SPX. The gate voltage may be transferred from the gate pad 171 to the gate electrode 151 through the gate line formed on the pixel substrate 111. The gate pad 171 may be formed of the same material as the source and drain

electrodes

153 and 154, but is not limited thereto.

Referring to fig. 3, a data pad 172 among a plurality of pads 170 is disposed on the interlayer insulating layer 114. The data pad 172 serves to transfer a data voltage to the plurality of subpixels SPX. The data voltage may be transferred from the data pad 172 to the source electrode 153 or the drain electrode 154 through the data line formed on the pixel substrate 111. The data pad 172 may be formed of the same material as the source and drain

electrodes

153 and 154, but is not limited thereto.

Referring to fig. 3, a planarization layer 115 is formed on the driving transistor 150 and the interlayer insulating layer 114. The planarization layer 115 serves to flatten the upper portion of the driving transistor 150. The planarization layer 115 may be formed of a single layer or a plurality of layers and formed of an organic material. For example, the planarization layer 115 may be formed of an acrylic organic material, but is not limited thereto.

Referring to fig. 3, a planarization layer 115 is disposed on the plurality of pixel substrates 111 to cover upper surfaces and side surfaces of the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114. Accordingly, the planarization layer 115 surrounds the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114 together with the plurality of pixel substrates 111. Specifically, the planarization layer 115 may be disposed to cover the upper surface and the side surfaces of the interlayer insulating layer 114, the side surfaces of the gate insulating layer 113, the side surfaces of the buffer layer 112, and a portion of the upper surface of the plurality of pixel substrates 111. Accordingly, the planarization layer 115 may compensate for steps between side surfaces of the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114. In addition, the planarization layer 115 may improve the adhesive strength between the planarization layer 115 and the pixel connection line 180 disposed on the side surface of the planarization layer 115.

Referring to fig. 3, the inclination angle of the side surface of the planarization layer 115 may be lower than the inclination angles of the side surfaces of the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114. For example, the side surface of the planarization layer 115 may have a lower inclination than the inclination of the side surface of the interlayer insulating layer 114, the side surface of the gate insulating layer 113, and the side surface of the buffer layer 112. Accordingly, the pixel connection line 180 contacting the side surface of the planarization layer 115 is disposed to have a low inclination. Therefore, when the scalable display device 100 is scaled, stress generated in the pixel connection lines 180 can be reduced. In addition, it is possible to suppress cracks in the pixel connection line 180 or peeling of the pixel connection line 180 from the side surface of the planarization layer 115.

In some embodiments, a passivation layer may be formed between the driving transistor 150 and the planarization layer 115. That is, a passivation layer covering the driving transistor 150 may be formed to protect the driving transistor 150 from penetration of moisture, oxygen, or the like. The passivation layer may be formed of an inorganic material and formed of a single layer or a plurality of layers, but is not limited thereto.

Referring to fig. 3, the common line CL is disposed on the gate insulating layer 113. The common line CL is used to apply a common voltage to the plurality of subpixels SPX. The common line CL may be formed of the same material as the gate electrode 151 of the driving transistor 150, but is not limited thereto.

Referring to fig. 2 and 3, the pixel connection line 180 refers to a line electrically connecting a plurality of pixels PX disposed on the pixel substrate 111. The pixel connection line 180 is disposed on the pixel substrate 111 and the plurality of connection supports 120.

The pixel connection line 180 includes a first pixel connection line 181 and a second pixel connection line 182. The first and second

pixel connection lines

181 and 182 are disposed between the plurality of pixel substrates 111. Specifically, the first pixel connection line 181 denotes a line extending in the X-axis direction between the plurality of pixel substrates 111 among the pixel connection lines 180. The second pixel connection line 182 denotes a line extending in the Y-axis direction between the plurality of pixel substrates 111 among the pixel connection lines 180.

The pixel connection line 180 may be formed of a metal material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), gold (Au), and silver (Ag). Otherwise, the pixel connection line 180 may have a stacked structure of metal materials such as copper/molybdenum titanium (Cu/MoTi), titanium/aluminum/titanium (Ti/Al/Ti), etc., but is not limited thereto.

In a general organic light emitting display device, various lines such as a plurality of gate lines and a plurality of data lines extend in straight lines and are disposed between a plurality of sub-pixels. In addition, a plurality of sub-pixels are connected to a single signal line. Accordingly, in the general organic light emitting display device, various lines such as a gate line, a data line, a high potential pixel driving voltage line, and a reference voltage line continuously extend from one side to the other side of the organic light emitting display device on the substrate.

In contrast to this, in the retractable display device 100 according to the exemplary embodiment of the present disclosure, various lines, such as gate lines, data lines, and reference voltage lines, which are formed in a straight line and are considered to be used in a general organic light emitting display device, are disposed only on the plurality of pixel substrates 111 and the plurality of outer substrates 121. That is, in the scalable display device 100 according to the exemplary embodiment of the present disclosure, lines formed in straight lines are disposed only on the plurality of pixel substrates 111 and the plurality of outer substrates 121.

In the scalable display device 100 according to the exemplary embodiment of the present disclosure, the pads on two adjacent pixel substrates 111 or one pixel substrate 111 and one outer substrate 121 adjacent to each other may be connected by the pixel connection line 180 so as to connect the discontinuous lines on the pixel substrates 111 or the outer substrate 121. That is, the pixel connection line 180 electrically connects two adjacent pixel substrates 111 and pads on the adjacent pixel substrates 111 and the outer substrate 121. Accordingly, the scalable display device 100 according to the exemplary embodiment of the present disclosure may include a plurality of pixel connection lines 180 to electrically connect various lines, such as gate lines, data lines, and reference voltage lines, between the plurality of pixel substrates 111 and the plurality of outer substrates 121. For example, the gate lines may be disposed on a plurality of pixel substrates 111 disposed adjacent to each other in the X-axis direction and the gate pads 171 may be disposed on both ends of the gate lines. In this case, the plurality of gate pads 171 on the plurality of pixel substrates 111 disposed adjacent to each other in the X-axis direction may be connected to each other by the first pixel connection line 181 serving as a gate line. Accordingly, the gate lines disposed on the plurality of pixel substrates 111 and the first pixel connection line 181 disposed on the outer substrate 121 may be used as a single gate line. Further, among all the various lines that can be included in the retractable display apparatus 100, lines extending in the X-axis direction, such as the light emitting signal line, the low-potential pixel driving voltage line, and the high-potential pixel driving voltage line, may also be electrically connected through the first pixel connection line 181 as described above.

Referring to fig. 2 and 3, the first pixel connection line 181 may connect pads on two pixel substrates 111 disposed side by side among pads on a plurality of pixel substrates 111 disposed adjacent to each other in the X-axis direction. The first pixel connection line 181 may serve as a gate line, a light emitting signal line, a high-potential pixel driving voltage line, or a low-potential pixel driving voltage line, but is not limited thereto. For example, the first pixel connection line 181 may serve as a gate line and electrically connect the gate pads 171 on the two pixel substrates 111 disposed side by side in the X-axis direction. Accordingly, as described above, the gate pad 171 on the plurality of pixel substrates 111 disposed in the X-axis direction may be connected by the first pixel link line 181 serving as a gate line. A single gate signal may be transferred to the gate pad 171.

Referring to fig. 2, the second pixel connection line 182 may connect pads on two pixel substrates 111 disposed side by side among pads on a plurality of pixel substrates 111 disposed adjacent to each other in the Y-axis direction. The second pixel connection line 182 may function as a data line or a reference voltage line, but is not limited thereto. For example, the second pixel connection line 182 may serve as a data line and electrically connect the data lines on two pixel substrates 111 disposed side by side in the Y-axis direction. Therefore, as described above, the data lines on the plurality of pixel substrates 111 disposed in the Y-axis direction may be connected by the plurality of second pixel connection lines 182 serving as the data lines. A single data signal may be transferred to the data line.

Referring to fig. 1, the pixel connection line 180 may further include a line connecting the plurality of pixel substrates 111 and the plurality of pads on the outer substrate 121.

The first pixel connection line 181 is in contact with the upper surface and the side surface of the planarization layer 115 disposed on the pixel substrate 111 and may extend to the upper surface of the connection supporter 120. In addition, the second pixel connection line 182 is in contact with the upper surface and the side surface of the planarization layer 115 disposed on the pixel substrate 111 and may extend to the upper surface of the connection support 120. The arrangement and the composite effect of the first and second

pixel connection lines

181 and 182 will be described in detail later.

Referring to fig. 3, the bank 116 is formed on the first connection pad 191, the second connection pad 192, the pixel connection line 180, and the planarization layer 115. The bank 116 is a component for distinguishing the sub-pixels SPX adjacent to each other.

The bank 116 is disposed to cover the first connection pad 191 and a portion of the second pixel connection line 182 adjacent thereto or the second connection pad 192 and at least a portion of the first pixel connection line 181 adjacent thereto. The bank 116 may be formed of an insulating material. In addition, the bank 116 may include a black material. Since the bank 116 includes a black material, the bank 116 serves to hide lines visible through the display area AA. The bank 116 may be formed of, for example, a transparent carbon-based compound. Specifically, the bank 116 may include carbon black, but is not limited thereto. The bank 116 may also be formed of a transparent insulating material.

Referring to fig. 3, the LEDs 160 are disposed on the first and

second connection pads

191 and 192. The LED 160 includes an n-type layer 161, an active layer 162, a p-type layer 163, an n-electrode 164, and a p-electrode 165. The LED 160 of the retractable display device 100 according to the exemplary embodiment of the present disclosure has a flip chip structure in which an n-electrode 164 and a p-electrode 165 are formed on one surface thereof.

The n-type layer 161 may be formed by implanting n-type impurities into gallium nitride (GaN) having excellent crystallinity. The n-type layer 161 may be disposed on a separate base substrate formed of a light emitting material.

The active layer 162 is disposed on the n-type layer 161. The active layer 162 is a light emitting layer emitting light in the LED 160 and may be formed of a nitride semiconductor such as indium gallium nitride (InGaN). The p-type layer 163 is disposed on the active layer 162. The p-type layer 163 may be formed by implanting p-type impurities into gallium nitride (GaN).

The LED 160 according to an exemplary embodiment of the present disclosure is manufactured by sequentially stacking an n-type layer 161, an active layer 162, and a p-type layer 163, and then etching predetermined regions of the layers to thereby form an n-electrode 164 and a p-electrode 165. In this case, the predetermined region is a space that separates the n-electrode 164 and the p-electrode 165 from each other and is etched to expose a portion of the n-type layer 161. In other words, the surface of the LED 160 on which the n-electrode 164 and the p-electrode 165 will be disposed may not be flat and may have different height levels.

The n-electrode 164 is disposed on the etched region, i.e., on the n-type layer 161 exposed by etching. The n-electrode 164 may be formed of a conductive material. Meanwhile, the p-electrode 165 is disposed on the non-etched region, i.e., on the p-type layer 163. The p-electrode 165 may be formed of a conductive material. For example, the p-electrode 165 may be formed of the same material as the n-electrode 164.

The adhesive layer AD is disposed on the upper surfaces of the first and

second connection pads

191 and 192 and between the first and

second connection pads

191 and 192. Accordingly, the LED 160 can be incorporated into the first and second connection

upper pads

191 and 192. In this case, the n-electrode 164 may be disposed on the second connection pad 192 and the p-electrode 165 may be disposed on the first connection pad 191.

The adhesive layer AD may be a conductive adhesive layer formed by dispersing conductive balls in an insulating base member. Therefore, when heat or pressure is applied to the adhesive layer AD, the conductive balls are electrically connected to have a conductive property in a portion of the adhesive layer AD to which heat or pressure is applied. Also, the region of the adhesive layer AD to which pressure is not applied may have an insulating property. For example, the n-electrode 164 is electrically connected to the second pixel connection line 182 through the adhesive layer AD and the p-electrode 165 is electrically connected to the first pixel connection line 181 through the adhesive layer AD. That is, after the adhesive layer AD is applied to the first and

second connection pads

191 and 192 by an inkjet method or the like, the LEDs 160 may be transferred onto the adhesive layer AD. Then, the LED 160 may be pressurized and heated to thereby electrically connect the first connection pad 191 to the p-electrode 165 and the second connection pad 192 to the n-electrode 164. However, other portions of the adhesive layer AD than a portion of the adhesive layer AD between the n-electrode 164 and the second connection pad 192 and a portion of the adhesive layer AD between the p-electrode 165 and the first connection pad 191 have an insulating property. Meanwhile, the adhesive layer AD may be separately disposed on each of the first and

second connection pads

191 and 192.

As described above, the scalable display device 100 according to the exemplary embodiment of the present disclosure has a structure in which the LED 160 is disposed on the lower substrate 110a in which the driving transistor 150 is disposed. Accordingly, when the scalable display device 100 is turned on, a voltage of a different level applied to each of the first and

second connection pads

191 and 192 is transferred to the n-electrode 164 and the p-electrode 165, so that the LED 160 emits light.

Referring to fig. 3, a stretchable upper substrate 110b is disposed on the bank 116, the LEDs 160, and the lower substrate 110 a.

The flexible upper substrate 110b serves to support various components disposed below the flexible upper substrate 110 b. The stretchable upper substrate 110b is a flexible substrate and may be formed of a bendable or stretchable insulating material. For example, the stretchable upper substrate 110b may be formed of a material having flexibility, and may be formed of the same material as the lower substrate 110a, but is not limited thereto. Specifically, the stretchable upper substrate 110b may be formed by coating a material configuring the stretchable upper substrate 110b on the lower substrate 110a and the pixel substrate 111 and hardening it. Accordingly, the stretchable upper substrate 110b may be disposed in contact with the lower substrate 110a, the pixel substrate 111, the connection supporter 120, and the pixel connection line 180.

The stretchable upper substrate 110b is a flexible substrate and may be formed of a bendable or stretchable insulating material. The stretchable upper substrate 110b is a flexible substrate and can be reversibly expanded and contracted. In addition, the stretchable upper substrate 110b may have an elastic modulus of several MPa to several hundreds MPa. In addition, the stretchable upper substrate 110b may have an elongation at break of 100% or more. The thickness of the stretchable upper substrate 110b may be from 10 μm to 1mm, but is not limited thereto.

The stretchable upper substrate 110b may be formed of the same material as the lower substrate 110 a. For example, the stretchable upper substrate 110b may be formed of a silicone rubber such as Polydimethylsiloxane (PDMS) and an elastomer such as Polyurethane (PU), Polytetrafluoroethylene (PTFE), and the like. Accordingly, the stretchable upper substrate 110b may have flexibility. However, the material of the stretchable upper substrate 110b is not limited thereto.

Meanwhile, although not illustrated in fig. 3, a polarizing layer may be disposed on the stretchable upper substrate 110 b. The polarizing layer polarizes light incident from the outside of the retractable display device 100 and reduces reflection of the external light. Further, instead of the polarizing layer, another optical film or the like may be provided on the stretchable upper substrate 110 b.

In a conventional scalable display device, a planarization layer formed of an organic insulating material does not cover side surfaces of a plurality of inorganic insulating layers including a buffer layer, a gate insulating layer, and an interlayer insulating layer. Alternatively, the planarization layer is disposed on the plurality of inorganic insulating layers. Therefore, the connection line is disposed in contact with the side surfaces of the plurality of inorganic insulating layers. However, when a patterning process, i.e., an etching process, is performed on the plurality of inorganic insulating layers, steps may be generated between side surfaces of the plurality of inorganic insulating layers. That is, the side surfaces of the plurality of inorganic insulating layers have a significantly high inclination after the etching process. Therefore, if the connection lines are directly formed on the side surfaces of the plurality of inorganic insulating layers, the connection lines may be short-circuited.

Therefore, in the scalable display device 100 according to the exemplary embodiment of the present disclosure, the planarization layer 115 is disposed to cover the side surfaces of the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114. Therefore, when the scalable display device 100 is repeatedly stretched and contracted, it is possible to suppress peeling of the pixel connection line 180 from the side surfaces of the flattening layer 115 and the plurality of inorganic insulating layers. More specifically, the pixel connection line 180 formed of Cu or other low-resistance metal material is disposed on the upper surface and the side surface of the planarization layer 115 formed of an organic insulating material. Accordingly, the adhesive strength of the lower portion of the pixel connection line 180 can be improved. Therefore, in the scalable display device 100 according to the exemplary embodiment of the present disclosure, the planarization layer 115 is disposed to cover side surfaces of a plurality of inorganic insulating layers such as the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114 on the first substrate 111. Therefore, when the retractable display device 100 is repeatedly retracted and extended, it is possible to suppress the pixel connection lines 180 from being peeled off from the planarization layer 115. Therefore, the retractable display device 100 can be improved. In addition, in the scalable display device 100 according to the exemplary embodiment of the present disclosure, the planarization layer 115 is disposed to cover side surfaces of a plurality of inorganic insulating layers (such as the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114) between the pixel substrate 111 and the planarization layer 115. Accordingly, the planarization layer 115 can compensate for steps between side surfaces of the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114. That is, the planarization layer 115 is disposed to cover upper surfaces and side surfaces of the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114. In addition, the inclination angle of the side surface of the planarization layer 115 may be lower than the inclination angles of the side surfaces of the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114. That is, the side surface of the planarization layer 115 may have a more gentle slope than the slopes of the side surface of the interlayer insulating layer 114, the side surface of the gate insulating layer 113, and the side surface of the buffer layer 112. Therefore, the pixel connection line 180 contacting the side surface of the planarization layer 115 is disposed at a gentle slope. Therefore, when the pixel connection line 180 is formed, the occurrence of cracks in the pixel connection line 180 can be suppressed. In addition, when the scalable display device 100 is scaled, stress generated in the pixel connection line 180 can be reduced. Further, it is possible to suppress cracks in the pixel connection line 180 or peeling of the pixel connection line 180 from the side surface of the planarization layer 115.

Further, in the scalable display device 100 according to the exemplary embodiment of the present disclosure, the pixel connection line 180 may have the same shape as the connection support 120 and thus may have a sine wave shape. Therefore, the resistance of the pixel connection line 180 may increase as compared to the case where the pixel connection line 180 has a straight shape. Accordingly, copper (Cu) having a low resistance among various metal materials that can be used for the lines may be used in the pixel connection line 180 in order to reduce the resistance of the pixel connection line 180. However, when Cu or other low-resistance metal material is formed on the inorganic insulating layer, the adhesive strength between the metal material and the inorganic insulating layer may be problematic. That is, Cu or other low-resistance metal material has a small adhesive strength with respect to the inorganic insulating layer. Therefore, if the pixel link line 180 is disposed in contact with the side portions of the plurality of inorganic insulating layers, such as the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114, the pixel link line 180 may be peeled off from the side surfaces of the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114 when the scalable display device 100 is scaled. Therefore, the reliability of the scalable display device 100 may be degraded.

Further, in the scalable display device 100 according to the exemplary embodiment of the present disclosure, the planarization layer 115 is disposed on the plurality of inorganic insulating layers, such as the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114, and the driving transistor 150. Therefore, when the LED 160 is transferred, it is possible to protect the components disposed under the planarization layer 115. When the LED 160 is disposed on the retractable display device 100, the LED 160 may be pressed from above the retractable display device 100. In this case, the driving transistor 150, the various lines, and the connection line 180 disposed under the LED 160 may be damaged by pressure. Accordingly, the planarization layer 115 is disposed on the buffer layer 112, the gate insulating layer 113, the interlayer insulating layer 114, and the driving transistor 150. Therefore, when the LED 160 is transferred, stress caused by pressing can be reduced. Accordingly, damage to the driving transistor 150, various lines, the connection line 180, and the like, which are disposed under the planarization layer 115, can be reduced.

< method for driving gate driver >

Fig. 4 is a block diagram for illustrating driving of a gate driver according to an exemplary embodiment of the present disclosure.

Referring to fig. 4, the gate driver GD of the scalable display device according to an exemplary embodiment of the present disclosure may be configured by a shift register including first to nth stages S1, S2, S3 to S (n-1) and Sn, which receive a high potential gate driving voltage VGH and a low potential gate driving voltage VGL according to a gate clock voltage CLK and output gate voltages Vout1, Vout2, Vout3 to Vout (n-1) and Vout (n), respectively.

As described above, the first to nth stages S1, S2, S3 to S (n-1), and Sn are separately provided on the outer substrate 121. However, the present disclosure is not limited thereto, and a plurality of stages among the first to nth stages S1, S2, S3 to S (n-1), and Sn may be disposed on one outer substrate 121 having an island shape according to design requirements.

In addition, the gate clock voltage CLK may include a plurality of gate clock voltages having different phases. For example, the gated clock voltage CLK may include a first gated clock voltage and a second gated clock voltage, and the phase of the first gated clock voltage is opposite to the phase of the second gated clock voltage. However, the present disclosure is not limited thereto, and the phase and the number of the gate clock voltage CLK may be variously changed according to driving needs.

Accordingly, the first stage S1 receives the gate start signal VST and outputs the first gate voltage Vout1 using the gate clock voltage CLK. Thereafter, the second stage S2 outputs a second gate voltage using the gate clock voltage CLK and the first gate voltage Vout1 output from the first stage S1. Thereafter, the third through nth stages S3 through Sn sequentially output third through nth gate voltages Vout3 through Vout (n) using the gate clock voltage CLK and gate voltages Vout2 through Vout (n-1) output from the previous stages S2 through S (n-1).

< Gate driver and Power supply Unit >

Fig. 5A and 5B are enlarged plan views of the region Y illustrated in fig. 1. Fig. 6 is a sectional view taken along line VI-VI' of fig. 5A.

Referring to fig. 5A, the gate driver GD, the power supply unit PS, and the plurality of power supply lines PSL1 to PSL7 may be formed on the outer substrate 121 disposed in the non-display area NA.

Specifically, the gate driver GD is disposed at one side of the power supply unit PS in the X-axis direction. Then, the gate driver GD receives a plurality of powers from the power supply unit PS and outputs a gate voltage to the first sub-pixel connection line 181a as a gate line.

Also, the plurality of power supply lines PSL1 to PSL7 extend along the X axis and overlap the power supply unit PS. Accordingly, the plurality of power supply lines PSL1 to PSL7 are connected to the power supply unit PS through the contact holes to transfer the plurality of voltages to the gate driver GD and the plurality of pixels PX.

In addition, the power supply unit PS may include: a gate power supply unit GPSa applying a gate clock voltage and a gate driving voltage to the gate driver GD; and a pixel power supply unit (power supply circuit) PPS that applies a pixel drive voltage to each of the plurality of pixels PX. The gated power supply circuit GPSa (which may be referred to herein as the gated power supply unit GPSa) and the pixel power supply circuit PPS (which may be referred to herein as the pixel power supply unit PPS) may include any circuitry, features, components, combinations of electronic components, etc., configured to perform various operations of the gated power supply features and the pixel power supply features as described herein. In some embodiments, the gate power supply unit GPSa and the pixel power supply unit PPS may be included in or implemented by a processing circuit such as a microprocessor, microcontroller, integrated circuit, chip, microchip, or the like.

In fig. 5A, the gate power supply unit GPSa is disposed at one side of the pixel power supply unit PPS in the X-axis direction. That is, in the X-axis direction, the pixel power supply unit PPS, the gate power supply unit GPSa, and the gate driver GD may be sequentially disposed.

The pixel power supply unit PPS applies a high potential pixel driving voltage and a low potential pixel driving voltage to each of the plurality of pixels PX disposed in the display area AA. That is, the pixel power supply unit PPS may include: a first sub-pixel power supply unit PPS1 that applies a low potential pixel driving voltage to each of the plurality of pixels PX; and a second sub-pixel power supply unit PPS2 that applies a high-potential pixel driving voltage to each of the plurality of pixels PX. In fig. 5A, the second sub-pixel power supply unit PPS2 is disposed on one side of the first sub-pixel power supply unit PPS1 in the X-axis direction.

In addition, the pixel power supply unit PPS is connected to the pixel power connection line PCL and receives not only the high-potential pixel driving voltage and the low-potential pixel driving voltage but also supplies the high-potential pixel driving voltage and the low-potential pixel driving voltage to another pixel power supply unit PPS.

The other pixel power supply unit PPS described above refers to an individual pixel power supply unit PPS formed on the other outer substrate 121 adjacent thereto.

In particular, the first sub-pixel power supply unit PPS1 is connected to the first sub-pixel power connection line PCL 1. Specifically, the plurality of first sub-pixel power connection lines PCL1 are spaced apart in the Y-axis direction. In addition, the first sub-pixel power connection line PCL1 extends in the Y-axis direction and electrically connects a plurality of first sub-pixel power supply units PPS1 spaced apart from each other. Thus, the first sub-pixel power supply unit PPS1 may receive a low potential pixel driving voltage through the first sub-pixel power connection line PCL1 or supply the low potential pixel driving voltage to another first sub-pixel power supply unit PPS1 through the first sub-pixel power connection line PCL 1.

Further, the second sub-pixel power supply unit PPS2 is connected to the second sub-pixel power connection line PCL 2. Specifically, a plurality of second sub-pixel power supply units PPS2 are also spaced in the Y-axis direction. The second sub-pixel power connection line PCL2 also extends in the Y-axis direction and electrically connects the plurality of second sub-pixel power supply units PPS 2. Thus, the second sub-pixel power supply unit PPS2 may receive a high potential pixel driving voltage through the second sub-pixel power connection line PCL2 or supply the high potential pixel driving voltage to another second sub-pixel power supply unit PPS2 through the second sub-pixel power connection line PCL 2.

In this regard, the pixel power supply unit PPS is formed on the outer substrate 121 as a rigid substrate and does not expand and contract, whereas the pixel power connection line PCL is formed on the lower substrate 110a as a flexible substrate that expands and contracts.

Therefore, the plurality of pixel power connection lines PCL may have a shape in which they are bent such that they are extended and contracted. For example, as illustrated in fig. 5A, the plurality of pixel power connection lines PCL may have a sine wave shape. However, the shape of the plurality of pixel power connection lines PCL is not limited thereto. The plurality of pixel power connection lines PCL may be shaped differently. For example, the plurality of pixel power connection lines PCL may extend in a zigzag manner, or a plurality of diamond-shaped substrates may extend by being connected to each other at the apexes thereof. The number and shape of the plurality of pixel power connection lines PCL shown in fig. 5A are provided by way of example. The number and shape of the plurality of pixel power connection lines PCL may vary depending on the design thereof.

However, when the plurality of pixel power connection lines PCL have their curved shapes, the entire length of the plurality of pixel power connection lines PCL increases. Accordingly, the resistance of the plurality of pixel power connection lines PCL increases, thereby causing an IR drop in the pixel driving voltage. As a result, a defect that the plurality of pixels PX do not achieve a desired gray may occur.

Therefore, each of the pixel power supply units PPS formed on the outer substrate 121, which is a rigid substrate, may be arranged in a plate shape.

That is, the width of the plate-shaped pixel power supply unit PPS may be greater than the width of the pixel power connection line PCL. Thus, as illustrated in fig. 5A, four first sub-pixel power connection lines PCL1 may be connected to the first sub-pixel power supply unit PPS 1. However, the number of the first sub-pixel power connection lines PCL1 connected to the first sub-pixel power supply unit PPS1 is not limited thereto and may be variously modified according to design requirements.

Since the width of the plate-shaped pixel power supply unit PPS is greater than the width of the pixel power connection line PCL, the resistance of the plate-shaped pixel power supply unit PPS may be lower than that of the pixel power connection line PCL. Therefore, the degree of IR drop of the pixel drive voltage can be reduced. Therefore, by configuring the pixel power supply unit PPS in a plate shape, the pixel driving voltage can reach the target voltage, so that the plurality of pixels PX can normally realize the gray scale.

As described above, the low potential pixel driving voltage may be charged in the first sub-pixel power supply unit PPS1, and the high potential pixel driving voltage may be charged in the second sub-pixel power supply unit PPS 2.

In addition, the first sub-pixel power supply unit PPS1 may supply the low-potential pixel driving voltage to the second sub-pixel connection line 181b as the low-potential pixel driving voltage line through the first power supply line PSL 1. Specifically, the first sub-pixel power supply unit PPS1 may be electrically connected to the first power supply line PSL1 through a contact hole, and the first power supply line PSL1 may be connected to the second sub-pixel connection line 181 b. Accordingly, the low-potential pixel driving voltage charged in the first sub-pixel power supply unit PPS1 may be transferred to the second sub-pixel connection line 181b and supplied to the plurality of pixels PX.

In addition, the second sub-pixel power supply unit PPS2 may supply the high-potential pixel driving voltage to the third sub-pixel connection line 181c as the high-potential pixel driving voltage line through the second power supply line PSL 2. Specifically, the second sub-pixel power supply unit PPS2 may be electrically connected to the second power supply line PSL2 through a contact hole, and the second power supply line PSL2 may be connected to the third sub-pixel connection line 181 c. Accordingly, the high-potential pixel driving voltage charged in the second sub-pixel power supply unit PPS2 can be transferred to the third sub-pixel connection line 181c and supplied to the plurality of pixels PX.

The gate power supply unit GPSa applies a gate clock voltage, a high potential gate driving voltage, and a low potential gate driving voltage to the gate driver GD disposed in the non-display area NA. That is, the gate power supply unit GPSa may include: a first sub-gate power supply unit GPSa1 for applying a first gate clock voltage to the gate driver GD; a second sub-gate power supply unit GPSa2 for applying a second gate clock voltage to the gate driver GD; a third sub-gate power supply unit GPSa3 for applying a low-potential gate driving voltage to the gate driver GD; and a fourth sub-gate power supply unit GPSa4 for applying a high-potential gate driving voltage to the plurality of gate drivers GD. In fig. 5A, the first to fourth sub-gate power supply units GPSa1 to GPSa4 may be sequentially disposed in the X-axis direction.

In addition, the gate power supply unit GPSa is connected to the gate power connection line GCL and receives not only the gate clock voltage, the high-potential gate driving voltage, and the low-potential gate driving voltage but also supplies the gate clock voltage, the high-potential gate driving voltage, and the low-potential gate driving voltage to another gate power supply unit GPSa.

The other gate power supply unit GPSa as described above is an individual gate power supply unit GPSa formed on the other outer substrate 121 adjacent thereto.

Specifically, the first sub-gate power supply unit GPSa1 is connected to the first sub-gate power connection line GCL 1. Specifically, the plurality of first sub-gate power supply units GPSa1 are spaced in the Y-axis direction, and the first sub-gate power connection line GCL1 extends in the Y-axis direction and electrically connects the plurality of first sub-gate power supply units GPSa 1. Accordingly, the first sub-gated power supply unit GPSa1 receives the first gated clock voltage through the first sub-gated power connection line GCL1 or supplies the first gated clock voltage to another first sub-gated power supply unit GPSa1 through the first sub-gated power connection line GCL 1.

In addition, the second sub-gate power supply unit GPSa2 is connected to the second sub-gate power connection line GCL 2. Specifically, the plurality of second sub-gate power supply units GPSa2 are also spaced in the Y-axis direction, and the second sub-gate power connection line GCL2 extends in the Y-axis direction and electrically connects the plurality of second sub-gate power supply units GPSa 2. Accordingly, the second sub-gated power supply unit GPSa2 receives the second gated clock voltage through the second sub-gated power connection line GCL2 or supplies the second gated clock voltage to another second sub-gated power supply unit GPSa2 through the second sub-gated power connection line GCL 2.

In addition, the third sub-gate power supply unit GPSa3 is connected to the third sub-gate power connection line GCL 3. Specifically, the plurality of third sub-gate power supply units GPSa3 are also spaced in the Y-axis direction, and the third sub-gate power connection line GCL3 extends in the Y-axis direction and electrically connects the plurality of third sub-gate power supply units GPSa 3. Accordingly, the third sub-gate power supply unit GPSa3 receives the low potential gate driving voltage through the third sub-gate power connection line GCL3 or supplies the low potential gate driving voltage to another third sub-gate power supply unit GPSa3 through the third sub-gate power connection line GCL 3.

In addition, the fourth sub-gate power supply unit GPSa4 is connected to the fourth sub-gate power connection line GCL 4. Specifically, the plurality of fourth sub-gate power supply units GPSa4 are also spaced in the Y-axis direction, and the fourth sub-gate power connection line GCL4 extends in the Y-axis direction and electrically connects the plurality of fourth sub-gate power supply units GPSa 4. Accordingly, the fourth sub gate power supply unit GPSa4 receives the high-potential gate driving voltage through the fourth sub gate power connection line GCL4 or supplies the high-potential gate driving voltage to another fourth sub gate power supply unit GPSa4 through the fourth sub gate power connection line GCL 4.

In this regard, the gate power supply unit GPSa is formed on the outer substrate 121 as a rigid substrate and thus does not expand and contract, while the gate power connection line GCL is formed on the lower substrate 110a as a flexible substrate that expands and contracts.

Therefore, the plurality of gate power connection lines GCL may have a shape in which they are bent such that they are extended and contracted. For example, as illustrated in fig. 5A, the plurality of gate power connection lines GCL may have a sine wave shape. However, the shape of the plurality of gate power connection lines GCL is not limited thereto. The plurality of gate power connection lines GCL may be shaped differently. For example, the plurality of gate power connection lines GCL may extend in a zigzag manner, or a plurality of diamond-shaped substrates may extend by being connected to each other at the apexes thereof. In addition, the number and shape of the plurality of gate power connection lines GCL shown in fig. 5A are provided by way of example. The number and shape of the plurality of gated power connection lines GCL may vary depending on the design thereof.

In addition, each of the gate power supply units GPSa formed on the outer substrate 121, which is a rigid substrate, may be configured in a plate shape.

That is, the width of the plate-shaped gated power supply unit GPSa may be greater than the width of the gated power connection line GCL. Accordingly, as illustrated in fig. 5A, four first sub-gate power connection lines GCL1 may be connected to the first sub-gate power supply unit GPSa 1. However, the number of the first sub-gate power connection lines GCL1 connected to the first sub-gate power supply unit GPSa1 is not limited thereto and may be variously modified according to design requirements.

Since the plate-shaped gated power supply unit GPSa has a width greater than that of the gated power link line GCL, the resistance of the plate-shaped gated power supply unit GPSa may be lower than that of the gated power link line GCL. Therefore, the degree of IR drop of the gate drive voltage can be reduced. Therefore, by configuring the gate power supply unit GPSa in a plate shape, the gate driving voltage can reach the target voltage.

As described above, the first gate clock voltage may be charged in the first sub-gate power supply unit GPSa1, the second gate clock voltage may be charged in the second sub-gate power supply unit GPSa2, the low potential driving voltage may be charged in the third sub-gate power supply unit GPSa3, and the high potential gate driving voltage may be charged in the fourth sub-gate power supply unit GPSa 4.

In addition, the first sub-gate power supply unit GPSa1 may supply the first gate clock voltage to the gate driver GD through the third power supply line PSL 3. Specifically, the first sub-gate power supply unit GPSa1 may be electrically connected to the third power supply line PSL3 through a contact hole, and the third power supply line PSL3 may be electrically connected to the gate driver GD through a contact hole. Accordingly, the first gate clock voltage charged in the first sub-gate power supply unit GPSa1 may be supplied to the gate driver GD.

In addition, the second sub-gate power supply unit GPSa2 may supply the second gate clock voltage to the gate driver GD through the fourth power supply line PSL 4. Specifically, the second sub-gate power supply unit GPSa2 may be electrically connected to the fourth power supply line PSL4 through a contact hole, and the fourth power supply line PSL4 may be electrically connected to the gate driver GD through a contact hole. Accordingly, the second gate clock voltage charged in the second sub-gate power supply unit GPSa2 may be supplied to the gate driver GD.

In addition, the third sub-gate power supply unit GPSa3 may supply a low potential gate driving voltage to the gate driver GD through the fifth power supply line PSL 5. Specifically, the third sub-gate power supply unit GPSa3 may be electrically connected to the fifth power supply line PSL5 through a contact hole, and the fifth power supply line PSL5 may be electrically connected to the gate driver GD through a contact hole. Accordingly, the low-potential gate driving voltage charged in the third sub-gate power supply unit GPSa3 may be supplied to the gate driver GD.

In addition, the fourth sub-gate power supply unit GPSa4 may supply the fourth gate clock voltage to the gate driver GD through the sixth power supply line PSL 6. Specifically, the fourth sub-gate power supply unit GPSa4 may be electrically connected to the sixth power supply line PSL6 through a contact hole, and the sixth power supply line PSL6 may be electrically connected to the gate driver GD through a contact hole. Accordingly, the high-potential gate driving voltage charged in the fourth sub-gate power supply unit GPSa4 may be supplied to the gate driver GD.

Meanwhile, the gate driver GD may output a gate voltage to the gate output line GOL and apply the gate voltage to another gate driver GD of a next stage. Specifically, the gate driver GD may be electrically connected to the seventh power line PSL7 through a contact hole, and the seventh power line PSL7 may be electrically connected to the gate output line GOL. Accordingly, the gate voltage output from the gate driver GD may be applied to another gate driver GD of a next stage.

Referring to fig. 5A and 6, the connection support 120 may be disposed under the plurality of pixel power connection lines PCL, the plurality of gate power connection lines GCL, and the gate output line GOL.

In addition, the connection support 120 may have the same shape as that of the plurality of pixel power connection lines PCL, the plurality of gate power connection lines GCL, and the gate output lines GOL.

Therefore, the plurality of connection supports 120 also have their curved shapes. For example, as shown in fig. 5A, the plurality of connection supporters 120 may have a sine wave shape. However, the shape of the plurality of connection supports 120 is not limited thereto. The plurality of connection supports 120 may be shaped differently. For example, the plurality of connection struts 120 may extend in a zigzag manner, or the plurality of diamond-shaped connection struts 120 may extend by being connected to each other at the vertexes thereof.

As described above, the connection supports 120 are disposed under the plurality of pixel power connection lines PCL, the plurality of gate power connection lines GCL, and the gate output lines GOL, so that the stretching stress received by the plurality of pixel power connection lines PCL, the plurality of gate power connection lines GCL, and the gate output lines GOL when the scalable display device 100 is stretched can be reduced. Accordingly, even if the expansion and contraction of the scalable display device 100 are repeated, cracks do not occur in the plurality of pixel power connection lines PCL, the plurality of gate power connection lines GCL, and the gate output lines GOL, so that the pixel driving voltage, the gate clock voltage, and the gate driving voltage can be stably supplied.

In addition, referring to fig. 5B, in some embodiments, a connection support may be disposed between the plurality of gate drivers GD.

That is, the connection supporter 120 may be disposed in all regions between the plurality of outer substrates 121. Accordingly, the connection supporter 120 may be uniformly disposed between the plurality of outer substrates 121.

Accordingly, the collapsible display device 100 according to the exemplary embodiment of the present disclosure can disperse the collapsing stress by uniformly disposing the connection supporter 120 between the plurality of outer substrates 121. As a result, it is possible to prevent the occurrence of cracks during the expansion and contraction of the retractable display apparatus 100.

Hereinafter, with reference to fig. 6, the stacking relationship and the connection relationship of the plurality of power supply lines and the power supply unit will be described.

Referring to fig. 6, an outer substrate 121 and a connection supporter are disposed on the lower substrate.

Both the outer substrate 121 and the connection supporter 120 may be formed of the same material and by the same process.

That is, each of the outer substrate 121 and the connection support 120 may be formed of a plastic material having flexibility, such as Polyimide (PI), polyacrylate, polyacetate, etc. However, it is not limited thereto, and may be formed of other materials.

In addition, the buffer layer 112 may be disposed on the outer substrate 121. The buffer layer 112 may be formed of an insulating material and may be composed of a single layer or a plurality of layers of an inorganic layer formed of, for example, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or the like. However, the buffer layer 112 may be omitted depending on the structure or characteristics of the scalable display device 100.

A plurality of power supply lines PSL1 through PSL7 may be formed on the buffer layer 112. For example, as illustrated in fig. 6, the sixth and seventh power supply lines PSL6 and PSL7 may be disposed on the buffer layer 112. The sixth and seventh power supply lines PSL6 and PSL7 are disposed to be spaced apart on the same layer as the source and drain

electrodes

153 and 154. In addition, the plurality of power lines PSL1 to PSL7 may be formed of the same material as the source and drain

electrodes

153 and 154. That is, the plurality of power supply lines PSL1 to PSL7 may be formed of any one of various metal materials, such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of two or more thereof, or a multi-layer thereof, but are not limited thereto.

In some embodiments, the plurality of power supply lines PSL1 to PSL7 may be spaced apart from the gate electrode 151 and formed of the same material as the gate electrode 151.

Then, the planarization layer 115 is formed on the plurality of power supply lines PSL1 to PSL 7. The planarization layer 115 planarizes an upper portion of the driving transistor 150. The planarization layer 115 may be composed of a single layer or a plurality of layers, and may be formed of an organic material. Accordingly, the planarization layer 115 may be referred to as an organic insulating layer. For example, the planarization layer 115 may be formed of an acrylic organic material, but is not limited thereto.

In addition, the gate output line GOL, the plurality of gate power connection lines GCL, and the plurality of pixel power connection lines GCL may be disposed on the connection support 120. For example, as illustrated in fig. 6, the fourth sub-gate power connection line GCL4 may be disposed on the connection support 120.

In addition, the gate power supply unit GPSa and the pixel power supply unit PPS may be disposed on the planarization layer 115. For example, as illustrated in fig. 6, the fourth sub-gate power supply unit GPSa4 may be disposed on the planarization layer 115.

In addition, the gate power supply unit GPSa and the pixel power supply unit PPS may be formed of the same material as the gate output line GOL, the plurality of gate power connection lines GCL, and the plurality of pixel power connection lines PCL and may be electrically connected thereto. In addition, the gate power supply unit GPSa and the pixel power supply unit PPS may be electrically connected to the plurality of power supply lines PSL1 to PSL7 through contact holes.

For example, as illustrated in fig. 6, the fourth sub-gate power connection line GCL4 is formed of the same material as the fourth sub-gate power supply unit GPSa4 and may be electrically connected thereto. In addition, the fourth sub-gate power supply unit GPSa4 may be electrically connected to the sixth power supply line PSL6 through a contact hole. Accordingly, the high-potential gate driving voltage charged in the fourth sub-gate power supply unit GPSa4 may be supplied to the gate driver GD.

As described above, in the scalable display device 100 according to the exemplary embodiment of the present disclosure, the gate driver GD and the power supply unit PS are disposed on the outer substrates 121, and the gate output line GOL, the gate power connection line GCL, and the pixel power supply line PSL are disposed between the outer substrates 121.

Accordingly, each of the plurality of gate drivers GD outputs a gate voltage to the plurality of pixels PX disposed on the same line, and the plurality of power supply units PS outputs a pixel driving voltage to the plurality of pixels PX.

That is, the scalable display device 100 according to the exemplary embodiment of the present disclosure includes the gate driver GD and the power supply unit PS that are scalable to thereby drive the plurality of pixels PX.

Hereinafter, a retractable display device according to another exemplary embodiment of the present disclosure will be described. A scalable display apparatus according to another exemplary embodiment of the present disclosure is different from the scalable display apparatus according to the exemplary embodiment of the present disclosure only in an overlapping relationship of the gate driver GD and the power supply unit PS. Also, the scalable display device according to another exemplary embodiment of the present disclosure is the same as the scalable display device according to the exemplary embodiment of the present disclosure in terms of technical characteristics of the gate output line GOL, the gate power connection line GCL, and the pixel power supply line PSL. Therefore, an overlapping relationship of the gate driver GD and the power supply unit PS of the scalable display device according to another embodiment of the present disclosure will be described in detail below.

< overlapped gate driver and power supply unit >

Fig. 7 is an enlarged plan view of a non-display area of a scalable display device according to another exemplary embodiment of the present disclosure. Fig. 8 is a sectional view taken along line VIII-VIII' of fig. 7. Fig. 9 is a sectional view taken along line IX-IX' of fig. 7.

In the scalable display device 200 according to another exemplary embodiment of the present disclosure, the power supply unit PS and the gate driver GD may overlap.

As illustrated in fig. 7, the gate power supply unit GPSb of the power supply unit PS may overlap the gate driver GD. In addition, the gate power supply unit GPSb may be built in the gate driver GD.

Specifically, the gated power supply unit GPSb may include: a first sub-gate power supply unit GPSb1 for applying a first gate clock voltage to the gate driver GD; a second sub-gate power supply unit GPSb2 for applying a second gate clock voltage to the gate driver GD; a third sub-gate power supply unit GPSb3 for applying a low-potential gate driving voltage to the gate driver GD; and a fourth sub-gate power supply unit GPSb4 for applying a high-potential gate driving voltage to the plurality of gate drivers GD.

In addition, each of the first, second, third, and fourth sub-gate power supply units GPSb1, GPSb2, GPSb3, and GPSb4 may be differently formed such that they are electrically connected to the gate power link line GCL and to the gate driver GD.

For this, in fig. 7, each of the first, second, third, and fourth sub-gate power supply units GPSb1, GPSb2, GPSb3, and GPSb4 may be divided into a portion overlapping the gate power connection line GCL and a portion overlapping the gate driver GD.

For example, referring to fig. 7 and 8, the first sub-gate power supply unit GPSb1 may be electrically connected to the first sub-gate power connection line GCL1 through a plurality of contact holes located at both sides thereof in the Y-axis direction. Accordingly, the first sub-gated power supply unit GPSb1 receives the first gated clock voltage through the first sub-gated power link GCL1 or supplies the first gated clock voltage to another first sub-gated power supply unit GPSb1 through the first sub-gated power link GCL 1.

In addition, the first sub-gate power supply unit GPSb1 may be connected to the gate driver GD through a contact hole. Accordingly, the first gate clock voltage charged in the first sub-gate power supply unit GPSb1 may be supplied to the gate driver GD.

In the same manner, the second sub-gate power supply unit GPSb2 may be electrically connected to the second sub-gate power connection line GCL2 through a plurality of contact holes located at both sides thereof in the Y-axis direction. Accordingly, the second sub-gated power supply unit GPSb2 receives the second gated clock voltage through the second sub-gated power link GCL2 or supplies the second gated clock voltage to another second sub-gated power supply unit GPSb2 through the second sub-gated power link GCL 2.

In addition, the second sub-gate power supply unit GPSb2 may be connected to the gate driver GD through a contact hole. Accordingly, the second gate clock voltage charged in the second sub-gate power supply unit GPSb2 may be supplied to the gate driver GD.

In the same manner, the third sub-gate power supply unit GPSb3 may be electrically connected to the third sub-gate power link line GCL3 through a plurality of contact holes located at both sides thereof in the Y-axis direction. Accordingly, the third sub-gate power supply unit GPSb3 receives the low potential gate driving voltage through the third sub-gate power link GCL3 or supplies the low potential gate driving voltage to another third sub-gate power supply unit GPSb3 through the third sub-gate power link GCL 3.

In addition, the third sub-gate power supply unit GPSb3 may be connected to the gate driver GD through a contact hole. Accordingly, the low-potential gate driving voltage charged in the third sub-gate power supply unit GPSb3 may be supplied to the gate driver GD.

In the same manner, the fourth sub-gate power supply unit GPSb4 may be electrically connected to the fourth sub-gate power connection line GCL4 through a plurality of contact holes located at both sides thereof in the Y-axis direction. Accordingly, the fourth sub-gate power supply unit GPSb4 receives the high-potential gate driving voltage through the fourth sub-gate power link GCL4 or supplies the high-potential gate driving voltage to another fourth sub-gate power supply unit GPSb4 through the fourth sub-gate power link GCL 4.

In addition, the fourth sub-gate power supply unit GPSb4 may be connected to the gate driver GD through a contact hole. Accordingly, the high-potential gate driving voltage charged in the fourth sub-gate power supply unit GPSb4 may be supplied to the gate driver GD.

In addition, each of the first, second, third, and fourth sub-gate power supply units GPSb1, GPSb2, GPSb3, and GPSb4 may be formed of the same material as the source and drain

electrodes

153 and 154. That is, each of the first, second, third, and fourth sub-gate power supply units GPSb1, GPSb2, GPSb3, and GPSb4 may be formed of any one of various metal materials, or a multi-layer thereof, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of two or more thereof, but is not limited thereto.

In some embodiments, each of the first, second, third, and fourth sub-gate power supply units GPSb1, GPSb2, GPSb3, and GPSb4 may be disposed on the same layer as the gate 151 to be spaced apart from the gate 151, and may be formed of the same material as the gate 151.

As described above, the power supply unit PS and the gate driver GD may overlap each other. Accordingly, the size of the non-display area NA in which the power supply unit PS and the gate driver GD are disposed may be reduced. Therefore, in the scalable display device 200 according to another embodiment of the present disclosure, the size of the bezel area may be reduced, so that the size of the display area displaying an image may be relatively increased.

Next, referring to fig. 7 and 9, the first sub-pixel power supply unit PPS1 may supply the low potential pixel driving voltage to the second sub-pixel connection line 181b as the low potential pixel driving voltage line through the contact portion CTP. The contact portion CTP may be formed on a different layer from the pixel power supply unit PPS and may overlap the pixel power supply unit PPS. Specifically, the first sub-pixel power supply unit PPS1 may be electrically connected to the contact portion CTP through a plurality of contact holes, and the contact portion CTP may be connected to the second sub-pixel connection line 181b through another contact hole. Accordingly, the low-potential pixel driving voltage charged in the first sub-pixel power supply unit PPS1 may be transferred to the second sub-pixel connection line 181b and supplied to the plurality of pixels PX. That is, the first sub-pixel power supply unit PPS1 and the second sub-pixel connection line 181b may be connected to each other in a skip structure through the contact portion CTP.

The contact portion CTP formed on the outer substrate 121 as a rigid substrate may be arranged in a plate shape. Also, as shown in fig. 9, the width of the plate-shaped contact portion CTP may be greater than the sum of the width of the first sub-pixel power supply unit PPS1 and the width of the second sub-pixel power supply unit PPS 2. Therefore, the resistance of the plate-like contact portion CTP may be relatively low. Therefore, the degree of occurrence of IR drop of the pixel drive voltage can be reduced. Therefore, by arranging the contact portion CTP in a plate shape, the pixel driving voltage can reach the target voltage, so that the plurality of pixels PX can normally realize the gray scale.

In addition, fig. 7 and 9 illustrate that the contact portion CTP is formed of the same material as the source and drain

electrodes

153 and 154 and is formed on the same layer as the source and drain

electrodes

153 and 154. However, the present disclosure is not limited thereto. The contact portion CTP may be disposed on the same layer as the gate electrode 151 to be spaced apart therefrom, and may be formed of the same material as the gate electrode 151.

Hereinafter, a retractable display device according to still another exemplary embodiment of the present disclosure will be described. In the retractable display apparatus according to still another exemplary embodiment of the present disclosure, only the first and second barrier layers are added as compared with the retractable display apparatus according to the exemplary embodiment and another exemplary embodiment of the present disclosure, and technical characteristics of the gate driver GD are the same. Accordingly, hereinafter, the first barrier layer and the second barrier layer of the retractable display device according to still another exemplary embodiment of the present disclosure will be described in detail.

< first Barrier layer and second Barrier layer >

Fig. 10 is a cross-sectional view of a non-display area of a retractable display device according to another exemplary embodiment of the present disclosure.

The scalable display device 300 according to still another exemplary embodiment of the present disclosure may include a first barrier layer BL1 and a second barrier layer BL2 overlapping the gate driver GD. Accordingly, the first and second barrier layers BL1 and BL2 may protect various circuit components constituting one stage of the gate driver GD.

The various circuit components constituting one stage of the gate driver GD may be representatively a gate transistor 390. The gate transistor 390 may include a gate electrode 391, an active layer 392, a source electrode 393, and a drain electrode 394. Accordingly, the gating transistor 390 may output a gating voltage. Gating transistor 390 may also be referred to as a buffer transistor that outputs the gating voltage.

Also, the gate 391, the active layer 392, the source 393, and the drain 394 of the gate transistor 390 may be formed on the same layer as the gate 151, the active layer 152, the source 153, and the drain 154 of the driving transistor 150 described in fig. 3.

That is, the buffer layer 112 is disposed on the outer substrate 121 in the scalable display device 300 according to still another exemplary embodiment of the present disclosure. Then, the active layer 152 of the driving transistor 150 and the active layer 392 of the gate transistor 390 are disposed on the buffer layer 112. Then, the gate insulating layer 113 is disposed on the active layer 152 of the driving transistor 150 and the active layer 392 of the gate transistor 390. The gate 151 of the driving transistor 150 and the gate 391 of the gate transistor 390 are disposed on the gate insulating layer 113. In addition, an interlayer insulating layer 114 is disposed on the gate electrode 151 of the driving transistor 150 and the gate electrode 391 of the gate transistor 390. In addition, the source 153 and the drain 154 of the driving transistor 150 and the source 393 and the drain 394 of the gate transistor 390 are disposed on the interlayer insulating layer 114. The planarization layer 115 may be disposed to cover the source 153 and the drain 154 of the driving transistor 150 and the source 393 and the drain 394 of the gate transistor 390. In addition, a second sub-pixel connection line 181b to which a low-potential pixel driving voltage is applied and a third sub-pixel connection line 181c to which a high-potential pixel driving voltage is applied may be disposed on the planarization layer 115. In addition, the cover insulating layer 117 may be disposed to cover the second and third

sub-pixel connection lines

181b and 181 c.

The above-described cover insulating layer 117 may serve to insulate the second and third

sub-pixel connection lines

181b and 181c from the outside, so that the low and high potential pixel driving voltages can be applied to the second and third

sub-pixel connection lines

181b and 181c, respectively.

Accordingly, the cover insulating layer 117 may be formed of an insulating material, and for example, may be composed of a single layer or a plurality of layers of an inorganic layer formed of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or the like.

The first barrier layer BL1 is disposed under the gate driver GD to protect the gate transistor 390 of the gate driver GD.

The first barrier layer BL1 may be disposed between the lower substrate 110a and the outer substrate 121. In addition, the first blocking layer BL1 may overlap the gate transistor 390. Fig. 10 illustrates that the first barrier layer BL1 is disposed in the entire region between the lower substrate 110a and the outer substrate 121 so as to overlap the gate transistor 390, but the present disclosure is not limited thereto. If necessary, the first barrier layer BL1 may be patterned to overlap the gate transistor 390.

The first barrier BL1 may be formed of a material having a resistivity of 10^ (12) omega/m²Or a metal of greater surface resistance for electrostatic shielding. Specifically, the first barrier layer BL1 may be composed of a metal material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), gold (Au), and silver (Ag), or a stacked structure of metal materials such as copper/molybdenum titanium (Cu/Moti), titanium/aluminum/titanium (Ti/Al/Ti), and the like, but is not limited thereto. The first barrier layer BL1 may be formed of a transparent conductive oxide such as Indium Tin Oxide (ITO).

In addition, the first barrier layer BL1 may be electrically connected to a pixel connection line that supplies a constant voltage for effective discharge effect. That is, the first barrier layer BL1 may be connected to the second sub-pixel connection line 181b to which the low-potential pixel driving voltage is applied or the third sub-pixel connection line 181c to which the high-potential pixel driving voltage is applied.

Fig. 10 illustrates that the first barrier layer BL1 is connected to the third sub-pixel connection line 181c through a contact hole passing through the outer substrate 121, the buffer layer 112, the gate insulating layer 113, the interlayer insulating layer 114, and the planarization layer 115. Therefore, a high potential pixel driving voltage may be fixedly applied to the first barrier layer BL 1.

However, the present disclosure is not limited thereto, and the first barrier layer BL1 may be connected to the second sub-pixel connection line 181b through a contact hole passing through the outer substrate 121, the buffer layer 112, the gate insulating layer 113, the interlayer insulating layer 114, and the planarization layer 115.

A second barrier layer BL2 is disposed over the gate driver GD to protect the gate transistor 390 of the gate driver GD.

The second barrier layer BL2 may be disposed between the upper substrate 110b and the cap insulating layer 117. In addition, the second barrier layer BL2 may overlap the gate transistor 390. Fig. 10 illustrates that the second barrier layer BL2 is disposed in the entire region between the upper substrate 110b and the capping insulating layer 117 so as to overlap the gate transistor 390, but the present disclosure is not limited thereto. If necessary, the second barrier layer BL2 may be patterned to overlap the gate transistor 390.

The second barrier BL2 may also be formed of a material having a resistivity of 10^ (12) omega/m²Or a metal of greater surface resistance for electrostatic shielding. Specifically, the second barrier layer BL2 may be composed of a metal material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), gold (Au), and silver (Ag), or a stacked structure of metal materials such as copper/molybdenum titanium (Cu/Moti), titanium/aluminum/titanium (Ti/Al/Ti), and the like, but is not limited thereto. The second barrier layer BL2 may also be formed of a transparent conductive oxide such as Indium Tin Oxide (ITO).

In addition, the second barrier layer BL2 may be electrically connected to a pixel connection line that supplies a constant voltage for an effective discharge effect. That is, the second barrier layer BL2 may be connected to the second sub-pixel connection line 181b to which the low-potential pixel driving voltage is applied or the third sub-pixel connection line 181c to which the high-potential pixel driving voltage is applied.

Fig. 10 illustrates that the second barrier layer BL2 is connected to the second sub-pixel connection line 181b through a contact hole passing through the cover insulating layer 117. Accordingly, a low potential pixel driving voltage may be fixedly applied to the second barrier layer BL 2.

However, the present disclosure is not limited thereto, and the second barrier layer BL2 may be connected to the third sub-pixel connection line 181c through a contact hole passing through the cover insulating layer 117.

In the scalable display device 300 according to still another exemplary embodiment of the present disclosure, the first barrier layer BL1 and the second barrier layer BL2 are illustrated to overlap the gate transistor 390. However, the present disclosure is not limited thereto, and the first and second barrier layers BL1 and BL2 may be disposed to overlap the driving transistor 150 disposed in the display area AA.

Fig. 11 is a diagram illustrating a relationship between a gate voltage and a drain current of a gate transistor of a scalable display device according to still another embodiment of the present disclosure.

Specifically, the reference example shows the relationship between the gate voltage and the drain current of the gate transistor in the case where static electricity does not cause damage. The comparative example shows the relationship between the gate voltage and the drain current of the gate transistor in the case where damage is caused by static electricity. The inventive example of the present disclosure shows a relationship between a gate voltage and a drain current of the gating transistor 390 according to still another exemplary embodiment of the present disclosure.

As shown in the reference example, the drain current was reduced to about 10 at a gate voltage of 0V without causing damage by static electricity^-12A, enabling the gating transistor to be turned off. That is, in the reference example, the gate transistor can be turned off at a threshold voltage of 0V.

However, when the retractable display device is repeatedly retracted and extended, static electricity may be generated due to contact and separation between the retracted lower substrate and components disposed on the lower substrate. Otherwise, static electricity may be generated by friction with an external object. Static electricity generated through such a process as described above is introduced into the gate transistor of the scalable display device, thereby interrupting normal driving.

That is, as can be seen in the comparative example, static electricity is introduced into the active layer of the gate transistor, thereby forming an undesired channel. Therefore, the drain current of the gate transistor cannot be reduced to about 10^-12A, can be reduced to about 10^-7A, so that the gating transistor cannot be turned off. As a result, in the comparative example, a problem occurs in that the gate driver cannot normally operate due to static electricity.

Accordingly, the scalable display device 300 according to still another exemplary embodiment of the present disclosure includes the first and second barrier layers BL1 and BL2 overlapping the gate driver GD, and the first and second barrier layers BL1 and BL2 are electrically connected to a pixel connection line supplying a constant voltage. Accordingly, static electricity introduced from each of upper and lower portions of the gate driver GD may be blocked by the first and second blocking layers BL1 and BL 2. In addition, static electricity introduced into the first and second barrier layers BL1 and BL2 may be discharged to the second or third

sub-pixel connection line

181b or 181 c.

As a result, in the scalable display device 300 according to still another exemplary embodiment of the present disclosure, the drain current of the gate transistor 390 is reduced to about 10^-12A, enabling the gating transistor to be turned off.

Accordingly, the gate driver GD of the scalable display apparatus 300 according to still another exemplary embodiment of the present disclosure may normally operate. That is, the retractable display apparatus 300 according to still another exemplary embodiment of the present disclosure can be designed to be resistant to external static electricity.

Exemplary embodiments of the present disclosure can also be described as follows:

The at least one barrier layer may include: a first blocking layer disposed under the gate driver; and a second blocking layer disposed over the gate driver.

The first barrier layer may be formed of a metal or a transparent conductive oxide.

The first barrier layer may be disposed between the lower substrate and the outer substrate.

The second barrier layer may be formed of a metal or a transparent conductive oxide.

The scalable display device may further include: a second sub-pixel connection line supplying a low-potential pixel driving voltage to each of the plurality of pixels; and a third sub-pixel connection line supplying a high-potential pixel driving voltage to each of the plurality of pixels.

The second sub-pixel link line and the third sub-pixel link line may be disposed on the gate driver.

The scalable display device may further include: a cover insulating layer covering the second sub-pixel connection line and the third sub-pixel connection line.

The scalable display device may further include: an upper substrate facing the lower substrate, and the second barrier layer may be disposed between the cover insulating layer and the upper substrate.

Each of the first and second blocking layers may be electrically connected to the second sub-pixel connection line or the third sub-pixel connection line.

According to another aspect of the present disclosure, a scalable display device includes: a stretchable substrate on which a display area displaying an image and a non-display area adjacent to the display area are provided; a plurality of first rigid substrates disposed in the display area; a plurality of second rigid substrates disposed in the non-display area; a plurality of pixels disposed on the plurality of first rigid substrates; a plurality of gate drivers disposed on the plurality of second rigid substrates and including at least one gate transistor; and a plurality of blocking layers, the at least one blocking layer being disposed above and below the at least one gate transistor to prevent introduction of external static electricity. Therefore, it is possible to prevent the gate driver of the scalable display device from being damaged by external static electricity.

The plurality of barrier layers may further include: a first blocking layer disposed under the gate transistor; and a second blocking layer disposed over the gate transistor.

The scalable display device may further include: at least one pixel connection line supplying a constant voltage to each of the plurality of pixels.

Each of the plurality of barrier layers may be electrically connected to the at least one pixel connection line.

The plurality of barrier layers may be formed of a metal or a transparent conductive oxide.

Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and may be embodied in many different forms without departing from the technical concept of the present disclosure. Accordingly, the exemplary embodiments of the present disclosure are provided only for illustrative purposes, and are not intended to limit the technical concept of the present disclosure. The scope of the technical idea of the present disclosure is not limited thereto. Therefore, it should be understood that the above-described exemplary embodiments are illustrative in all respects, not restrictive of the disclosure. The scope of the present disclosure should be construed based on the following claims, and all technical ideas within the equivalent scope thereof should be construed to fall within the scope of the present disclosure.

Claims

1. A scalable display device, the scalable display device comprising:

a lower substrate on which a display region displaying an image and a non-display region adjacent to the display region are disposed;

a plurality of pixel substrates disposed in the display region;

a plurality of outer substrates disposed in the non-display region;

a plurality of pixels disposed on the plurality of pixel substrates;

a plurality of gate drivers disposed on the plurality of outer substrates and outputting gate voltages to the plurality of pixels; and

at least one blocking layer at least partially overlapping the plurality of gate drivers.

2. The retractable display device of claim 1, wherein the at least one barrier layer comprises:

a first blocking layer disposed under the gate driver; and

a second blocking layer disposed over the gate driver.

3. The scalable display device of claim 2, wherein the first barrier layer is formed of a metal or a transparent conductive oxide.

4. The retractable display device of claim 2, wherein the first barrier layer is disposed between the lower substrate and the outer substrate.

5. The scalable display device of claim 2, wherein the second barrier layer is formed of a metal or a transparent conductive oxide.

6. The retractable display apparatus of claim 2, further comprising:

a second sub-pixel connection line supplying a low-potential pixel driving voltage to each of the plurality of pixels; and

a third sub-pixel connection line supplying a high potential pixel driving voltage to each of the plurality of pixels.

7. The scalable display device of claim 6, wherein the second and third sub-pixel connecting lines are disposed on the gate driver.

8. The retractable display apparatus of claim 7, further comprising:

a cover insulating layer covering the second sub-pixel connection line and the third sub-pixel connection line.

9. The retractable display device of claim 8, further comprising:

an upper substrate facing the lower substrate,

wherein the second barrier layer is disposed between the cover insulating layer and the upper substrate.

10. The scalable display device of claim 6, wherein each of the first and second barrier layers is electrically connected to the second or third sub-pixel connection line.

11. A scalable display device, the scalable display device comprising:

a stretchable substrate on which a display area displaying an image and a non-display area adjacent to the display area are disposed;

a plurality of first rigid substrates disposed in the display area;

a plurality of second rigid substrates disposed in the non-display area;

a plurality of pixels disposed on the plurality of first rigid substrates;

a plurality of gate drivers disposed on the plurality of second rigid substrates and including at least one gate transistor; and

a plurality of blocking layers disposed above and below the at least one gate transistor to prevent introduction of external static electricity.

12. The retractable display device of claim 11, further comprising:

a first blocking layer disposed below the gate transistor; and

a second blocking layer disposed over the gate transistor.

13. The retractable display device of claim 11, further comprising:

at least one pixel connection line supplying a constant voltage to each of the plurality of pixels,

wherein each of the plurality of barrier layers is electrically connected to the at least one pixel connection line.

14. The scalable display device of claim 11, wherein each of the plurality of barrier layers is formed of a metal or a transparent conductive oxide.