CN112992841A - Circuit substrate - Google Patents

Circuit substrate Download PDF

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Publication number
CN112992841A
CN112992841A CN202010096556.0A CN202010096556A CN112992841A CN 112992841 A CN112992841 A CN 112992841A CN 202010096556 A CN202010096556 A CN 202010096556A CN 112992841 A CN112992841 A CN 112992841A
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CN
China
Prior art keywords
substrate
patterned
contact opening
layer
circuit substrate
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Pending
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CN202010096556.0A
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Chinese (zh)
Inventor
杨凯铭
林晨浩
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Unimicron Technology Corp
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Unimicron Technology Corp
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Publication of CN112992841A publication Critical patent/CN112992841A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention provides a circuit substrate which comprises a substrate, a circuit layer-adding structure and an insulating layer. The substrate has a first surface and a second surface opposite to the first surface. The substrate comprises a plurality of patterned connecting pads. The patterned pad is disposed on the first surface of the substrate and has a contact opening. The line build-up structure is arranged on the first surface of the substrate. The line build-up structure includes an interconnect stack and a plurality of conductive pillars. The conductive post is electrically connected with the interconnection lamination layer and the patterned connecting pad. The insulating layer is arranged between the substrate and the line build-up structure.

Description

Circuit substrate
Technical Field
The present disclosure relates to circuit boards, and particularly to a circuit board.
Background
With the development of semiconductor packaging technology, semiconductor devices (semiconductor devices) have been developed with different packaging types, such as: wire bonding, flip chip, or hybrid (i.e., flip-chip-wire bonding).
The above-mentioned bonding technique using solder balls or bumps uses solder for bonding, but the bonding surface is easily separated due to fatigue over a long period of time, the solder balls are easily defective during the manufacturing process, which affects the reliability, and the resistance of the joint is high.
Disclosure of Invention
The present invention is directed to a circuit board which is suitable for low-temperature bonding and assembly, and has excellent bonding reliability and bonding quality and excellent electrical characteristics.
According to an embodiment of the invention, the circuit substrate comprises a substrate, a circuit build-up structure and an insulating layer. The substrate has a first surface and a second surface opposite to the first surface. The substrate comprises a plurality of patterned connecting pads arranged on the first surface of the substrate, and each patterned connecting pad is provided with a contact opening. The circuit build-up structure is arranged on the first surface of the substrate and comprises an interconnection lamination and a plurality of conductive columns. The conductive posts are electrically connected with the interconnection lamination layer and the patterned connecting pads. The insulating layer is arranged between the substrate and the line build-up structure.
In the circuit substrate according to the embodiment of the invention, each conductive pillar is abutted against each contact opening correspondingly.
In the circuit substrate according to an embodiment of the invention, the wall surface of the contact opening is an inclined surface, and an aperture of the contact opening away from the first surface is larger than an aperture of the contact opening adjacent to the first surface.
In the circuit substrate according to an embodiment of the invention, each of the patterned pads further includes a patterned metal layer, the contact opening is disposed on the patterned metal layer, and a depth of the contact opening is smaller than a thickness of the patterned metal layer.
In the circuit substrate according to an embodiment of the invention, each of the patterned pads further includes a patterned metal layer, and the contact opening is disposed on the patterned metal layer, and penetrates through a thickness of the patterned metal layer and exposes the first surface of the substrate.
In the circuit substrate according to the embodiment of the invention, each conductive pillar correspondingly abuts against each contact opening and contacts the first surface.
In an embodiment of the circuit substrate, the circuit substrate further includes a plurality of etching stop layers disposed on the first surface, each of the patterned pads is disposed corresponding to each of the etching stop layers, and each of the etching stop layers is located between each of the patterned pads and the substrate.
In the circuit substrate according to an embodiment of the invention, each of the patterned pads further includes a patterned metal layer, and the contact opening is disposed on the patterned metal layer, and penetrates through a thickness of the patterned metal layer and exposes the etching stop layer.
In the circuit substrate according to the embodiment of the invention, each conductive pillar correspondingly abuts against each contact opening and contacts the etching stop layer.
In the circuit substrate according to the embodiment of the invention, the insulating layer surrounds the conductive pillars and fills the gaps between the conductive pillars, and the insulating layer covers the patterned pads.
Based on the above, since the circuit substrate of the present invention can directly fabricate the contact opening on the patterned pad, an additional dielectric layer can be omitted to simplify the process and reduce the cost. In addition, because a stress concentration point is generated between the conductive pillar and the wall surface of the contact opening, the pressing temperature can be effectively reduced, and the force required by bonding can be reduced. Therefore, the invention can meet the requirement of copper to copper butt joint, is suitable for reducing the requirement of the manufacturing process and the manufacturing cost, improves the combination reliability and the combination quality of the conductive post and the patterned connecting pad, and has excellent electrical characteristics so as to improve the signal transmission speed and the signal transmission quality of the circuit substrate. In addition, the insulating layer arranged between the substrate and the circuit layer-adding structure can not only improve the bonding force, but also protect the conductive posts and the patterned pads from being affected by moisture in the environment, and has good elasticity and flexibility, so that the impact resistance of the circuit substrate can be improved by absorbing stress, and the bonding reliability and the bonding quality of the circuit substrate can be further improved.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
Fig. 1A to fig. 1D are schematic cross-sectional views illustrating a manufacturing process of a circuit substrate according to an embodiment of the invention;
FIG. 2 is a schematic cross-sectional view of a circuit substrate according to another embodiment of the present invention;
fig. 3 is a schematic cross-sectional view of a circuit substrate according to still another embodiment of the invention.
Description of the reference numerals
10. 10A, 10B: a circuit substrate;
100: a line layer-adding structure;
110: a carrier plate;
120: an interconnect stack;
122: patterning the interconnect;
124: a dielectric layer;
140: a conductive post;
160: an insulating layer;
200. 200A, 200B: a substrate;
220: an outer dielectric layer;
221: a first surface;
222: a second surface;
224: a via hole;
240. 240A, 240B: patterning the connecting pad;
242. 242A, 242B: patterning the metal layer;
244. 244A, 244B: a contact opening;
260: a contact point;
280: an etch stop layer;
d: depth;
h1, H2: thickness;
l: a length;
w: width.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Some embodiments are listed below and described in detail with reference to the attached drawings, but the embodiments are not provided to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, like elements in the following description will be described with like reference numerals.
The terms "first", "second", etc. used herein do not denote any order or order, but rather are used to distinguish one element from another.
Furthermore, as used herein, the terms "comprising," "including," "having," and the like are open-ended terms; that is, including but not limited to.
Furthermore, as used herein, the terms "contacting," "joining," and the like, unless otherwise specified, may refer to direct contact or indirect contact through other layers.
Fig. 1A to fig. 1D are schematic cross-sectional views illustrating a manufacturing process of a circuit substrate according to an embodiment of the invention. Referring to fig. 1D, fig. 1D is a schematic cross-sectional view of a circuit substrate 10 according to an embodiment of the invention. The circuit substrate 10 includes a substrate 200, a circuit build-up structure 100, and an insulating layer 160 disposed between the substrate 200 and the circuit build-up structure 100. In the present embodiment, a plurality of conductive pillars 140 are disposed on the line build-up structure 100, and the conductive pillars 140 are electrically connected to a plurality of patterned pads 240 on the substrate 200. Thereby, the reliability and quality of the bonding between the substrate 200 and the build-up structure 100 can be improved, and the circuit substrate 10 has excellent electrical characteristics. The manufacturing process of the circuit substrate 10 will be briefly described below with an embodiment.
Referring to fig. 1A, fig. 1A is a schematic cross-sectional view of a line build-up structure 100 according to the present invention. First, a carrier 110 is provided. The material of the carrier plate 110 may include glass, ceramic, polymer material or silicon. For example, the material of the carrier plate 110 may be polysilicon (Poly-Silicon), Silicon carbide (SiC), Graphene (Graphene), Aluminum Nitride (AlN), or other suitable materials, but the invention is not limited thereto.
Next, a multi-layer interconnect 122 and a multi-layer dielectric layer 124 are formed on the carrier substrate 110. In some embodiments, before the step of forming the interconnect 122 and the dielectric layer 124, a release film may be formed on the carrier substrate 110, and then the interconnect 122 and the dielectric layer 124 may be formed on the release film.
In the present embodiment, the multi-layer interconnect 122 and the multi-layer dielectric layer 124 may be stacked alternately to form the multi-layer stacked interconnect stack 120. Alternatively, the interconnect stack 120 may be a redistribution layer (RDL), a multi-layer circuit formed by the dielectric layer 124, the patterned interconnect 122 disposed on two opposite sides of the dielectric layer 124, and a conductive via (not labeled) penetrating the dielectric layer 124 and connecting to the patterned interconnect 122, or a single-layer circuit or a multi-layer circuit with other components, but the invention is not limited thereto. It should be noted that fig. 1A only schematically illustrates the four-layer interconnect stack 120 in which the four-layer interconnect 122 and the four-layer dielectric layer 124 are stacked alternately, but the structure of fig. 1A is not intended to limit the present invention. In other embodiments, the interconnect stack 120 may optionally include one, two, three, five, or more layers of interconnect and dielectric layers.
In the present embodiment, the material of the interconnect 122 includes a metal material, a metal nitride, a metal silicide or a combination thereof, based on the consideration of conductivity. The metal material may be, for example, titanium, copper, nickel, palladium, gold, silver, or an alloy thereof, but the present invention is not limited thereto. The interconnect 122 may be formed by a physical vapor deposition (pvd) process, such as sputtering or evaporation, a chemical vapor deposition (cvd) process, an electroplating process, or an electroless plating (electro plating) process, but the invention is not limited thereto.
In the present embodiment, the material of the dielectric layer 124 includes an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a stacked layer of at least two of the above materials), an organic material (e.g., Polyimide (PI), Polybenzoxazole (PBO), silicon gel (silicone), epoxy resin (epoxy), benzocyclobutene (BCB), or other suitable materials, or a stacked layer of at least two of the above materials), or other suitable materials, or a combination thereof, which is not limited in the present invention.
Referring to fig. 1A, a plurality of conductive pillars 140 are formed on the interconnect stack 120. In the present embodiment, the conductive pillar 140 is disposed on the interconnect 122 and electrically connected to the interconnect 122 of the interconnect stack 120. The conductive pillars 140 may be plated bumps or etched bumps, which may be the same or different from the interconnect 122, including a metal material. The metal material may be, for example, titanium, copper, nickel, palladium, gold, silver, or an alloy thereof, but the present invention is not limited thereto. The method of forming the conductive pillars 140 may include forming a conductive material on the interconnect stack 120, and patterning a plurality of conductive pillars 140 electrically connected to the interconnect 122 by photolithography, but the invention is not limited thereto. In the present embodiment, the diameter of any one of the conductive pillars 140 may be 5 micrometers (micrometer) to 60 micrometers, and the height of any one of the conductive pillars 140 may be 5 micrometers to 35 micrometers, but the invention is not limited thereto. In the present embodiment, the height of the conductive pillar 140 may be defined as the farthest distance from the interface where the conductive pillar 140 contacts the interconnect stack 120, extending along the normal direction of the interface to the surface of the conductive pillar 140 away from the interconnect stack 120.
In the present embodiment, an insulating layer 160 may be disposed on the interconnect stack 120 to cover the conductive pillars 140 and the interconnect stack 120. In the present embodiment, the material of the insulating layer 160 includes an organic material or an inorganic material. For example, epoxy resin (epoxy), acrylic resin, Polyimide (PI), Polybenzazole (PBO), silicone, benzocyclobutene (BCB), or other suitable materials may be included, but the invention is not limited thereto. The insulating layer 160 may serve as a passivation layer to protect the interconnect stack 120 and the conductive pillar 140 and improve protection from moisture and oxygen in the environment. In addition, the insulating layer 160 can also provide a bonding force for fixing the subsequent line build-up structure 100 to the substrate 200, so as to improve the bonding quality and reliability of the line substrate 10.
In the present embodiment, the insulating layer 160 may completely cover the conductive pillars 140. That is, the thickness of the insulating layer 160 disposed on the line build-up structure 100 may be greater than the thickness of the conductive pillar 140, but the invention is not limited thereto. In some embodiments, the thickness of the insulating layer 160 may also be equal to or less than the thickness of the conductive pillars 140.
In other embodiments, the insulating layer 160 may also be disposed on the substrate 200 to protect the circuit or the pad on the substrate 200, but not limited thereto.
Referring to fig. 1B, fig. 1B is a schematic cross-sectional view of a substrate 200 according to the present invention. In the embodiment, the substrate 200 is, for example, an organic substrate (organic substrate) having a circuit layer, and includes an outer dielectric layer 220 and a plurality of patterned pads 240 or contacts 260(terminal) disposed on the outer dielectric layer 220, but the invention is not limited thereto. In some embodiments, the substrate 200 may also be a coreless substrate (core), a Printed Circuit Board (PCB), an arbitrary-layer printed circuit board (any-layer printed circuit board), or a High Density Interconnect (HDI) technology, but is not limited thereto.
In the embodiment, the substrate 200 includes a core substrate (core) or a coreless substrate (core), and may be an insulating substrate, a flexible substrate, a glass substrate, or a combination thereof, which is not limited in the invention. The outer dielectric layer 220 may be a PrePreg (PrePrePreg) or other suitable dielectric material, but the invention is not limited thereto.
As shown in fig. 1B, the substrate 200 (or the outer dielectric layer 220) has a first surface 221 and a second surface 222 opposite to the first surface 221. In the present embodiment, a plurality of patterned pads 240 are disposed on the first surface 221 of the substrate 200. In the embodiment, the patterned pad 240 may be a part of a signal wire on the outer dielectric layer 220, but the invention is not limited thereto. In some embodiments, the patterned pads 240 may also be disposed separately from the signal wires but may be connected to each other. In addition, a plurality of contacts 260 are disposed on the second surface 222 of the substrate 200. In the embodiment, a via hole 224 may be selectively formed in the outer dielectric layer 220 to interconnect the patterned pad 240 on the first surface 221 of the substrate 200 and the internal circuit of the substrate 200, but the invention is not limited thereto. The formation of the via 224 may include photolithography, mechanical drilling, laser drilling or other suitable methods, but the invention is not limited thereto.
In the embodiment, the material of the patterned pad 240 and the contact 260 may be, for example, titanium, copper, nickel, palladium, gold, silver, or an alloy thereof, but the invention is not limited thereto.
It is noted that the patterned pad 240 of the present embodiment has a contact opening 244. Specifically, the patterned pad 240 includes a patterned metal layer 242 and a contact opening 244 disposed on the patterned metal layer 242. In this embodiment, the forming of the patterned pad 240 may include forming a metal material layer (not shown), then disposing a photoresist layer (photoresist) on the metal material layer, and then developing the photoresist layer. And etching the metal material layer by using a copper etching solution. The copper etching solution includes, for example, hydrogen peroxide (H) sulfate2SO4+H2O2) Iron chloride (FeCl)3) Ammonium cupric ammine chloride (H)8ClCuNO2) Copper chloride (CuCl)2) Hydrofluoric acid (HF), dilute hydrofluoric acid (DHF), or Buffered Oxide Etchant (BOE), but the invention is not limited thereto. Thus, the pattern of the photoresist layer can be transferred to the metal material layer, and the patterned metal layer 242 and the contact opening 244 on the patterned metal layer 242 can be directly formed. Therefore, the manufacturing process can be simplified and the cost can be saved.
In some embodiments, the patterned pad 240 with the contact opening 244 may also be directly formed. In other embodiments, the contact opening 244 may be formed by laser drilling or mechanical drilling after the patterned metal layer 242 is formed.
In the present embodiment, the patterned pad 240 (or the patterned metal layer 242) can meet the requirement of fine pitch. For example, the length L of the patterned pad 240 may be 15 to 80 microns, but not limited thereto. In some embodiments, the length L may be 40 to 60 microns or 60 to 80 microns. In the present embodiment, the length L may be defined as the maximum length of the patterned pad 240 extending along the first surface 221.
In the present embodiment, the thickness H1 of the patterned pad 240 (or the patterned metal layer 242) may be 5 to 35 micrometers, but is not limited thereto. In some embodiments, the thickness H1 may be 6 to 10 microns or 10 to 18 microns. In the present embodiment, the thickness H1 may be defined as the maximum thickness of the patterned pad 240 on the first surface 221 in a direction perpendicular to the substrate 200.
In the present embodiment, the aperture of the contact opening 244 away from the first surface 221 is larger than the aperture of the contact opening 244 adjacent to the first surface 221. For example, the aperture of the contact opening 244 is gradually reduced from the first surface 221 to the position adjacent to the first surface 221, so that the wall surface of the contact opening 244 is an inclined surface and an included angle may be formed between the wall surface and the bottom surface of the contact opening 244. In the embodiment, the included angle may be 0 to 90 degrees, but the invention is not limited thereto. In some embodiments, the included angle may be 30 degrees or 60 degrees.
In the present embodiment, the aperture of the contact opening 244 away from the first surface 221 may have a width W. The width W may be 5 to 60 micrometers, but is not limited thereto. In some embodiments, the width W may be 10 to 15 microns or 15 to 30 microns. In the present embodiment, the width W may be defined as the maximum width of the contact opening 244 at the aperture away from the first surface 221.
In the present embodiment, the depth D of the contact opening 244 may be 5 to 35 micrometers, but is not limited thereto. In some embodiments, the depth D may be 6 to 10 microns or 10 to 18 microns. In the present embodiment, the depth D may be defined as the maximum depth of the contact opening 244 on the first surface 221 in a direction perpendicular to the substrate 200. In the present embodiment, the depth D may be smaller than the thickness H1 of the patterned pad 240 (or the patterned metal layer 242). That is, the contact opening 244 does not penetrate the patterned metal layer 242, but a groove having an appropriate depth is formed on the patterned metal layer 242.
In some embodiments, the height (not labeled) of the conductive pillars 140 may be greater than or equal to the depth D of the contact openings 244, but not limited thereto.
In the present embodiment, the shape of the contact opening 244 in the top view is not particularly limited, and may be triangular, rectangular, polygonal, circular, oval or irregular. The contact opening 244 may be tapered or bowl-shaped in cross-section, but is not limited thereto.
In the present embodiment, the substrate 200 may be selectively cleaned after the contact opening 244 is formed, so as to remove impurities or dust that may be present, thereby further improving the reliability and quality of the subsequent bonding.
Referring to fig. 1C, the line build-up structure 100 is then laminated on the substrate 200. For example, the line build-up structure 100 may be pressed and disposed on the first surface 221 of the substrate 200. The conductive pillars 140 of the line build-up structure 100 correspond to the patterned pads 240 on the first surface 221, and each conductive pillar 140 correspondingly abuts each contact opening 244. In the present embodiment, the conductive pillars 140 may fill the contact openings 244 by thermocompression bonding. As such, the conductive pillars 140 can electrically connect the patterned pads 240, so as to electrically connect the line build-up structure 100 to the conductive lines and pads of the substrate 200 between the interconnect stack 120 and the patterned pads 240.
In the embodiment, the material of the conductive pillar 140 and the material of the patterned pad 240 may be the same, such as titanium, copper, nickel, palladium, gold, silver, or an alloy thereof, but the invention is not limited thereto.
Referring to fig. 1C, in the step of laminating the line build-up structure 100 to the substrate 200, the insulating layer 160 is also laminated to the substrate 200. In the above steps, the conductive pillars 140 pressed to the patterned pads 240 and the contact openings 244 can push away the insulating layer 160 covering the conductive pillars 140 without affecting the contact of the conductive pillars 140 to the contact openings 244. In addition, the insulating layer 160 may be located between the substrate 200 and the line build-up structure 100 to surround the conductive pillars 140 and fill the gaps between the conductive pillars 140. In addition, the insulating layer 160 may further cover the patterned pad 240. In this way, the insulating layer 160 can firmly fix the line build-up structure 100 to the substrate 200, and further enhance the bonding reliability and the bonding quality between the conductive pillars 140 and the patterned pads 240, so that the line substrate 10 has excellent electrical characteristics. In addition, the insulating layer 160 can further protect the conductive pillars 140 and the patterned pads 240 from moisture in the environment, and has better elasticity and flexibility, so as to absorb stress to improve the shock resistance of the circuit substrate 10, and further increase the bonding reliability and the bonding quality.
Referring to fig. 1C and fig. 1D, the carrier 110 is removed. In the present embodiment, the method of removing the carrier 110 includes, for example, separating the carrier 110 from the line build-up structure 100 by irradiation, heating, external mechanical force (e.g., peeling), or laser dissociation. Thus, the process of the circuit board 10 is completed.
It should be noted that, in the circuit substrate 10 according to the embodiment of the invention, the contact opening 244 can be directly formed on the patterned metal layer 242 of the patterned pad 240, so that the steps of additionally disposing a dielectric layer on the patterned metal layer 242 and disposing an opening to expose the patterned metal layer 242 can be omitted, thereby simplifying the process and reducing the cost.
In addition, since the wall surface of the contact opening 244 is an inclined surface, a metal-to-metal bonding process can be performed at a bonding temperature of 200 ℃ or lower in an ambient pressure environment during the bonding step. Specifically, when the conductive pillar 140 is a conductive copper pillar and the patterned pad 240 is a copper pad, a stress concentration point is generated between the conductive pillar 140 and the inclined wall surface of the contact opening 244 after the conductive pillar 140 contacts the inclined copper sidewall of the contact opening 244, so that the pressing temperature can be effectively reduced, and the force required for bonding can be reduced. In addition, the surface of the conductive post 140 does not need to be cleaned before bonding, and the surface of the conductive post is not required to be planarized by a chemical polishing process. In addition, the circuit substrate 10 does not need to be subjected to an additional annealing process after the bonding. Therefore, the copper-to-copper bonding method shown in this embodiment is suitable for reducing the manufacturing process requirement and reducing the manufacturing cost, and can also meet the copper-to-copper butt joint requirement, improve the bonding reliability and bonding quality of the conductive post 140 and the patterned pad 240, have good elasticity and flexibility, and have excellent electrical characteristics, so as to improve the signal transmission speed and quality of the circuit substrate 10.
It should be noted that, in the following embodiments, the reference numerals and partial contents of the elements in the foregoing embodiments are used, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the portions with the same technical contents omitted may refer to the foregoing embodiments, and the description in the following embodiments is not repeated.
Fig. 2 is a schematic cross-sectional view of a circuit substrate according to another embodiment of the invention. Referring to fig. 1D and fig. 2, the circuit substrate 10A of the present embodiment is similar to the circuit substrate 10 of fig. 1D, and the main difference is: the patterned pad 240A of the circuit substrate 10A includes a patterned metal layer 242A and a contact opening 244A. The contact opening 244A is disposed on the patterned metal layer 242A, and the contact opening 244A penetrates through the thickness of the patterned metal layer 242A and exposes the first surface 221 of the substrate 200A. That is, the depth of the contact opening 244A may be equal to the thickness of the patterned metal layer 242A.
Under the above arrangement, the conductive pillar 140 correspondingly abutting against the contact opening 244A can contact the first surface 221. Thus, the process for forming the contact opening 244A can be simplified, and the need for thinning can be further satisfied.
Fig. 3 is a schematic cross-sectional view of a circuit substrate according to still another embodiment of the invention. Referring to fig. 1D and fig. 3, the circuit substrate 10B of the present embodiment is similar to the circuit substrate 10 of fig. 1D, and the main difference is that: the circuit substrate 10B further includes a plurality of etch stop layers 280 disposed on the first surface 221 of the substrate 200B. The etch stop layer 280 is disposed corresponding to the patterned pad 240B (or the patterned metal layer 242B). Specifically, before the step of forming the patterned pad 240B, an etching stop material (not shown) may be formed on the first surface 221, and then the etching stop material is patterned by a photolithography process to form the etching stop layer 280. In the present embodiment, the etch stop layer 280 may conformally fill the via hole 224 of the substrate 200B on the first surface 221.
In the present embodiment, the material of the etch stop layer 280 includes titanium, tin, molybdenum, aluminum, or other suitable materials, which is not limited by the invention. In the present embodiment, the thickness H2 of the etch stop layer 280 may be, but is not limited to, 5 nanometers (nanometer) to 100 nanometers. In some embodiments, the thickness H2 may be 5 nanometers to 10 nanometers or 10 nanometers to 20 nanometers. In the present embodiment, the thickness H2 may be defined as the maximum thickness of the etch stop layer 280 on the first surface 221 in a direction perpendicular to the substrate 200.
Next, a patterned pad 240B is correspondingly disposed on the etch stop layer 280. For example, a patterned metal layer 242B is disposed on the etch stop layer 280, and then a contact opening 244B is formed in the patterned metal layer 242B. In some embodiments, the edge of the patterned metal layer 242B is aligned with the etch stop layer 280, but the invention is not limited thereto. Under the above configuration, the etch stop layer 280 is located between the patterned pad 240B (or the patterned metal layer 242B) and the substrate 200. In the embodiment, the thickness of the patterned pad 240B may be greater than the thickness H2 of the etch stop layer 280, but the invention is not limited thereto. In some embodiments, the thickness of the patterned pad 240B may be equal to or less than the thickness H2 of the etch stop layer 280.
In the present embodiment, the orthographic projection of the contact opening 244B in the direction perpendicular to the substrate 200 does not overlap the orthographic projection of the via 224 in the direction perpendicular to the substrate 200, but the invention is not limited thereto.
In the present embodiment, the contact opening 244B may extend through the thickness of the patterned metal layer 242B and expose the etch stop layer 280. That is, the depth of the contact opening 244B may be equal to the thickness of the patterned metal layer 242B. Under the above arrangement, in the step of developing and etching the patterned metal layer 242B, the etching stop layer 280 can reduce the influence of the etching solution on the substrate 200. As a result, the influence of the manufacturing process on the substrate 200 can be reduced, and the patterned pad 240B can be formed on the substantially flat etch stop layer 280, so that the subsequent contact opening 244B can be reliably abutted to the conductive pillar 140, thereby improving the quality of the circuit substrate 10B.
In the present embodiment, the conductive pillars 140 corresponding to the contact openings 244B may contact the etch stop layer 280. As a result, the circuit substrate 10B can not only simplify the process and protect the substrate 200, but also improve the reliability and quality of the bonding through the etching stop layer 280 and have good electrical characteristics. Further, the wiring substrate 10B can also obtain the same effects as those of the above-described embodiment.
In summary, in the circuit substrate according to an embodiment of the invention, the contact opening can be directly formed on the patterned pad, so that an additional dielectric layer can be omitted, the process can be simplified, and the cost can be reduced. In addition, because the wall surface of the contact opening is an inclined surface, the pressing and copper-to-copper bonding processes can be performed under the environment of normal pressure and low temperature (the temperature is less than or equal to 200 ℃). After the conductive pillar contacts the inclined surface of the contact opening, a stress concentration point is generated between the conductive pillar and the wall surface of the contact opening, so that the pressing temperature can be effectively reduced, and the force required by bonding can be reduced. Therefore, the copper-to-copper bonding method shown in this embodiment is suitable for reducing the requirement of the manufacturing process and the manufacturing cost, and can also meet the requirement of copper-to-copper butt joint, improve the bonding reliability and the bonding quality of the conductive post and the patterned pad, have good elasticity and flexibility, and have excellent electrical characteristics so as to improve the signal transmission speed and quality of the circuit substrate.
In addition, the insulating layer arranged between the substrate and the line build-up structure can improve the bonding force, and can surround the conductive posts and cover the patterned bonding pads. Therefore, the insulating layer can protect the conductive posts and the patterned connecting pads from being affected by moisture in the environment, has good elasticity and flexibility, and can absorb stress to improve the shock resistance of the circuit substrate, and further increase the connection reliability and the connection quality of the circuit substrate.
In addition, the circuit substrate can reduce the influence of the etching solution process on the substrate through the etching stop layer, the patterned connecting pad can be flat, the connection reliability and quality of the contact opening and the conductive column are improved, and the circuit substrate has excellent quality and electrical characteristics.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A circuit substrate, comprising:
a substrate having a first surface and a second surface opposite the first surface, the substrate comprising:
a plurality of patterned pads disposed on the first surface of the substrate, each patterned pad having a contact opening;
a line build-up structure disposed on the first surface of the substrate, comprising:
an interconnect stack; and
a plurality of conductive pillars electrically connecting the interconnect stack and the patterned pads; and
the insulating layer is arranged between the substrate and the line layer-adding structure.
2. The circuit substrate of claim 1, wherein each of the conductive posts abuts each of the contact openings.
3. The circuit substrate of claim 1, wherein the wall surface of the contact opening is an inclined surface, and an aperture of the contact opening away from the first surface is larger than an aperture of the contact opening adjacent to the first surface.
4. The circuit substrate of claim 1, wherein each of the patterned pads further comprises a patterned metal layer, the contact opening is disposed on the patterned metal layer, and a depth of the contact opening is smaller than a thickness of the patterned metal layer.
5. The circuit substrate of claim 1, wherein each of the patterned pads further comprises a patterned metal layer, the contact opening is disposed on the patterned metal layer, and the contact opening penetrates through a thickness of the patterned metal layer and exposes the first surface of the substrate.
6. The circuit substrate of claim 5, wherein each of the conductive posts abuts against each of the contact openings and contacts the first surface.
7. The circuit substrate according to claim 1, further comprising a plurality of etching stop layers disposed on the first surface, wherein each of the patterned pads is disposed corresponding to each of the etching stop layers, and each of the etching stop layers is disposed between each of the patterned pads and the substrate.
8. The circuit substrate of claim 7, wherein each of the patterned pads further comprises a patterned metal layer, the contact opening is disposed on the patterned metal layer, and the contact opening penetrates through a thickness of the patterned metal layer and exposes the etch stop layer.
9. The circuit substrate of claim 7, wherein each of the conductive posts abuts each of the contact openings and contacts the etch stop layer.
10. The circuit substrate according to claim 1, wherein the insulating layer surrounds the conductive pillars and fills gaps between the conductive pillars, and the insulating layer covers the patterned pads.
CN202010096556.0A 2019-12-16 2020-02-14 Circuit substrate Pending CN112992841A (en)

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CN114126190A (en) * 2020-08-28 2022-03-01 欣兴电子股份有限公司 Circuit board structure and manufacturing method thereof
US11540396B2 (en) 2020-08-28 2022-12-27 Unimicron Technology Corp. Circuit board structure and manufacturing method thereof
TWI762310B (en) * 2021-05-13 2022-04-21 欣興電子股份有限公司 Circuit board structure and manufacturing method thereof

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