CN112992805A - Semiconductor package device and method of manufacturing the same - Google Patents
Semiconductor package device and method of manufacturing the same Download PDFInfo
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- CN112992805A CN112992805A CN202110117239.7A CN202110117239A CN112992805A CN 112992805 A CN112992805 A CN 112992805A CN 202110117239 A CN202110117239 A CN 202110117239A CN 112992805 A CN112992805 A CN 112992805A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
The present disclosure provides a semiconductor package device and a method of manufacturing the same. The packaging material with higher Young modulus is used as the underfill to protect the solder bumps at the bottom of the wafer, and the packaging material has higher hardness at normal temperature and high temperature relative to the underfill, so that the bumps at the bottom of the bare wafer in the stacked package can be better protected, the stress of the dielectric layer and the ultralow dielectric material is reduced, the strength of the whole packaging device at normal temperature to high temperature is improved, and the problem of mechanical reliability caused by the adoption of the traditional underfill is avoided.
Description
Technical Field
The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor packaging device and a method for manufacturing the same.
Background
A Package on Package (PoP) structure is a Package structure formed by integrating two or more semiconductor Package devices in a vertical stack or back-to-back mounting manner, a high-density logic device in a bottom structure, and a high-density memory device in a top structure.
Because the stacked package structure allows more than two package structures to be vertically stacked, the stacked package structure occupies less space than the conventional side-by-side structure, and the effect of improving the overall frequency can be achieved by directly electrically connecting the memory device and the logic device.
Disclosure of Invention
The present disclosure provides a semiconductor package device and a method of manufacturing the same.
In a first aspect, the present disclosure provides a semiconductor package device comprising: the lower surface of the bottom substrate is provided with a bottom substrate lower solder ball which is electrically connected with the bottom substrate; the packaging structure comprises a bottom substrate, solder balls, a bare chip and a first packaging material, wherein the solder balls, the bare chip and the first packaging material are arranged on the bottom substrate, the solder balls on the bottom substrate are electrically connected with the bottom substrate, the bottom of the bare chip is electrically connected with the bottom substrate through a bump, the first packaging material surrounds the solder balls on the bottom substrate and the bare chip and does not cover the upper surfaces of the solder balls on the bottom substrate and the bare chip, and the first packaging material is filled between the bottom of the bare chip and the bottom substrate; a second packaging material disposed on the first packaging material and the bare chip; the middle substrate is arranged on the second packaging material, a middle substrate lower solder ball electrically connected with the middle substrate lower solder ball is arranged on the lower surface of the middle substrate, the middle substrate lower solder ball is electrically connected with the bottom substrate upper solder ball, and the second packaging material surrounds the lower surface and the side surface of the middle substrate and the middle substrate lower solder ball.
In some optional embodiments, a solder mask is disposed on a region of the lower surface of the intermediate substrate not corresponding to the bare chip.
In some optional embodiments, no solder mask is disposed on the region of the lower surface of the intermediate substrate corresponding to the bare chip.
In some optional embodiments, at least one solder mask bump is disposed on a region of the lower surface of the intermediate substrate corresponding to the bare chip.
In some optional embodiments, the young's modulus of the first encapsulant is greater than 0.3 gigapascal (Gpa) between ambient temperature and 260 degrees celsius, and/or the glass transition temperature of the first encapsulant is greater than 125 degrees celsius.
In some alternative embodiments, the first encapsulant and the second encapsulant have different thermal expansion coefficients.
In some alternative embodiments, the area of the intermediate substrate is smaller than the area of the bottom substrate.
In some alternative embodiments, an interface is formed between the first encapsulant and the second encapsulant.
In some optional embodiments, the upper surface of the intermediate substrate is provided with a solder mask and a conductive connector electrically connecting the intermediate substrate.
In some alternative embodiments, the thickness of the intermediate substrate is 80 microns.
In a second aspect, the present disclosure provides a method of manufacturing a semiconductor package device, the method comprising: providing a bottom substrate, a bare chip and an intermediate substrate, wherein the upper surface of the bottom substrate is provided with a bottom substrate upper solder ball electrically connected with the bottom substrate, the lower surface of the bare chip is provided with a bump electrically connected with the bare chip, and the lower surface of the intermediate substrate is provided with an intermediate substrate lower solder ball electrically connected with the intermediate substrate lower solder ball; electrically connecting the bottom die lower surface to the bottom substrate upper surface; molding to form a first packaging material which covers the bottom substrate and the solder balls on the bottom substrate and does not cover the upper surface of the bare chip; removing the first packaging material on the solder balls on the bottom substrate to expose the solder balls on the bottom substrate; electrically connecting the intermediate substrate lower solder balls to the bottom substrate upper solder balls; molding to form a second packaging material surrounding the lower surface and the side surface of the middle substrate and the lower solder balls of the middle substrate; and mounting bottom substrate lower solder balls on the lower surface of the bottom substrate so that the bottom substrate lower solder balls are electrically connected with the bottom substrate.
In some optional embodiments, before the removing the first encapsulant on the solder balls on the base substrate to expose the solder balls on the base substrate, the method further includes: and carrying out cavity detection on the bump area at the bottom of the bare chip.
In some optional embodiments, said electrically connecting said bottom die lower surface to said bottom substrate upper surface comprises: and flip-chip bonding the lower surface of the bare chip to the upper surface of the bottom substrate.
In some optional embodiments, the removing the first encapsulant on the solder balls on the base substrate to expose the solder balls on the base substrate includes: and laser ablating the first packaging material on the solder balls on the bottom substrate to expose the solder balls on the bottom substrate.
After the semiconductor wafer process enters 5 nm, in order to reduce the problems of Integrated Circuit (IC) leakage current, inter-wire capacitance effect, and Integrated Circuit heating, the Dielectric layer of the wafer is mostly prepared by using an ultra Low Dielectric material (ELK), and the ultra Low Dielectric material is made of a porous material because vacuum has the lowest Dielectric constant. However, the pores of the porous material may reduce the strength of the material. That is, the 5 nm wafer is low in strength because of the use of an ultra-low dielectric material.
After the chip is connected to the substrate in the stacked package structure, an Underfill (underfil) is generally used to protect the bumps (Bump) or Micro bumps (Micro Bump) on the bottom of the chip (Die) to enhance the overall strength of the package structure. However, the underfill is soft at high temperatures (the young's modulus of the underfill is 11.1 gpa at 25 degrees celsius, the young's modulus at 260 degrees celsius is only 0.08 gpa, and the glass transition temperature of the underfill is 75.7 degrees), which makes the CPI (Chip Package Interaction) of the entire Package structure large, directly affecting the ultra-low dielectric material of the wafer. Here, CPI means that because of differences in CTE (Coefficient of Thermal Expansion) between the wafer and the substrate, the heat and stress generated during the packaging process and reliability test will cause mechanical reliability problems in the underfill at the bottom of the wafer, such as: solder Fatigue Failure (Solder Fatigue Failure), Underfill Delamination (Underfill Delamination), and the like.
To solve the technical problems in the prior art, the present disclosure provides a semiconductor package device and a method for manufacturing the same, which can achieve the following technical effects, including but not limited to:
firstly, the bare chip is electrically connected to the bottom substrate, and then the first molding is carried out to form a first packaging material, the first packaging material wraps the bottom substrate and the solder balls on the bottom substrate, and the first packaging material is exposed on the upper surface of the bare chip. The upper surface of the bare chip is exposed, so that the cavity detection of the bare chip can be realized, and the yield of the packaging device can be improved due to the cavity detection of the bare chip.
And secondly, covering the solder balls on the bottom substrate by the first packaging material formed in the first molding, removing the first packaging material on the solder balls on the bottom substrate, exposing the solder balls on the bottom substrate, and electrically connecting the lower solder balls of the middle substrate to the solder balls on the bottom substrate. Instead of directly exposing the solder balls on the bottom substrate and electrically connecting the lower solder balls of the intermediate substrate to the solder balls on the bottom substrate during the first molding, Electrostatic Discharge (ESD) can be avoided, thereby improving the yield of the packaging device.
Thirdly, the second packaging material surrounding the lower surface and the side surface of the middle substrate and the lower solder balls of the middle substrate is formed through the second molding, so that the interconnection between the middle substrate and the bottom substrate can be protected, and the upper surface of the bare chip can also be protected by the second packaging material.
Fourth, by using a packaging material (Molding Compound) with a higher young's modulus as an Underfill material (i.e., MUF, Molded Underfill) to protect solder bumps (Bump) on the bottom of the wafer, since the packaging material has a higher hardness at both normal and high temperatures relative to the Underfill (the young's modulus of the packaging material at 25 degrees celsius is 22 gigapascals, the young's modulus at 260 degrees celsius is 1.25 gigapascals, and the glass transition temperature of the packaging material can reach 150 degrees), it is possible to better protect the bumps on the bottom of the bare wafer in the package stack, reduce the stress on the dielectric layer and the ultra-low dielectric material, improve the strength of the overall package device at normal to high temperatures, and avoid the mechanical reliability problem caused by using the conventional Underfill.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1A is a schematic structural diagram of one embodiment of a semiconductor package device according to the present disclosure;
fig. 1B is a schematic structural diagram of yet another embodiment of a semiconductor package device according to the present disclosure;
fig. 1C is a schematic structural diagram of yet another embodiment of a semiconductor package device according to the present disclosure;
fig. 2A-2G are cross-sectional views of a semiconductor package device fabricated at various stages according to one embodiment of the present disclosure.
Description of the symbols:
1a base substrate; 7 a second sealing material;
2 bottom substrate lower solder balls; 8 an intermediate substrate;
3, solder balls are arranged on the bottom substrate; 9 lower solder balls of the intermediate substrate;
4 bare wafer; 10, solder mask;
5 a first encapsulating material; 11 solder mask bumps;
6, a bump; 12 conductive connection member.
Detailed Description
The following description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples, and the technical problems and effects solved by the present invention will be readily apparent to those skilled in the art from the description of the embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.
It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined by the claims and the appended claims, and therefore, they are not technically essential, and any structural modification, proportion change, or size adjustment should be within the scope of the present disclosure without affecting the function and achievement of the present disclosure. In addition, the terms "above", "first", "second" and "a" as used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship thereof may be regarded as the scope of the present invention without substantial technical changes.
In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Referring to fig. 1A, fig. 1A illustrates a cross-sectional view of one embodiment of a semiconductor package device 1A according to the present disclosure.
As shown in fig. 1A, the semiconductor package device 1A may include a base substrate 1, base substrate lower solder balls 2, base substrate upper solder balls 3, a bare chip 4, a first encapsulant 5, bumps 6, a second encapsulant 7, an intermediate substrate 8, and intermediate substrate lower solder balls 9.
Wherein:
the lower surface of the base substrate 1 is provided with a base substrate lower solder ball 2 electrically connected thereto for realizing connection of the semiconductor package device 1a with the outside.
The solder balls 3, the bare chip 4 and the first packaging material 5 are arranged on the bottom substrate 1.
The solder balls 3 on the bottom substrate are electrically connected with the bottom substrate 1, and the bottom of the bare chip 4 is electrically connected with the bottom substrate 1 through the bumps 6.
The first encapsulating material 5 surrounds the solder balls 3 on the base substrate and the bare chip 4 and does not cover the upper surfaces of the solder balls 3 on the base substrate and the bare chip 4, that is, the first encapsulating material 5 is exposed on the upper surface of the bare chip 4. And the first packaging material 5 is filled between the bottom of the bare chip 4 and the bottom substrate 1, and the first packaging material 5 filled between the bottom of the bare chip 4 and the bottom substrate 1 can protect the interconnection between the bare chip 4 and the bottom substrate 1.
And a second sealing material 7 disposed on the first sealing material 5 and the bare chip 4.
And the intermediate substrate 8 is arranged on the second packaging material 7, the lower surface of the intermediate substrate 8 is provided with an intermediate substrate lower solder ball 9 electrically connected with the intermediate substrate, and the intermediate substrate lower solder ball 9 is electrically connected with the bottom substrate upper solder ball 3, namely the intermediate substrate 8 and the bottom substrate 1 are electrically connected through the intermediate substrate lower solder ball 9 and the bottom substrate upper solder ball 3.
The second encapsulant 7 surrounds the lower surface and side surfaces of the intermediate substrate 8 and the intermediate substrate lower solder balls 9. That is, the second sealing material can protect the bottom of the intermediate substrate 8.
Wherein, the concrete description is as follows:
the base substrate 1 and the intermediate substrate 8 may be various substrates (substrates) provided with wiring. In addition, according to actual needs, through holes, buried holes or blind holes may be further disposed on the base substrate 1 and the intermediate substrate 8 to implement circuit connection. It should be noted that the size or direction of the through hole, buried hole or blind hole is not specifically limited. If a via, buried via or blind via is provided, the via, buried via or blind via may be filled with or contain a conductive material such as a metal or metal alloy. Here, the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy thereof.
Here, the bare chip 4 may be a bare chip (Die) that realizes various functions. For example, the bare die 4 may be a logic chip that implements logic operations or a memory chip that implements data storage.
The first and second potting materials 5 and 7 may be formed of various Molding compounds (Molding compounds). For example, the encapsulating material may include Epoxy resin (Epoxy resin), Filler (Filler), Catalyst (Catalyst), Pigment (Pigment), Release Agent (Release Agent), Flame Retardant (Flame Retardant), Coupling Agent (Coupling Agent), Hardener (hardner), Low Stress absorbent (Low Stress Absorber), Adhesion Promoter (Adhesion Promoter), Ion trap (Ion Trapping Agent), and the like.
The technical effects that the semiconductor package device 1a can achieve include, but are not limited to:
(1) by filling the space between the bottom of the bare chip 4 and the base substrate 1 with the first encapsulating material 5 having a higher young's modulus, the interconnection between the bare chip 4 and the base substrate 1 can be protected. Compared with the prior art that the underfill is filled at the bottom of the bare chip, the underfill is replaced by the packaging material, the property of higher Young modulus of the packaging material at normal temperature and high temperature is utilized, the strength of the semiconductor packaging device is improved, and the problem of mechanical reliability possibly caused by the traditional underfill is solved.
(2) The upper surface of the bare chip 4 is not covered with the first encapsulating material 5, which makes it easier to perform void detection on the bottom bump area of the bare chip 4 during the manufacturing process. Since the cavity detection can be performed for the bare chip 4, the yield of the packaging device can be improved.
In some alternative embodiments, the young's modulus of the first encapsulant 5 is greater than 0.3 gpa at ambient temperature (i.e., 25 degrees celsius) to 260 degrees celsius, and/or the glass transition temperature of the first encapsulant is greater than 125 degrees celsius. With this alternative embodiment, the hardness of the first encapsulant 5 is relatively high from normal temperature to a higher temperature (i.e., 260 degrees celsius), which may improve the overall strength and yield of the semiconductor package.
In practice, the substrate thicknesses of the base substrate 1 and the intermediate substrate 8 are usually different, and the thermal expansion coefficients of the base substrate 1 and the intermediate substrate 8 may also be different, and in order to reduce the occurrence of warpage, in some alternative embodiments, the thermal expansion coefficients of the first packaging material and the second packaging material may be different. With this alternative embodiment, it is possible to balance the difference in the thermal expansion coefficients of the base substrate 1 and the intermediate substrate 8, reducing warpage.
In order to fill the gap between the intermediate substrate 8 and the bare chip 4 with the second encapsulant 7, in some alternative embodiments, the area of the intermediate substrate 8 may be smaller than that of the bottom substrate 1, and the second encapsulant 7 may cover the lower surface and the side surface of the intermediate substrate 8 and the solder balls 9 under the intermediate substrate, thereby improving the strength of the semiconductor package device.
In some alternative embodiments, the thickness of the intermediate substrate 8 may be 80 microns.
In some alternative embodiments, an interface is formed between the first encapsulant 5 and the second encapsulant 7. That is, the first sealing material 5 and the second sealing material 7 are formed by two different sealing processes.
In some alternative embodiments, the upper surface of the intermediate substrate 8 may be provided with a solder mask and a conductive connection member electrically connecting the intermediate substrate 8. With this alternative embodiment, additional wafers may be further stacked above the semiconductor package. For example, the bare chip 4 is a logic chip, and the upper surface of the intermediate substrate 8 may be overlaid with a memory chip, and the memory chip may be electrically connected to the intermediate substrate 8 through an electrical connector disposed on the upper surface of the intermediate substrate 8.
With continued reference to fig. 1B, the semiconductor package device 1B shown in fig. 1B is similar to the semiconductor package device 1A shown in fig. 1A, except that: in the semiconductor package device 1b, the Solder Mask 10 is provided on the lower surface of the intermediate substrate 8 in the region not corresponding to the bare chip 4, and the Solder Mask 10 is not provided on the lower surface of the intermediate substrate 8 in the region corresponding to the bare chip 4. In the semiconductor package device 1b, since the solder resist 10 is not disposed in the region of the lower surface of the intermediate substrate 8 corresponding to the bare chip 4, the space between the upper surface of the bare chip 4 and the lower surface of the intermediate substrate 8 can be increased, which is advantageous for filling the second encapsulant 7 into the space.
With continued reference to fig. 1C, the semiconductor package device 1C shown in fig. 1C is similar to the semiconductor package device 1A shown in fig. 1A, except that: in the semiconductor package device 1c, a Solder resist 10 is provided on a region of the lower surface of the intermediate substrate 8 not corresponding to the bare chip 4, and at least one Solder resist bump (Solder Mask Dot)11 is provided on a region of the lower surface of the intermediate substrate 8 corresponding to the bare chip 4.
In the semiconductor package device 1c, compared with the semiconductor package device 1a, the area of the lower surface of the intermediate substrate 8 corresponding to the bare chip 4 is provided with at least one solder mask bump 11 instead of the solder mask on the whole, so that the space between the upper surface of the bare chip 4 and the lower surface of the intermediate substrate 8 can be increased, and the second package material 7 can be filled in the space. Because the intermediate substrate 8 is not very rigid, the semiconductor packaging device 1c is relatively to the semiconductor packaging device 1b, and because the region of the lower surface of the intermediate substrate 8 corresponding to the bare chip 4 is provided with at least one solder mask bump 11, the intermediate substrate 8 can be supported and reinforced, and the structural strength of the semiconductor packaging device 1c is further improved.
Fig. 2A, 2B, 2C, 2D, 2E, 2F, and 2G are schematic cross-sectional views of semiconductor package devices 2A, 2B, 2C, 2D, 2E, 2F, and 2G fabricated at various stages according to some embodiments of the present disclosure. The figures have been simplified for a better understanding of various aspects of the disclosure.
Referring to fig. 2A, a base substrate 1, a bare chip 4, and an intermediate substrate 8 are provided.
The upper surface of the bottom substrate 1 is provided with a bottom substrate upper solder ball 3 electrically connected with the bottom substrate, the lower surface of the bare chip 4 is provided with a bump 6 electrically connected with the bare chip, and the lower surface of the middle substrate 8 is provided with a middle substrate lower solder ball 9 electrically connected with the middle substrate.
The lower surface of the intermediate substrate 8 may be provided with other circuits in addition to the intermediate substrate lower solder balls 9.
Referring to fig. 2B, the lower surface of the bare wafer 4 is electrically connected to the upper surface of the base substrate 1.
That is, the bumps 6 provided on the lower surface of the bare chip 4 are electrically connected to the conductive connecting members provided on the upper surface of the base substrate 1. For example, the upper surface of the base substrate 1 may be provided with wires, solder balls, solder bumps, or the like for electrical connection with the bare chip 4. In particular, a corresponding connection may be used. In some alternative embodiments, Flip Chip Bonding (Flip Chip Bonding) can be used to electrically connect the bottom surface of the die 4 to the top surface of the base substrate 1.
With continued reference to fig. 2C, the first encapsulant 5 is molded to cover the bottom substrate 1 and the solder balls 3 on the bottom substrate, and not cover the upper surface of the bare chip 4.
Since the first packaging material 5 covers the solder balls 3 on the bottom substrate, in order to electrically connect the solder balls 3 on the bottom substrate with the lower solder balls 9 on the middle substrate, referring to fig. 2D, the first packaging material 5 on the solder balls 3 on the bottom substrate is removed to expose the solder balls 3 on the bottom substrate. In some alternative embodiments, Laser Ablation (Laser Ablation) may be used to expose the first encapsulant 5 on the solder balls 3 on the bottom substrate to expose the solder balls 3 on the bottom substrate.
Since the first encapsulant 5 obtained by molding in fig. 2C does not cover the upper surface of the bare chip 4, in some alternative embodiments, the cavity detection may be performed on the bump region where the bumps 6 on the bottom of the bare chip 4 are located before the first encapsulant 5 on the solder balls 3 on the bottom substrate is removed to expose the solder balls 3 on the bottom substrate. For example, cavity detection can be performed using ultrasound microscopy (SAT), also known as C-SCAN. Since the void detection is performed, the yield of the semiconductor package device can be improved.
Referring next to fig. 2E, the intermediate substrate lower solder balls 9 are electrically connected to the bottom substrate upper solder balls 3. Thereby achieving electrical connection of the intermediate substrate 8 to the base substrate 1. If another chip is subsequently stacked on the intermediate substrate 8 and electrically connected thereto, the stacked chip may be electrically connected to the base substrate 1. Since the bare chip 4 is also electrically connected to the base substrate 1 in the step shown in fig. 2B, further other chips subsequently laminated onto the intermediate substrate 8 may also be electrically connected to the bare chip 4.
With continued reference to fig. 2F, the second encapsulant 7 is molded to form a package surrounding the lower surface, side surfaces and the under-substrate solder balls 9 of the intermediate substrate 8.
With respect to the first molding of fig. 2C, the molding of fig. 2F is referred to herein as a second molding. By the second molding, Interconnection (Interconnection) between the intermediate substrate 8 and the base substrate 1 and the bare chip 4 can be protected.
Referring next to fig. 2G, bottom substrate lower solder balls 2 are mounted on the lower surface of the bottom substrate 1, so that the bottom substrate lower solder balls 2 are electrically connected to the bottom substrate 1 for connection of the semiconductor package device to the outside.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction and the actual implementation in the present disclosure due to variables in the manufacturing process, and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.
Claims (14)
1. A semiconductor package device, comprising:
the lower surface of the bottom substrate is provided with a bottom substrate lower solder ball which is electrically connected with the bottom substrate;
the packaging structure comprises a bottom substrate, solder balls, a bare chip and a first packaging material, wherein the solder balls, the bare chip and the first packaging material are arranged on the bottom substrate, the solder balls on the bottom substrate are electrically connected with the bottom substrate, the bottom of the bare chip is electrically connected with the bottom substrate through a bump, the first packaging material surrounds the solder balls on the bottom substrate and the bare chip and does not cover the upper surfaces of the solder balls on the bottom substrate and the bare chip, and the first packaging material is filled between the bottom of the bare chip and the bottom substrate;
a second packaging material disposed on the first packaging material and the bare chip;
the middle substrate is arranged on the second packaging material, a middle substrate lower solder ball electrically connected with the middle substrate lower solder ball is arranged on the lower surface of the middle substrate, the middle substrate lower solder ball is electrically connected with the bottom substrate upper solder ball, and the second packaging material surrounds the lower surface and the side surface of the middle substrate and the middle substrate lower solder ball.
2. The semiconductor package device according to claim 1, wherein a solder mask is provided on a region of the lower surface of the intermediate substrate not corresponding to the bare chip.
3. The semiconductor package device according to claim 2, wherein a solder mask is not provided on a region of the lower surface of the intermediate substrate corresponding to the bare chip.
4. The semiconductor package device according to claim 2, wherein at least one solder bump is provided on a region of the lower surface of the intermediate substrate corresponding to the bare chip.
5. The semiconductor package device according to claim 1, wherein the young's modulus of the first package material between room temperature and 260 degrees celsius is greater than 0.3 gigapascal Gpa, and/or the glass transition temperature of the first package material is greater than 125 degrees celsius.
6. The semiconductor package device according to claim 1, wherein the first encapsulating material and the second encapsulating material have different coefficients of thermal expansion.
7. The semiconductor package device of claim 1, wherein the area of the middle substrate is smaller than the area of the bottom substrate.
8. The semiconductor package device of claim 1, wherein an interface is formed between the first encapsulant and the second encapsulant.
9. The semiconductor package device according to claim 1, wherein the intermediate substrate upper surface is provided with a solder resist and a conductive connecting member electrically connecting the intermediate substrate.
10. The semiconductor package device of claim 1, wherein the thickness of the intermediate substrate is 80 microns.
11. A method of manufacturing a semiconductor package device, comprising:
providing a bottom substrate, a bare chip and an intermediate substrate, wherein the upper surface of the bottom substrate is provided with a bottom substrate upper solder ball electrically connected with the bottom substrate, the lower surface of the bare chip is provided with a bump electrically connected with the bare chip, and the lower surface of the intermediate substrate is provided with an intermediate substrate lower solder ball electrically connected with the intermediate substrate lower solder ball;
electrically connecting the bottom die lower surface to the bottom substrate upper surface;
molding to form a first packaging material which covers the bottom substrate and the solder balls on the bottom substrate and does not cover the upper surface of the bare chip;
removing the first packaging material on the solder balls on the bottom substrate to expose the solder balls on the bottom substrate;
electrically connecting the intermediate substrate lower solder balls to the bottom substrate upper solder balls;
molding to form a second packaging material surrounding the lower surface and the side surface of the middle substrate and the lower solder balls of the middle substrate;
and mounting bottom substrate lower solder balls on the lower surface of the bottom substrate so that the bottom substrate lower solder balls are electrically connected with the bottom substrate.
12. The method of claim 11, wherein prior to said removing the first encapsulant over the solder balls on the base substrate to expose the solder balls on the base substrate, the method further comprises:
and carrying out cavity detection on the bump area at the bottom of the bare chip.
13. The method of claim 11, wherein said electrically connecting said bare wafer lower surface to said base substrate upper surface comprises:
and flip-chip bonding the lower surface of the bare chip to the upper surface of the bottom substrate.
14. The method of claim 11, wherein the removing the first encapsulant over the solder balls on the base substrate to expose the solder balls on the base substrate comprises:
and laser ablating the first packaging material on the solder balls on the bottom substrate to expose the solder balls on the bottom substrate.
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| CN202110117239.7A CN112992805B (en) | 2021-01-28 | 2021-01-28 | Semiconductor package device and method of manufacturing the same |
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| US20120299183A1 (en) * | 2010-02-17 | 2012-11-29 | Canon Kabushiki Kaisha | Semiconductor device and stacked-type semiconductor device |
| US20120153499A1 (en) * | 2010-12-21 | 2012-06-21 | Samsung Electronics Co., Ltd. | Semiconductor package and package on package having the same |
| CN103050454A (en) * | 2012-12-06 | 2013-04-17 | 日月光半导体制造股份有限公司 | Package on package structure |
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