CN112992040A - Adjusting circuit and display device - Google Patents
Adjusting circuit and display device Download PDFInfo
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- CN112992040A CN112992040A CN202110395380.3A CN202110395380A CN112992040A CN 112992040 A CN112992040 A CN 112992040A CN 202110395380 A CN202110395380 A CN 202110395380A CN 112992040 A CN112992040 A CN 112992040A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
Abstract
The invention discloses a regulating circuit and a display device, relating to the technical field of display, wherein the regulating circuit comprises: the voltage adjusting module is used for receiving the first voltage signal to control the signal of the first node, and adjusting the signal of the first node according to the temperature or the illumination intensity; and the control module is used for receiving the signal of the first node and the second voltage signal, responding to the first control signal, the second control signal, the third control signal, the fourth control signal, the fifth control signal and the sixth control signal, and controlling the signal of the second node, wherein the signal of the second node is an output signal. The invention solves the problem of higher power consumption caused by always adopting the highest voltage to set the driving voltage in the prior art.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to an adjusting circuit and a display device.
Background
As the display panel is more and more commonly used in various electronic devices, for example, the display panel has been widely used in smart phones, tablet personal computers, laptop computers, digital cameras, camcorders, Personal Digital Assistants (PDAs), and thin televisions, etc., research on the display panel is more and more intensive.
In order to realize normal display at different temperatures or different brightness, the conventional display panel usually sets a driving voltage according to the highest voltage, so that the power consumption of the display panel is high, and energy waste is caused.
Disclosure of Invention
In view of the above, the present invention provides a regulating circuit and a display device to solve the problem of large power consumption caused by always using the highest voltage to set the driving voltage in the prior art.
The present invention provides a regulating circuit, comprising: the voltage adjusting module is used for receiving the first voltage signal to control the signal of the first node, and adjusting the signal of the first node according to the temperature or the illumination intensity; and the control module is used for receiving the signal of the first node and the second voltage signal, responding to the first control signal, the second control signal, the third control signal, the fourth control signal, the fifth control signal and the sixth control signal, and controlling the signal of the second node, wherein the signal of the second node is an output signal.
Based on the same idea, the invention also provides a display device which comprises the adjusting circuit.
Compared with the prior art, the adjusting circuit and the display device provided by the invention at least realize the following beneficial effects:
the adjusting circuit provided by the invention comprises a voltage adjusting module and a control module, wherein the voltage adjusting module is used for receiving a first voltage signal to control a signal of a first node, and the voltage adjusting module adjusts the signal of the first node according to temperature or illumination intensity, namely when the external temperature or the external illumination intensity changes, the signal of the first node also changes. The control module is used for receiving the signal of the first node and the second voltage signal, responding to a first control signal, a second control signal, a third control signal, a fourth control signal, a fifth control signal and a sixth control signal, and controlling the signal of the second node, wherein the signal of the second node is an output signal. The generation of output signal is based on the signal and the second voltage signal of first node, the generation of the signal of first node is based on first voltage signal, and the signal of first node changes along with ambient temperature or external illumination intensity change, thereby output signal also corresponding changes along with ambient temperature or external illumination intensity change, promptly adjusting circuit can adjust output signal according to ambient temperature or external illumination intensity, can promote the flexibility of adjusting circuit output signal, when being used for driving voltage with adjusting circuit's output signal, adjusting circuit can adjust driving voltage according to ambient temperature or external illumination intensity, need not always with the highest voltage signal as driving voltage, effectively reduce the consumption.
Of course, it is not necessary for any product in which the present invention is practiced to specifically achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic diagram of a frame structure of a regulating circuit according to the present invention;
FIG. 2 is a schematic diagram of a frame structure of another regulating circuit provided by the present invention;
FIG. 3 is a schematic diagram of a frame structure of another regulating circuit provided by the present invention;
FIG. 4 is a schematic diagram of a frame structure of another regulating circuit provided by the present invention;
FIG. 5 is a schematic diagram of a frame structure of another regulating circuit provided by the present invention;
FIG. 6 is a schematic diagram of a frame structure of another regulating circuit provided by the present invention;
FIG. 7 is a schematic diagram of a frame structure of another regulating circuit provided by the present invention;
FIG. 8 is a circuit schematic of yet another regulation circuit provided by the present invention;
FIG. 9 is a circuit schematic of yet another regulation circuit provided by the present invention;
FIG. 10 is a timing diagram for driving the regulating circuit according to the present invention;
FIG. 11 is another driving timing diagram of the regulating circuit provided by the present invention;
FIG. 12 is a timing diagram illustrating further driving of the regulator circuit according to the present invention;
FIG. 13 is a timing diagram illustrating further driving of the regulator circuit according to the present invention;
FIG. 14 is a schematic plan view of a display device according to the present invention;
FIG. 15 is a schematic structural diagram of another display panel provided in the present invention;
FIG. 16 is a circuit schematic of yet another regulation circuit provided by the present invention;
fig. 17 is a circuit schematic of yet another regulation circuit provided by the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Fig. 1 is a schematic diagram of a frame structure of a regulating circuit provided in the present invention, and referring to fig. 1, the present embodiment provides a regulating circuit including a voltage regulating module 10 and a control module 20.
The voltage adjusting module 10 is configured to receive the first voltage signal VA to control a signal of the first node a, and the voltage adjusting module 10 adjusts the signal of the first node a according to the temperature or the illumination intensity, that is, when the external temperature or the external illumination intensity changes, the signal of the first node a also changes.
The control module 20 is configured to receive the signal of the first node a and the second voltage signal VB, and control the signal of the second node B in response to the first control signal K1, the second control signal K2, the third control signal K3, the fourth control signal K4, the fifth control signal K5, and the sixth control signal K6, where the signal of the second node B is the output signal OUT.
The generation of output signal OUT is based on the signal of first node A and second voltage signal VB, the generation of the signal of first node A is based on first voltage signal VA, and the signal of first node A changes along with ambient temperature or ambient light intensity change to output signal OUT also corresponding changes along with ambient temperature or ambient light intensity change, promptly adjusting circuit can adjust output signal OUT according to ambient temperature or ambient light intensity, can promote the flexibility of adjusting circuit output signal. When the output signal OUT of the adjusting circuit is used for driving voltage, the adjusting circuit can adjust the driving voltage according to the external temperature or the external illumination intensity, the highest voltage signal VGH is not required to be used as the driving voltage all the time, and the power consumption is effectively reduced.
Optionally, the upper limit potential of the output signal OUT of the adjusting circuit is smaller than the potential of the highest voltage signal VGH, the lower limit potential of the output signal OUT of the adjusting circuit can be set according to actual production needs, correspondingly, the potentials of the first voltage signal VA and the second voltage signal VB are both smaller than the potential of the highest voltage signal VGH, the potentials of the first voltage signal VA and the second voltage signal VB are set according to actual production needs, and the potentials of the first voltage signal VA and the second voltage signal VB can be the same or different.
Fig. 2 is a schematic diagram of a frame structure of another regulating circuit provided by the present invention, and referring to fig. 2, in some alternative embodiments, the voltage regulating module 10 includes a first resistor R1 and a second resistor R2.
The first end of the first resistor R1 receives a first voltage signal VA, the second end of the first resistor R1 is connected to a first node a, the first end of the second resistor R2 is connected to the first node a, the second end of the second resistor R2 is connected to ground, the signal of the first node a is VA × [ R2/(R1+ R2) ], and the signal of the first node a is influenced by the first resistor R1 and the second resistor R2.
In the voltage regulating module 10, the first resistor R1 or the second resistor R2 is a variable resistor, so that the voltage regulating module 10 regulates the signal of the first node a according to the temperature or the illumination intensity.
In some alternative embodiments, the variable resistor is a thermistor. Referring to fig. 3, fig. 3 is a schematic diagram of a frame structure of another regulating circuit according to the present invention, in which the second resistor R2 is a thermistor, when the external temperature increases, the resistance of the second resistor R2 decreases, so that the potential of the first node a decreases, and when the external temperature decreases, the resistance of the second resistor R2 increases, so that the potential of the first node a increases.
It should be noted that fig. 3 exemplarily shows that the second resistor R2 is a thermistor, and in other embodiments of the present invention, the first resistor R1 may also be a thermistor. It is also possible that the first resistor R1 and the second resistor R2 are both provided as thermistors.
In some alternative embodiments, the variable resistor is a photo-resistor. Referring to fig. 4, fig. 4 is a schematic diagram of a frame structure of another adjusting circuit provided by the present invention, in which the second resistor R2 is a photo-sensitive resistor, when the external illumination intensity increases, the resistance of the second resistor R2 decreases, so that the potential of the first node a decreases, and when the external illumination intensity decreases, the resistance of the second resistor R2 increases, so that the potential of the first node a increases.
It should be noted that, fig. 4 exemplarily shows that the second resistor R2 is a photo-resistor, and in other embodiments of the present invention, the first resistor R1 may also be configured as a photo-resistor.
Fig. 5 is a schematic diagram of a frame structure of another regulating circuit provided by the present invention, and referring to fig. 5, in some alternative embodiments, the regulating circuit further includes a voltage stabilizing unit 30, the voltage stabilizing unit 30 is connected to the second node B, and the voltage stabilizing unit 30 is configured to stabilize a signal of the second node B, i.e., stabilize the output signal OUT.
Fig. 6 is a schematic diagram of a frame structure of a further regulating circuit provided by the present invention, and referring to fig. 6, in some alternative embodiments, the voltage stabilizing unit 30 includes a third capacitor C3, a first plate of the third capacitor C3 is grounded, and a second plate of the third capacitor C3 is connected to a second node B, which effectively stabilizes a signal at the second node B due to a holding effect of the third capacitor C3, and the signal at the second node B is an output signal OUT, i.e., a stabilized output signal OUT.
Fig. 7 is a schematic diagram of a frame structure of another regulating circuit provided by the present invention, and referring to fig. 7, in some alternative embodiments, the control module 20 includes a first control unit 21 and a second control unit 22.
Wherein the first control unit 21 is configured to receive the signal of the first node a and the second voltage signal VB, and control the signal of the second node B in response to the first control signal K1, the third control signal K3 and the fifth control signal K5 during the first period; the second control unit 22 is for receiving the signal of the first node a and the second voltage signal VB, and controlling the signal of the second node B in the second period in response to the second control signal K2, the fourth control signal K4 and the sixth control signal K6. Therefore, the control module 20 controls the second node B to continuously output the output signal OUT in the first period and the second period, so that the output signal OUT of the regulating circuit can be used for a high-potential signal of a gate driving circuit, a driving signal of a light source and other circuit structures or electronic elements needing continuous signals.
Fig. 8 is a circuit schematic diagram of another regulating circuit provided by the present invention, and referring to fig. 8, in some alternative embodiments, the first control unit 21 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 and a first capacitor C1.
A gate of the first transistor T1 receives the first control signal K1, a source of the first transistor T1 is grounded, and a drain of the first transistor T1 is connected to the third node D; a gate of the second transistor T2 receives the first control signal K1, a source of the second transistor T2 is connected to the first node a, and a drain of the second transistor T2 is connected to the third node D; a gate of the third transistor T3 receives the third control signal K3, a source of the third transistor T3 receives the second voltage signal VB, and a drain of the third transistor T3 is connected to the fourth node E; a gate of the fourth transistor T4 receives the fifth control signal K5, a source of the fourth transistor T4 is connected to the fourth node E, and a drain of the fourth transistor T4 is connected to the second node B; the first plate of the first capacitor C1 is connected to the third node D, and the second plate of the first capacitor C1 is connected to the fourth node E. The first control unit 21 is used to control the signals of the second node B during a first period.
The second control unit 22 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a second capacitor C2.
A gate of the fifth transistor T5 receives the second control signal K2, a source of the fifth transistor T5 is grounded, and a drain of the fifth transistor T5 is connected to the fifth node F; a gate of the sixth transistor T6 receives the second control signal K2, a source of the sixth transistor T6 is connected to the first node a, and a drain of the sixth transistor T6 is connected to the fifth node F; a gate of the seventh transistor T7 receives the fourth control signal K4, a source of the seventh transistor T7 receives the second voltage signal VB, and a drain of the seventh transistor T7 is connected to the sixth node G; a gate of the eighth transistor T8 receives the sixth control signal K6, a source of the eighth transistor T8 is connected to the sixth node G, and a drain of the eighth transistor T8 is connected to the second node B; the first plate of the second capacitor C2 is connected to the fifth node F, and the second plate of the second capacitor C2 is connected to the sixth node G. The second control unit 22 is used to control the signal of the second node B during the second period.
In some alternative embodiments, the first transistor and the fifth transistor are of the same type, the second transistor and the sixth transistor are of the same type, the first transistor and the second transistor are of different types, the fifth transistor and the sixth transistor are of different types, the first transistor and the second transistor are alternately turned on, and the fifth transistor and the sixth transistor are alternately turned on. The first control unit 21 controls the signal of the second node B in the first period, the second control unit 22 controls the signal of the second node B in the second period, and the control module 20 controls the second node B to continuously output the output signal OUT in the first period and the second period, so that the output signal OUT of the regulating circuit can be used for a high-potential signal of a gate driving circuit, a driving signal of a light source and other circuit structures or electronic elements needing continuous signals.
Illustratively, with continued reference to fig. 8, the first transistor T1 and the fifth transistor T5 are P-type transistors, the second transistor T2 and the sixth transistor T6 are N-type transistors, and when the first control signal K1 is high, the second control signal K2 is low, the first transistor T1 is off, the second transistor T2 is on, the fifth transistor T5 is on, and the sixth transistor T6 is off; when the first control signal K1 is at a low level, the second control signal K2 is at a high level, the first transistor T1 is turned on, the second transistor T2 is turned off, the fifth transistor T5 is turned off, and the sixth transistor T6 is turned on, so that the second transistor T2 and the sixth transistor T6 are alternately turned on.
Similarly, it can also be set as: the first transistor and the fifth transistor are P-type transistors, and the second transistor and the sixth transistor are N-type transistors, which are not described again herein.
In some alternative embodiments, the third and seventh transistors are of the same type.
Illustratively, with continued reference to fig. 8, the third transistor T3 and the seventh transistor T7 are both N-type transistors, and when the third control signal K3 is high, the fourth control signal K4 is low, the third transistor T3 is turned on, and the seventh transistor T7 is turned off; when the third control signal K3 is at a low level, the fourth control signal K4 is at a high level, the third transistor T3 is turned off, the seventh transistor T7 is turned on, and the third transistor T3 and the seventh transistor T7 are alternately turned on.
Similarly, it can also be set as: the third transistor and the seventh transistor are both P-type transistors, and the description of the invention is omitted here.
In some alternative embodiments, the first transistor and the sixth transistor are of the same type, the second transistor and the fifth transistor are of the same type, the first transistor and the second transistor are of different types, the fifth transistor and the sixth transistor are of different types, the first transistor and the second transistor are alternately turned on, and the fifth transistor and the sixth transistor are alternately turned on.
Exemplarily, with continuing reference to fig. 9, fig. 9 is a circuit schematic diagram of another regulating circuit provided by the present invention, where the first transistor T1 and the sixth transistor T6 are P-type transistors, the second transistor T2 and the fifth transistor T5 are N-type transistors, when the first control signal K1 is at a high level, the second control signal K2 is at a high level, the first transistor T1 is turned off, the second transistor T2 is turned on, the fifth transistor T5 is turned on, and the sixth transistor T6 is turned off; when the first control signal K1 is at a low level, the second control signal K2 is at a low level, the first transistor T1 is turned on, the second transistor T2 is turned off, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the second control signal K2 multiplexes the first control signal K1, so that the second transistor T2 and the sixth transistor T6 are alternately turned on, the setting of the control signals is effectively reduced, the complexity of the circuit is reduced, and the wiring difficulty is reduced.
Similarly, it can also be set as: the first transistor and the sixth transistor are N-type transistors, the second transistor and the fifth transistor are P-type transistors, and at this time, the second control signal may also multiplex the first control signal, which is not described herein again.
In some alternative embodiments, the third transistor and the seventh transistor are of different types, the third transistor is one of an N-type transistor and a P-type transistor, the seventh transistor is the other of the N-type transistor and the P-type transistor, and the fourth control signal multiplexes the third control signal.
Illustratively, with continued reference to fig. 9, the third transistor T3 is an N-type transistor, the seventh transistor T7 is a P-type transistor, and when the third control signal K3 is high, the fourth control signal K4 is high, the third transistor T3 is turned on, and the seventh transistor T7 is turned off; when the third control signal K3 is at a low level, the fourth control signal K4 is at a low level, the third transistor T3 is turned off, the seventh transistor T7 is turned on, and the fourth control signal K4 can reuse the third control signal K3, so that the third transistor T3 and the seventh transistor T7 are turned on alternately, the setting of the control signals is effectively reduced, the complexity of the circuit is reduced, and the difficulty of wire arrangement is reduced.
Similarly, it can also be set as: the third transistor T3 is a P-type transistor, and the seventh transistor T7 is an N-type transistor, which will not be described herein again.
In some alternative embodiments, the fourth transistor and the eighth transistor are of the same type, and both the fourth transistor and the eighth transistor may be N-type transistors or both P-type transistors.
Illustratively, with continued reference to fig. 8, the fourth transistor T4 and the eighth transistor T8 are both N-type transistors, and when the fifth control signal K5 is high, the sixth control signal K6 is low, the fourth transistor T4 is turned on, and the eighth transistor T8 is turned off; when the fifth control signal K5 is at a low level, the sixth control signal K6 is at a high level, the fourth transistor T4 is turned off, the eighth transistor T8 is turned on, and the fourth transistor T4 and the eighth transistor T8 are alternately turned on.
Similarly, it can also be set as: the fourth transistor and the eighth transistor are both P-type transistors, and the description of the invention is omitted here.
The operation of the regulating circuit according to the invention will be described below with reference to the timing diagrams of the signals in the regulating circuit.
Fig. 10 is a driving timing diagram of the regulating circuit according to the present invention, please refer to fig. 8 and fig. 10. The second resistor R2 is a thermistor, and the potential of the first node a is a1 at the first temperature.
At the stage T1, the first control signal K1 is at a high level, the first transistor T1 is turned off, the second transistor T2 is turned on, the signal of the first node a is transmitted to the third node D, and the signal of the third node D is a 1. The third control signal K3 is at a low level, the third transistor T3 is turned off, and before the third transistor T3 is turned off, the signal of the fourth node E is the second voltage signal VB, the signal of the third node D is the ground signal GND, and the signal of the third node D rises to a1 in the period T1, so that the potential of the fourth node E is coupled to a1+ VB by the first capacitor C1. The fifth control signal K5 is at high level, the fourth transistor T4 is turned on, the signal of the fourth node E is transmitted to the second node B, and the potential of the second node B is a1+ VB, so that the output signal OUT is a1+ VB.
The second control signal K2 is at a low level, the fifth transistor T5 is turned on, the sixth transistor T6 is turned off, the ground signal GND is transmitted to the fifth node F, and the signal at the fifth node F is the ground signal GND. The fourth control signal K4 is at a high level, the seventh transistor T7 is turned on, and the signal at the sixth node G is the second voltage signal VB. The sixth control signal K6 is low, the eighth transistor T8 is turned off, and the signal at the sixth node G does not affect the signal at the second node B.
At the stage T2, the second control signal K2 is at high level, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, the signal at the first node a is transmitted to the fifth node F, and the signal at the fifth node F is a 1. Since the fourth control signal K4 is at a low level and the seventh transistor T7 is turned off, the signal at the sixth node G is the second voltage signal VB and the signal at the fifth node F is the ground signal GND before the seventh transistor T7 is turned off, and the signal at the fifth node F rises to a1 in the period T2, the potential of the sixth node G is coupled to a1+ VB by the second capacitor C2. The sixth control signal K6 is at a high level, the eighth transistor T8 is turned on, and the signal of the sixth node G is transmitted to the second node B at a potential of a1+ VB, so that the output signal OUT is a1+ VB.
The first control signal K1 is at a low level, the first transistor T1 is turned on, the second transistor T2 is turned off, and the ground signal GND is transmitted to the third node D. The third control signal K3 is at a high level, the third transistor T3 is turned on, and the signal of the fourth node E is the second voltage signal VB. The fifth control signal K5 is low, the fourth transistor T4 is turned off, and the signal at the fourth node E does not affect the signal at the second node B.
Thus, at the first temperature, the t1 phase and the t2 phase alternate, and the output signal OUT is always A1+ VB.
Fig. 11 is another driving timing diagram of the adjusting circuit according to the present invention, please refer to fig. 8 and fig. 11. At the second temperature, the potential of the first node a is a 2.
At the stage T1, the first control signal K1 is at a high level, the first transistor T1 is turned off, the second transistor T2 is turned on, the signal of the first node a is transmitted to the third node D, and the signal of the third node D is a 2. The third control signal K3 is at a low level, the third transistor T3 is turned off, and before the third transistor T3 is turned off, the signal of the fourth node E is the second voltage signal VB, the signal of the third node D is the ground signal GND, and the signal of the third node D rises to a2 in the period T1, so that the potential of the fourth node E is coupled to a2+ VB by the first capacitor C1. The fifth control signal K5 is at high level, the fourth transistor T4 is turned on, the signal of the fourth node E is transmitted to the second node B, and the potential of the second node B is a2+ VB, so that the output signal OUT is a2+ VB.
The second control signal K2 is at a low level, the fifth transistor T5 is turned on, the sixth transistor T6 is turned off, the ground signal GND is transmitted to the fifth node F, and the signal at the fifth node F is the ground signal GND. The fourth control signal K4 is at a high level, the seventh transistor T7 is turned on, and the signal at the sixth node G is the second voltage signal VB. The sixth control signal K6 is low, the eighth transistor T8 is turned off, and the signal at the sixth node G does not affect the signal at the second node B.
At the stage T2, the second control signal K2 is at high level, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, the signal at the first node a is transmitted to the fifth node F, and the signal at the fifth node F is a 2. Since the fourth control signal K4 is at a low level and the seventh transistor T7 is turned off, the signal at the sixth node G is the second voltage signal VB and the signal at the fifth node F is the ground signal GND before the seventh transistor T7 is turned off, and the signal at the fifth node F rises to a2 in the period T2, the potential of the sixth node G is coupled to a2+ VB by the second capacitor C2. The sixth control signal K6 is at a high level, the eighth transistor T8 is turned on, and the signal of the sixth node G is transmitted to the second node B at a potential of a2+ VB, so that the output signal OUT is a2+ VB.
The first control signal K1 is at a low level, the first transistor T1 is turned on, the second transistor T2 is turned off, and the ground signal GND is transmitted to the third node D. The third control signal K3 is at a high level, the third transistor T3 is turned on, and the signal of the fourth node E is the second voltage signal VB. The fifth control signal K5 is low, the fourth transistor T4 is turned off, and the signal at the fourth node E does not affect the signal at the second node B.
Thus, at the second temperature, the t1 phase and the t2 phase alternate, and the output signal OUT is always A2+ VB.
Referring to fig. 8, the signal of the first node a is VA × [ R2/(R1+ R2) ], the second resistor R2 is a thermistor, when the external environment temperature increases, the resistance value of the second resistor R2 decreases, so that the potential of the first node a decreases, the potential of the output signal OUT decreases, when the external environment temperature decreases, the resistance value of the second resistor R2 increases, so that the potential of the first node a increases, and the potential of the output signal OUT increases. When the output signal OUT of the adjusting circuit is used for driving voltage, the adjusting circuit can adjust the driving voltage according to the external temperature or the external illumination intensity, the highest voltage signal VGH is not required to be used as the driving voltage all the time, and the power consumption is effectively reduced. Illustratively, when the first temperature is greater than the second temperature, the resistance of the second resistor R2 at the first temperature is less than the resistance of the second resistor R2 at the second temperature, such that the potential a1 at the first node a at the first temperature is less than the potential a2 at the second temperature. It should be noted that, in this embodiment, the potential of the first node a is exemplarily shown at the first temperature and the second temperature, and at other temperatures, the potential of the first node a changes correspondingly with the temperature, which is not described herein again.
It is understood that, when the second resistor is a photo-resistor, the timing sequence of each signal of the adjusting circuit can refer to the timing sequence of fig. 10 and 11, and the description of the present invention is omitted here.
In some alternative embodiments, during the period T1, the sixth control signal K6 controls the eighth transistor T8 to be turned off for a longer time than the fifth control signal K5 controls the fourth transistor T4 to be turned on, and the fifth control signal K5 controls the fourth transistor T4 to be turned on after the first control signal K1 controls the second transistor T2 to be turned on, and the first control signal K1 controls the second transistor T2 to be turned off after the fifth control signal K5 controls the fourth transistor T4 to be turned off; at the stage T2, the fifth control signal K5 controls the fourth transistor T4 to be turned off for a time longer than the sixth control signal K6 controls the eighth transistor T8 to be turned on, the sixth control signal K6 controls the eighth transistor T8 to be turned on after the sixth transistor T6 is controlled to be turned on by the second control signal K2, and the sixth transistor T6 is controlled to be turned off by the second control signal K2 after the eighth transistor T8 is controlled to be turned off by the sixth control signal K6, so as to ensure that the output signal OUT always keeps VA × [ R2/(R1+ R2) ] + VB.
Fig. 12 is a timing diagram of another driving method of the adjusting circuit according to the present invention, please refer to fig. 9 and 12. At the first temperature, the potential of the first node a is a 1.
At the stage T1, the first control signal K1 is at a high level, the first transistor T1 is turned off, the second transistor T2 is turned on, the signal of the first node a is transmitted to the third node D, and the signal of the third node D is a 1. The third control signal K3 is at a low level, the third transistor T3 is turned off, and before the third transistor T3 is turned off, the signal of the fourth node E is the second voltage signal VB, the signal of the third node D is the ground signal GND, and the signal of the third node D rises to a1 in the period T1, so that the potential of the fourth node E is coupled to a1+ VB by the first capacitor C1. The fifth control signal K5 is at high level, the fourth transistor T4 is turned on, the signal of the fourth node E is transmitted to the second node B, and the potential of the second node B is a1+ VB, so that the output signal OUT is a1+ VB.
The first control signal K1 is at a high level, the fifth transistor T5 is turned on, the sixth transistor T6 is turned off, the ground signal GND is transmitted to the fifth node F, and the signal at the fifth node F is the ground signal GND. The third control signal K3 is at low level, the seventh transistor T7 is turned on, and the signal at the sixth node G is the second voltage signal VB. The sixth control signal K6 is low, the eighth transistor T8 is turned off, and the signal at the sixth node G does not affect the signal at the second node B.
At the stage T2, the first control signal K1 is low, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, the signal at the first node a is transmitted to the fifth node F, and the signal at the fifth node F is a 1. Since the third control signal K3 is at a high level and the seventh transistor T7 is turned off, the signal of the sixth node G is the second voltage signal VB and the signal of the fifth node F is the ground signal GND before the seventh transistor T7 is turned off, and the signal of the fifth node F rises to a1 at the T2 stage, the potential of the sixth node G is coupled to a1+ VB by the second capacitor C2. The sixth control signal K6 is at a high level, the eighth transistor T8 is turned on, and the signal of the sixth node G is transmitted to the second node B at a potential of a1+ VB, so that the output signal OUT is a1+ VB.
The first control signal K1 is at a low level, the first transistor T1 is turned on, the second transistor T2 is turned off, and the ground signal GND is transmitted to the third node D. The third control signal K3 is at a high level, the third transistor T3 is turned on, and the signal of the fourth node E is the second voltage signal VB. The fifth control signal K5 is low, the fourth transistor T4 is turned off, and the signal at the fourth node E does not affect the signal at the second node B.
Thus, at the first temperature, the t1 phase and the t2 phase alternate, and the output signal OUT is always A1+ VB.
Fig. 13 is a timing diagram of another driving method of the adjusting circuit according to the present invention, please refer to fig. 8 and fig. 13. At the second temperature, the potential of the first node a is a 2.
At the stage T1, the first control signal K1 is at a high level, the first transistor T1 is turned off, the second transistor T2 is turned on, the signal of the first node a is transmitted to the third node D, and the signal of the third node D is a 2. The third control signal K3 is at a low level, the third transistor T3 is turned off, and before the third transistor T3 is turned off, the signal of the fourth node E is the second voltage signal VB, the signal of the third node D is the ground signal GND, and the signal of the third node D rises to a2 in the period T1, so that the potential of the fourth node E is coupled to a2+ VB by the first capacitor C1. The fifth control signal K5 is at high level, the fourth transistor T4 is turned on, the signal of the fourth node E is transmitted to the second node B, and the potential of the second node B is a2+ VB, so that the output signal OUT is a2+ VB.
The first control signal K1 is at a high level, the fifth transistor T5 is turned on, the sixth transistor T6 is turned off, the ground signal GND is transmitted to the fifth node F, and the signal at the fifth node F is the ground signal GND. The third control signal K3 is at low level, the seventh transistor T7 is turned on, and the signal at the sixth node G is the second voltage signal VB. The sixth control signal K6 is low, the eighth transistor T8 is turned off, and the signal at the sixth node G does not affect the signal at the second node B.
At the stage T2, the first control signal K1 is low, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, the signal at the first node a is transmitted to the fifth node F, and the signal at the fifth node F is a 2. Since the third control signal K3 is at a high level and the seventh transistor T7 is turned off, the signal of the sixth node G is the second voltage signal VB and the signal of the fifth node F is the ground signal GND before the seventh transistor T7 is turned off, and the signal of the fifth node F rises to a2 at the T2 stage, the potential of the sixth node G is coupled to a2+ VB by the second capacitor C2. The sixth control signal K6 is at a high level, the eighth transistor T8 is turned on, and the signal of the sixth node G is transmitted to the second node B at a potential of a2+ VB, so that the output signal OUT is a2+ VB.
The first control signal K1 is at a low level, the first transistor T1 is turned on, the second transistor T2 is turned off, and the ground signal GND is transmitted to the third node D. The third control signal K3 is at a high level, the third transistor T3 is turned on, and the signal of the fourth node E is the second voltage signal VB. The fifth control signal K5 is low, the fourth transistor T4 is turned off, and the signal at the fourth node E does not affect the signal at the second node B.
Thus, at the second temperature, the t1 phase and the t2 phase alternate, and the output signal OUT is always A2+ VB.
In some optional embodiments, please refer to fig. 14, fig. 14 is a schematic plan view of a display device provided in the present invention, and the display device 1000 provided in the present embodiment includes the adjusting circuit provided in the above embodiments of the present invention. The embodiment of fig. 14 only uses a mobile phone as an example to describe the display device 1000, and it should be understood that the display device 1000 provided in the embodiment of the present invention may also be another display device 1000 having a display function, such as a computer, a television, a vehicle-mounted display device, and the present invention is not limited thereto. The display device 1000 provided in the embodiment of the present invention has the beneficial effects of the adjusting circuit provided in the embodiment of the present invention, and specific reference may be made to the specific description of the adjusting circuit in each of the above embodiments, which is not described herein again.
Fig. 15 is a schematic structural diagram of another display panel provided in the present invention, and referring to fig. 8 and fig. 15, in some alternative embodiments, the display device further includes a gate driving circuit 200, the gate driving circuit 200 is configured to provide a driving signal to the gate line g, the adjusting circuit 100 is electrically connected to the gate driving circuit 200, an output signal OUT of the adjusting circuit 100 is used as a high-potential signal provided to the gate driving circuit 200, and the high-potential signal of the gate driving circuit 200 is used to generate the driving signal of the gate line g.
In the regulating circuit 100, the voltage regulating module 10 includes a first resistor R1 and a second resistor R2, a first end of the first resistor R1 receives the first voltage signal VA, a second end of the first resistor R1 is connected to a first node a, a first end of the second resistor R2 is connected to the first node a, a second end of the second resistor R2 is grounded, and the second resistor R2 is a thermistor.
When the external ambient temperature rises, the resistance value of the second resistor R2 decreases, so that the potential of the first node a decreases, so that the potential of the output signal OUT decreases, and when the external ambient temperature falls, the resistance value of the second resistor R2 increases, so that the potential of the first node a increases, so that the potential of the output signal OUT increases. Accordingly, the adjusting circuit 100 can adjust the high-potential signal provided to the gate driving circuit 200 according to the external temperature, when the external temperature is lowered, the potential of the high-potential signal provided to the gate driving circuit 200 is increased, and when the external temperature is raised, the potential of the high-potential signal provided to the gate driving circuit 200 is decreased, so that the highest voltage signal VGH is not required to be used as the high-potential signal of the gate driving circuit 200 all the time in order to satisfy that the driving signals provided to the gate line g at different temperatures can normally drive the pixel, thereby effectively reducing the power consumption of the display device.
With continued reference to fig. 14, in some alternative embodiments, the display device 1000 may be a reflective display device that does not require the use of a backlight, effectively reducing the power consumption of the display device. It should be noted that, in other embodiments of the present invention, the display device may also be other types of display devices, and the description of the present invention is omitted here.
With continued reference to fig. 14, in some alternative embodiments, when the display device is a reflective display device, the visibility of the display device may be greatly reduced when the ambient light is low, and therefore, in order not to affect the display screen, the display device further includes a front light source (not shown in fig. 14). Referring to fig. 16, fig. 16 is a circuit schematic diagram of another adjusting circuit provided by the present invention, the adjusting circuit is electrically connected to the front light source 300, the output signal OUT of the adjusting circuit 100 is used as a signal provided to the front light source 300, in the adjusting circuit, the voltage adjusting module 10 includes a first resistor R1 and a second resistor R2, a first end of the first resistor R1 receives the first voltage signal VA, a second end of the first resistor R1 is connected to the first node a, a first end of the second resistor R2 is connected to the first node a, a second end of the second resistor R2 is grounded, and the second resistor R2 is a photo resistor.
When the intensity of the external light is increased, the resistance value of the second resistor R2 is decreased, so that the potential of the first node a is decreased, so that the potential of the output signal OUT is decreased, and when the intensity of the external light is decreased, the resistance value of the second resistor R2 is increased, so that the potential of the first node a is increased, so that the potential of the output signal OUT is increased. Accordingly, the adjusting circuit may adjust the signal provided to the front light 300 according to the external illumination intensity, and when the external illumination intensity decreases, the potential of the signal provided to the front light 300 increases, and when the external illumination intensity increases, the potential of the signal provided to the front light 300 decreases, thereby reducing the influence of the external illumination intensity on the display screen of the display device.
With continued reference to fig. 14, in some alternative embodiments, the display device further includes a backlight source (not shown in fig. 14), and when the illumination intensity is higher, the brightness of the backlight source needs to be increased, so as to reduce the influence on the display screen of the display device.
Referring to fig. 17, fig. 17 is a circuit schematic diagram of another adjusting circuit according to the present invention, the adjusting circuit is electrically connected to a backlight 400, an output signal OUT of the adjusting circuit 100 is used as a signal provided to the backlight 400, in the adjusting circuit, the voltage adjusting module 10 includes a first resistor R1 and a second resistor R2, a first end of the first resistor R1 receives a first voltage signal VA, a second end of the first resistor R1 is connected to a first node a, a first end of the second resistor R2 is connected to the first node a, a second end of the second resistor R2 is connected to ground, and the first resistor R1 is a photo resistor.
When the external light intensity increases, the resistance value of the first resistor R1 decreases, so that the potential of the first node a increases, so that the potential of the output signal OUT increases, and when the external light intensity decreases, the resistance value of the first resistor R1 increases, so that the potential of the first node a decreases, so that the potential of the output signal OUT decreases. Accordingly, the adjusting circuit may adjust the signal provided to the backlight 400 according to the external illumination intensity, and when the external illumination intensity increases, the potential of the signal provided to the backlight 400 increases, and when the external illumination intensity decreases, the potential of the signal provided to the backlight 400 decreases, thereby reducing the influence of the external illumination intensity on the display screen of the display device.
By the above embodiments, the adjusting circuit and the display device provided by the invention at least achieve the following beneficial effects:
the adjusting circuit provided by the invention comprises a voltage adjusting module and a control module, wherein the voltage adjusting module is used for receiving a first voltage signal to control a signal of a first node, and the voltage adjusting module adjusts the signal of the first node according to temperature or illumination intensity, namely when the external temperature or the external illumination intensity changes, the signal of the first node also changes. The control module is used for receiving the signal of the first node and the second voltage signal, responding to a first control signal, a second control signal, a third control signal, a fourth control signal, a fifth control signal and a sixth control signal, and controlling the signal of the second node, wherein the signal of the second node is an output signal. The generation of output signal is based on the signal and the second voltage signal of first node, the generation of the signal of first node is based on first voltage signal, and the signal of first node changes along with ambient temperature or external illumination intensity change, thereby output signal also corresponding changes along with ambient temperature or external illumination intensity change, promptly adjusting circuit can adjust output signal according to ambient temperature or external illumination intensity, can promote the flexibility of adjusting circuit output signal, when being used for driving voltage with adjusting circuit's output signal, adjusting circuit can adjust driving voltage according to ambient temperature or external illumination intensity, need not always with the highest voltage signal as driving voltage, effectively reduce the consumption.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (17)
1. A regulation circuit, comprising:
the voltage regulation module is used for receiving a first voltage signal to control a signal of a first node, and the voltage regulation module regulates the signal of the first node according to temperature or illumination intensity;
and the control module is used for receiving the signal of the first node and the second voltage signal, responding to a first control signal, a second control signal, a third control signal, a fourth control signal, a fifth control signal and a sixth control signal, and controlling the signal of the second node, wherein the signal of the second node is an output signal.
2. The regulation circuit of claim 1,
the voltage regulating module comprises a first resistor and a second resistor;
a first end of the first resistor receives the first voltage signal, and a second end of the first resistor is connected to the first node;
a first end of the second resistor is connected to the first node, and a second end of the second resistor is grounded;
the first resistance or the second resistance is a variable resistance.
3. The regulation circuit of claim 2,
the variable resistor is a thermistor or a photoresistor.
4. The regulation circuit of claim 1,
the control module comprises a first control unit and a second control unit;
the first control unit is configured to receive the signal of the first node and the second voltage signal, and control the signal of the second node in response to the first control signal, the third control signal, and the fifth control signal for a first period;
the second control unit is configured to receive the signal of the first node and the second voltage signal, and control the signal of the second node in a second period in response to the second control signal, the fourth control signal, and the sixth control signal.
5. The regulation circuit of claim 4,
the first control unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a first capacitor;
the grid electrode of the first transistor receives the first control signal, the source electrode of the first transistor is grounded, and the drain electrode of the first transistor is connected to a third node;
a gate of the second transistor receives the first control signal, a source of the second transistor is connected to the first node, and a drain of the second transistor is connected to the third node;
a gate of the third transistor receives the third control signal, a source of the third transistor receives the second voltage signal, and a drain of the third transistor is connected to a fourth node;
a gate of the fourth transistor receives the fifth control signal, a source of the fourth transistor is connected to the fourth node, and a drain of the fourth transistor is connected to the second node;
a first plate of the first capacitor is connected to the third node, and a second plate of the first capacitor is connected to the fourth node;
the second control unit comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a second capacitor;
a grid electrode of the fifth transistor receives the second control signal, a source electrode of the fifth transistor is grounded, and a drain electrode of the fifth transistor is connected to a fifth node;
a gate of the sixth transistor receives the second control signal, a source of the sixth transistor is connected to the first node, and a drain of the sixth transistor is connected to the fifth node;
a gate of the seventh transistor receives the fourth control signal, a source of the seventh transistor receives the second voltage signal, and a drain of the seventh transistor is connected to a sixth node;
a gate of the eighth transistor receives the sixth control signal, a source of the eighth transistor is connected to the sixth node, and a drain of the eighth transistor is connected to the second node;
the first plate of the second capacitor is connected to the fifth node, and the second plate of the second capacitor is connected to the sixth node.
6. The regulation circuit of claim 5,
the first transistor and the fifth transistor are N-type transistors, and the second transistor and the sixth transistor are P-type transistors, or the first transistor and the fifth transistor are P-type transistors, and the second transistor and the sixth transistor are N-type transistors.
7. The regulation circuit of claim 5,
the first transistor and the sixth transistor are N-type transistors, and the second transistor and the fifth transistor are P-type transistors, or the first transistor and the sixth transistor are P-type transistors, and the second transistor and the fifth transistor are N-type transistors;
the second control signal multiplexes the first control signal.
8. The regulation circuit of claim 5,
the third transistor and the seventh transistor are both N-type transistors or P-type transistors.
9. The regulation circuit of claim 5,
the third transistor is one of an N-type transistor and a P-type transistor, and the seventh transistor is the other of the N-type transistor and the P-type transistor;
the fourth control signal multiplexes the third control signal.
10. The regulation circuit of claim 5,
the fourth transistor and the eighth transistor are both N-type transistors or P-type transistors.
11. The regulation circuit of claim 1 further comprising a voltage regulation unit, said voltage regulation unit coupled to said second node.
12. The regulation circuit of claim 11,
the voltage stabilizing unit comprises a third capacitor, a first polar plate of the third capacitor is grounded, and a second polar plate of the third capacitor is connected to the second node.
13. A display device comprising the adjusting circuit of any one of claims 1 to 12.
14. The display device according to claim 13, further comprising a gate driving circuit, wherein the adjusting circuit is electrically connected to the gate driving circuit;
the voltage regulating module comprises a first resistor and a second resistor;
a first end of the first resistor receives the first voltage signal, and a second end of the first resistor is connected to the first node;
a first end of the second resistor is connected to the first node, and a second end of the second resistor is grounded;
the second resistor is a thermistor.
15. The display device according to claim 13, further comprising a front light, wherein the adjusting circuit is electrically connected to the front light;
the voltage regulating module comprises a first resistor and a second resistor;
a first end of the first resistor receives the first voltage signal, and a second end of the first resistor is connected to the first node;
a first end of the second resistor is connected to the first node, and a second end of the second resistor is grounded;
the second resistor is a photoresistor.
16. The display device of claim 13, further comprising a backlight, the conditioning circuit being electrically connected to the backlight;
the voltage regulating module comprises a first resistor and a second resistor;
a first end of the first resistor receives the first voltage signal, and a second end of the first resistor is connected to the first node;
a first end of the second resistor is connected to the first node, and a second end of the second resistor is grounded;
the first resistor is a photoresistor.
17. A display device as claimed in claim 14 or 15, characterized in that the display device is a reflective display device.
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