CN112968894B

CN112968894B - Interface conversion device and computing equipment

Info

Publication number: CN112968894B
Application number: CN202110195735.4A
Authority: CN
Inventors: 武文雄
Original assignee: Beijing Wuxin Technology Co ltd
Current assignee: Beijing Wuxin Technology Co ltd
Priority date: 2021-02-19
Filing date: 2021-02-19
Publication date: 2022-08-16
Anticipated expiration: 2041-02-19
Also published as: CN112968894A; CN115190187A

Abstract

The application relates to an interface conversion device and a computing device. In an embodiment of the present application, the interface conversion apparatus may include: the LIN unit comprises a state machine and an LIN main node, the state machine is respectively connected with the LIN main node, the processor interface and the TAXI interface, the TAXI interface is connected with the state machine and the LIN main node and is externally connected with a TAXI bus, and the processor interface is respectively connected with the state machine and the LIN main node and is externally connected with a CPU. The embodiment of the application realizes the conversion of the Ethernet message and the LIN message through hardware, and can effectively improve the efficiency and save CPU resources.

Description

Interface conversion device and computing equipment

Technical Field

The present application relates to the field of data communication technologies, and in particular, to an interface conversion apparatus and a computing device.

Background

At present, interface conversion between a Local Interconnect Network (LIN) and an ethernet Network is mostly processed directly by using a CPU, and the architecture of the interface conversion is as shown in fig. 1, where the CPU parses an ethernet packet and then configures the ethernet packet to a LIN master node (LIN _ Core). Because the LIN interface is slow in speed and the Ethernet is fast in speed, the LIN main node needs to initiate interruption to the CPU for multiple times in the process of receiving and transmitting one Ethernet data packet so as to carry out intermediate processing, and the efficiency of the CPU is seriously influenced.

Disclosure of Invention

In view of the above problems in the prior art, the present application provides an interface conversion apparatus dedicated for conversion between an ethernet interface and an LIN interface, so as to implement conversion between an ethernet packet and an LIN packet through hardware, without requiring direct processing by a CPU, thereby effectively improving efficiency and saving CPU resources.

To achieve the above object, a first aspect of the present application provides an interface conversion apparatus, including: the local interconnect network system comprises at least one Local Interconnect Network (LIN) unit, a processor interface and a TAXI interface, wherein each LIN unit comprises a state machine and an LIN main node, the state machines are respectively connected with the LIN main node, the processor interface and the TAXI interface, the TAXI interface is connected with the state machines and the LIN main node and is externally connected with a TAXI bus at the same time, and the processor interface is respectively connected with the state machines and the LIN main node and is externally connected with a Central Processing Unit (CPU) at the same time;

the Ethernet message from the TAXI bus is received by the TAXI interface and an effective bearing part in the Ethernet message is cached according to the LIN number in the Ethernet message; the method comprises the steps that an effective bearing part in an Ethernet message enters a state machine in an LIN unit corresponding to an LIN number of the Ethernet message, the state machine configures an LIN main node in the LIN unit by analyzing the effective bearing part in the Ethernet message, the LIN main node returns LIN data corresponding to the Ethernet message to a TAXI interface after receiving and sending according to the configuration and LIN control information from a processor interface, and the TAXI interface utilizes the LIN data and the LIN control information corresponding to the LIN number from the processor interface to package the LIN message and sends the LIN message to the TAXI bus.

Therefore, conversion from the Ethernet message to the LIN message is realized through hardware, direct processing of a CPU is not needed, efficiency is effectively improved, and CPU resources are saved.

In at least some embodiments, the TAXI interface includes: a first buffer configured to buffer an active bearer portion in the Ethernet message according to a LIN number.

Therefore, parallel receiving and transmitting of multiple LINs are achieved, and competition risks caused by simultaneous receiving and transmitting of the multiple LINs are effectively reduced.

In at least some embodiments, the taii interface includes a second buffer configured to buffer the LIN messages according to the LIN numbers, so as to send the LIN messages of the at least one LIN unit in parallel.

Therefore, the parallel processing of the multiple LIN messages is realized, and the competition risk caused by the simultaneous receiving and transmitting of the multiple LINs is effectively reduced.

In at least some embodiments, the state machine is further configured to receive an interrupt initiated by the LIN master, send an interrupt message to the CPU through the processor interface when the interrupt indicates abnormal, and directly mask the interrupt message when the interrupt indicates normal.

Therefore, the influence on the CPU efficiency caused by multiple times of interrupt initiation of the LIN main node in the data receiving and transmitting process is effectively avoided.

In at least some embodiments, the processor interface is further configured to update the error flag to be an interrupt reset after receiving an interrupt recovery signal from the CPU, so that each of the LIN units continues to enable the LIN unit by detecting the error flag bit.

Therefore, hardware reset of the interface conversion device is realized.

In at least some embodiments, each LIN cell further comprises: a judgment logic circuit; the state machine in the LIN unit is connected with the TAXI interface, the processor interface and the LIN main node through the judging logic circuit, and the TAXI interface and the processor interface are respectively connected with the LIN main node in the LIN unit through the judging logic circuit.

Therefore, unified management and reasonable shunting of data interaction in the interface conversion device are realized.

In at least some embodiments, the state machine is specifically configured to intercept an ID bit field of a valid bearer portion in the ethernet packet and configure the ID bit field into the IP of the LIN master node.

From the above, the IP configuration of the LIN host is realized.

In at least some embodiments, the state machine is specifically configured to intercept a data length bit field of an effective bearer portion of the ethernet packet and configure the data length bit field into a data length register of the LIN master node.

From above, the LIN master data length configuration is realized.

In at least some embodiments, the state machine is specifically configured to intercept a data bit field of a valid bearer portion of the ethernet packet and configure the data bit field into a corresponding data register in the LIN master node.

From the above, the data configuration of the LIN master is realized.

A second aspect of the present application provides a computing device comprising: the interface conversion device is provided.

Drawings

The individual features and the connections between the individual features of the present application are further explained below with reference to the drawings. The figures are exemplary, some features are not shown to scale, and some of the figures may omit features that are conventional in the art to which the application relates and are not essential to the application, or show additional features that are not essential to the application, and the combination of features shown in the figures is not intended to limit the application. In addition, the same reference numerals are used throughout the specification to designate the same components. The specific drawings are illustrated as follows:

fig. 1 is a schematic diagram of an interface conversion between an ethernet and a LIN in the related art;

fig. 2 is a schematic structural diagram of an interface conversion apparatus according to an embodiment of the present application;

fig. 3 is a schematic diagram of a format of a payload associated with LIN in an ethernet packet in the embodiment of the present application;

fig. 4 is an exemplary hardware structure of an interface conversion apparatus and an external schematic diagram thereof in an embodiment of the present application;

fig. 5 is a schematic processing state diagram of a state machine in an interface conversion apparatus according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a computing device according to an embodiment of the present application.

Detailed Description

The terms "first, second, third and the like" or "module a, module B, module C and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order, it being understood that specific orders or sequences may be interchanged where permissible to effect embodiments of the present application in other than those illustrated or described herein.

The term "comprising" as used in the specification and claims should not be construed as being limited to the contents listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the expression "an apparatus comprising the devices a and B" should not be limited to an apparatus consisting of only the components a and B.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, as would be apparent to one of ordinary skill in the art from this disclosure.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. In the case of inconsistency, the meaning described in the present specification or the meaning derived from the content described in the present specification shall control. In addition, the terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the present application.

As described above, in the related art, the conversion between the ethernet interface and the LIN interface in the chip is mainly completed by the CPU, which requires the LIN device to initiate an interrupt to the CPU multiple times to complete the intermediate processing, and thus, not only is the processing efficiency low, but also a large amount of CPU resources are required to be occupied, which seriously affects the CPU efficiency. In view of the technical problem, the basic idea of the embodiments of the present application is to provide an interface conversion device implemented by hardware, which can implement interface conversion by connecting the interface conversion device among a CPU, an ethernet interface, and a TAXI interface without requiring direct processing by the CPU, thereby effectively improving efficiency and saving CPU resources.

Herein, the taii interface, which may also be referred to as an ethernet interface, refers to an interface of the taii bus, which may be configured to transmit ethernet messages between routers. It should be noted that, although referred to as a TAXI interface herein, it is understood that the TAXI interface may be replaced by any other interface capable of transmitting ethernet messages.

Fig. 2 shows an exemplary structure of the interface conversion apparatus 100 provided in the embodiment of the present application. Referring to fig. 2, the interface conversion apparatus according to the embodiment of the present application may include at least one LIN unit 110, a TAXI bus (TAXI) interface 120, and a processor interface 130, where each LIN unit 110 may include a state machine 111 and a LIN master node (LIN Core)112, the state machine 111 is connected to one LIN master node 112, the processor interface 130 and the TAXI interface 120, the TAXI interface 120 is connected to the state machine 111 and the LIN master node 112, and is simultaneously connected to the TAXI bus, and the processor interface 130 is connected to the state machine 111 and the LIN master node 112, and is also connected to the CPU.

Wherein, the ethernet message from the taii bus is received by the taii interface 120 and buffers an effective bearer portion (payload) in the ethernet message according to the LIN number therein, the effective bearer portion in the ethernet message enters the state machine 111 in the LIN unit 110 corresponding to the LIN number thereof, the state machine 111 configures the LIN master node 112 in the LIN unit 110 by analyzing the effective bearer portion in the ethernet message, the LIN master node 112 returns LIN data corresponding to the ethernet message to the taii interface 120 after completing receiving and transmitting according to the configuration of the state machine and the LIN control information from the processor interface, and the taii interface 120 encapsulates the LIN message by using the LIN data and the LIN control information corresponding to the LIN number from the processor interface 130 and transmits the LIN message to the taii bus. Therefore, the conversion from the Ethernet message to the LIN message is realized through hardware, direct processing of a CPU is not needed, and the influence on the efficiency of the CPU caused by multiple interrupt initiated in the LIN receiving and transmitting process can be effectively avoided, so that the efficiency is effectively improved and the CPU resource is saved while the message conversion between the Ethernet and the LIN is realized.

In this embodiment of the application, the TAXI interface 120 may be configured to receive an ethernet packet from the TAXI bus, and cache a payload in the ethernet packet according to a LIN number in the ethernet packet; and is configured to encapsulate and send a LIN message onto the taix bus using LIN data from the LIN master 112 and LIN control information from the processor interface 130.

As shown in fig. 2, the taii interface 120 is connected between each of the lines of LIN units 110 and the taii bus, and can receive an ethernet message and return an LIN message to the ethernet via the taii bus, and the taii interface 120 can receive LIN data from each of the lines of LIN units 110 in parallel by being connected to each of the lines of LIN units 110, thereby implementing parallel transmission of multiple lines of LIN messages.

In some embodiments, a first buffer 121 may be included in the TAXI interface 120, and the first buffer 121 may be configured to buffer the valid bearer portion in the ethernet message according to the LIN number. In particular, as shown in fig. 2, the first buffer 121 may include first buffer areas 1211 distinguished by LIN numbers, where the first buffer areas 1211 are configured to buffer valid bearer portions to be sent to the LIN units 110 identified by their LIN numbers. In this embodiment, the tax interface 120 may send the corresponding effective bearer to the corresponding first buffer 1211 according to the LIN number in the ethernet message, and the state machine 111 in the corresponding LIN unit 110 only needs to read the effective bearer of the ethernet message to the first buffer 1211 corresponding to the LIN number. Thus, the multiple LIN units 110 can complete message transmission and reception in parallel and relatively independently, and competition hazards caused by simultaneous transmission and reception of multiple LIN units are effectively reduced.

In some embodiments, the tax interface 120 may further include a second buffer 122, where the second buffer 122 is configured to buffer LIN messages according to LIN numbers, so as to send LIN messages of at least one LIN unit in parallel. Specifically, as shown with reference to fig. 2, the second buffer 122 may include second buffer regions 1221 distinguished by LIN numbers, each second buffer region 1221 configured to buffer LIN data from a LIN cell 110 identified by a corresponding LIN number. In this embodiment, LIN data from each line of LIN units 110 may be sent to the corresponding second buffer area 1221 according to the LIN number, and the tax interface 120 only needs to read LIN data of one LIN number to the second buffer area 1221. Thus, LIN messages of multiple LIN units 110 can be processed in parallel and relatively independently, and competition hazards caused by simultaneous receiving and transmitting of multiple LIN units are effectively reduced.

In some embodiments, the taii interface 120 may further store a memory (not shown in fig. 2) for storing the ethernet packet, where the memory may be implemented by, for example, a first-in first-out (FIFO), and the ethernet packet is stored according to a first-in first-out principle after reaching the taii interface, and when the memory is full, the reception of the ethernet packet may be suspended to avoid packet loss. Referring to the example of fig. 4, the memory may be, but is not limited to, a 96bit wide, 16 depth FIFO, whose backpressure pipeline may be set to 10.

Lin is slow, and in order to solve the problem of being too late to transmit, in some examples, the first buffer and the second buffer may be implemented by setting two sets of buffers, and the buffers may be implemented by registers.

Taking the example of parallel multiple LIN, see the example of fig. 4 below, the effective bearers sent to different LIN (i.e. CTRL _1 to CTRL _6 in fig. 4) will be stored in FIFO according to LIN _ num, and then enter multiple groups of Buffer _1 (an example of a first Buffer) of 96bits × 6. In this way, multiple LIN cells 110 (i.e., CTRL _1 to CTRL _6 in fig. 4) can read the corresponding active bearer portions from the taii interface 120 in parallel. When the interface conversion device is in an enabled working state (for example, the state of the state machine jumps to a hardware process), one or more items of CTRL _ 1-CTRL _6 (an example of the LIN unit 110) take data from Buffer _1 in 96-bit width. Even if the data is less than 96bits, the data needs to be read according to the 96bits, and the data can be intercepted according to the data _ length after the data arrives at one or more items of CTRL _ 1-CTRL _ 6.

In some embodiments, the TAXI interface 120 may include an identifying module 123 configured to identify a payload in an ethernet packet from the TAXI bus, extract the payload, and send the extracted payload to the first buffer 1211 corresponding to the LIN number in the ethernet packet in the first buffer 121.

Fig. 3 shows a format diagram of payload in an ethernet packet. Referring to the example of fig. 3, the portion of the payload associated with a LIN extracted from an ethernet packet may include, but is not limited to, the following bit fields: vld, transmit, RFU, data length (byte _ num) [3:0], Lin _ num [2:0], id [5:0], Wakeup, wait for future use (RFU), Command maker [5:0], CRC [4:0], RFU [2:0], data.

The various bit fields in FIG. 3 are illustrated as follows:

lin _ num represents a Lin number.

vld: this bit is high indicating that the frame is valid and is to be distinguished from the padding frame when the message is less than 64B. If the bit is low, the frame is not processed and directly transmitted.

Wakeup, transmit, id are defined by the LIN protocol, which can be referred to in the document "LIN-usg-2 x21n00s 00". Wakeup indicates that the LIN master receives or transmits a Wakeup signal, where a transmit of 1 indicates transmission and a 0 indicates reception. id is an identifier.

Command _ marker is used to mark different frames, and the Command _ marker of frames in a packet from the same TAXI bus may or may not be the same.

The CRC is used to perform a CRC5 check on the payload field (about 96bits) of the entire LIN. If the CRC5 of the received message checks the error, the message is not processed any more, and the message is discarded.

In some embodiments, the tax interface 120 may include an encapsulation module 124 configured to encapsulate the LIN packet with payload in the ethernet packet and LIN data returned by the corresponding LIN master 112 and send the LIN packet to the ethernet via the tax bus. Specifically, the encapsulation module 124 may be configured to obtain the payload of the ethernet packet from a first buffer 1211 in the first buffer 121, obtain the LIN data with the same LIN number from a corresponding second buffer 1221 in the second buffer 122, encapsulate the LIN data into a LIN packet according to a predetermined LIN packet format, and send the LIN packet to the taii bus.

In some embodiments, the taii interface 120 may be configured to send out the LIN messages of each LIN unit 110 in sequence according to priority. Specifically, the tax interface 120 performs priority ordering on LIN messages of the multiple LIN units 110, and the tax interface 120 sequentially transmits the LIN messages to the ethernet according to the priority in the parallel transmission process of the multiple LIN messages.

The processor interface 130 may be configured to provide LIN control information to the TAXI i interface 120 and the LIN master 112, as well as to send interrupt messages initiated by the LIN master 112 to the CPU.

In some embodiments, the processor interface 130 may include registers (not shown in fig. 2) in which the various ways of LIN control information may be stored according to LIN numbers. These registers in the processor interface 130 may query the LIN control information required for the LIN master node 112 to transmit and receive according to information such as the LIN number provided by the state machine 111 and provide the LIN control information to the state machine 111, so that the state machine 111 configures the LIN master node 112. In addition, these registers in the processor interface 130 can also query LIN control information required for encapsulating a LIN message according to information such as a LIN number provided by the tax interface 120 and provide the LIN control information to the tax interface 120, so that the tax interface 120 completes encapsulation of the LIN message.

Here, the LIN control information required for the LIN master 112 to perform transmission and reception may include: address and necessary data. Such as message format, content to be returned, identifier, data length, software control status, hardware control status, etc.

Here, the control information required for encapsulating the LIN message may include: and control items corresponding to the LIN numbers and required for encapsulating all the lines of LIN messages, wherein the control items include but are not limited to Media Access Control (MAC), error types (classified into two categories, namely 3 errors specified by the LIN bus and 3 types of TAXI messages which do not accord with expectation), VLAN labels (VLAN tags) and the like. In some embodiments, the control entries for the respective LIN numbers may be stored by providing a register in the processor interface 130 corresponding to each way LIN number.

The state machine 111 may be configured to parse payload in the ethernet packet corresponding to the local LIN number from the TAXI i interface 120 to intercept LIN related information, and configure the LIN master 112 using the LIN related information. For specific details regarding the state machine, see the examples of fig. 4 and 5 below. It should be noted that fig. 5 is only used as an example, and is not used to limit the specific implementation manner of the state machine in the embodiment of the present application. It can be understood that the specific function, execution logic, state, and the like of the state machine 111 can be adjusted according to different actual application scenarios, different LIN formats, and different ethernet packet formats.

In this embodiment, the LIN master node 112 may be configured to complete data transmission and reception according to the configuration of the state machine 111, and return corresponding LIN data. Specifically, the LIN master 112 may be configured to complete data transceiving using LIN control information corresponding to its own LIN number from the processor interface 130, and return LIN data to the taix interface 120, as configured by the state machine 111. Here, the data transceiving of the LIN master 112 may include, but is not limited to, data interaction between the LIN master 112 and at least one slave node (slave) connected thereto. In a specific application, when the LIN master node 112 transmits data, the data is transmitted according to the minimum packet length of 64B specified by the LIN protocol, and if the data length is insufficient, the LIN master node 112 will complement 0 after the data and fill the data to 64B size, and then transmit the data.

In some embodiments, the LIN master 112 may be directly or indirectly connected to the taii interface 120 to return LIN data to the taii interface 120 after data transceiving is completed. For example, the LIN master 112 may be connected to the tax interface 120 through the decision logic 113.

Here, the LIN data may include, but is not limited to, LIN payload, error warning information, etc., which the LIN master interacts with its slave node (slave). The LIN payload may include, for example, status data, etc. The error prompt message is a message for indicating abnormality of the LIN device side. Here, the error prompt message may include two types, one type is an error prompt message specified by the LIN bus, for example, "slave response timeout", "LIN protocol bit error", "LIN protocol checksum error", and the like; the other type is error prompt information indicating error actions, for example, "length information in a TAXI message is out of bounds or LIN number is out of bounds", "CRC check of the TAXI message is in error", "CPU commands and states are in error and jump forcibly", and the like.

In some embodiments, each LIN unit 110 may further include a decision logic 113, and the decision logic 113 may be configured to connect the state machine 111 to the taii interface 120, the processor interface 130, and the LIN master 112, respectively. Furthermore, the decision logic 113 may be further configured to connect the LIN master 112 with the taii interface 120 to return the LIN data to the taii interface 120.

Here, the decision logic 113 may determine the actions that the LIN master 112 needs to perform (e.g., wake-up, transmit, receive, etc.) and notify the LIN master 112 based on the state of the tax interface 120 and the state of the state machine 111.

In some examples, the decision logic 113 also has a shunt function. Specifically, the judgment logic 113 may send data addressed to the LIN master 112 to the data side of the LIN master 112, and send address information of the LIN master 112 to the address side of the LIN master 112.

In addition, the determination logic 113 may be further configured to send status bits (e.g., flag bits corresponding to various statuses shown in fig. 5 below) of the state machine 111 to the processor interface 130 or the LIN master 112, so that the processor interface 130 and the taix interface 120 can know the status of the state machine 111 and the status of the LIN master 112 in time.

In some embodiments, each LIN unit 110 may also include a memory (not shown) that may be configured to store payload from the TAXI interface 120, LIN control information from the processor interface 130, LIN data that needs to be sent to the TAXI interface 120, and/or interrupt messages that need to be sent to the processor interface 130. The memory is accessible to both the decision logic 113 and the state machine 111 in the LIN unit 110. In some examples, data or information that needs to be provided to the LIN master 112, data or information from the LIN master 112, may be accessed by the decision logic 113 to complete its access. In practice, the memory may include, but is not limited to, one or more sets of registers.

In the embodiment of the present application, each part of the interface conversion apparatus may initiate an interrupt. The taii interface 120, the processor interface 130, the state machine 111 or the LIN master 112 may initiate an interrupt when an abnormal error occurs (e.g., a LIN protocol error of the LIN master 112, an ethernet packet error of the taii interface 120, a DRC check, etc.; a timeout (timing) interrupt of the state machine 111, etc.). Interrupts may also be initiated under certain normal conditions, for example, the LIN master 112 may initiate a completion (complete) interrupt after each execution of a complete transceive. In some embodiments, the state machine 111 may also be configured to receive an interrupt initiated by the LIN master 112, send an interrupt message to the CPU through the processor interface 130 when the interrupt indicates an anomaly, and directly mask the interrupt message (e.g., may be directly discarded or eliminated by the LIN master) when the interrupt indicates normal (e.g., a complete interrupt initiated by the LIN master 112). In this way, the interrupt indicating the abnormality can be processed by the CPU, and the state machine 111 controls the corresponding LIN master 112 to stop working, and the interrupt message indicating the normality can be directly cleared without notifying the CPU, thereby effectively avoiding the influence on the CPU efficiency caused by multiple interrupts initiated by the LIN master during the data transmission and reception process.

For example, a normal type interrupt such as "complete" may not be delivered to the CPU to avoid affecting CPU efficiency. Abnormal interrupts such as "slave timeout", "LIN protocol error", "message format illegal", etc., the state machine 111 may send its interrupt message to the CPU through the judgment logic circuit 113 and the processor interface 130, and the CPU processes the interrupt message. In this way, only abnormal interrupt messages are sent to the CPU for further processing after an interrupt is initiated by the LIN master node 112 or the state machine 111.

In some embodiments, after the CPU has processed the interrupt, an interrupt resume signal is sent to the processor interface 130. The processor interface 130 may be further configured to update the preconfigured error flag to an interrupt reset upon receiving an interrupt recovery signal from the CPU, so that each of the LIN cells 110 (e.g., a state machine in the LIN cell) continues to enable by detecting the error flag bit.

Taking 6-way LIN as an example, fig. 4 shows an exemplary specific structure of the interface conversion apparatus 100 according to the embodiment of the present application. Referring to fig. 4, the Interface conversion apparatus 100 includes 6 lines of LIN units 110 (i.e., CTRL _1 to CTRL _6), a tax Interface 120 (i.e., tax _ IF), a processor Interface 130 (i.e., CPU _ IF), which is externally connected to a CPU, a CPU external Serial Peripheral Interface (SPI), an Advanced High Performance Bus (AHB), and the like, the tax _ IF is externally connected to a tax _ i Bus, the tax _ i Bus is connected to a SWITCH CORE, each line of LIN units 110 includes a state machine 111, a judgment logic circuit 113, and a LIN master node LIN-CORE 112, the state machine 111 and the LIN-CORE 112 are connected by the judgment logic circuit 113, and each LIN master node 112 is externally connected to at least one slave node (slave).

In the example of fig. 4, the tax interface 120 may further include a backpressure control module, and the backpressure control module may be configured to report to the tax bus when Buffer _1 (an example of the first Buffer 121) and/or Buffer _2 (an example of the second Buffer 122) exceeds a predetermined waterline. In addition, the pressure back-control module can be configured to report to the TAXI bus when the FIFO exceeds the preset waterline.

Referring to fig. 4, in the interface conversion apparatus 100, the TAXI _ IF receives an ethernet message (Data _1) from the TAXI _ i bus (an example of the TAXI bus), determines whether the message should be processed according to a port number (port _ num) of the ethernet message, and IF the message should be processed, the TAXI _ IF sends the ethernet message to a 96bits × 16 FIFO (an example of a memory in the TAXI interface 120 for storing the ethernet message). Then, for each ethernet packet in the FIFO, the taii _ IF extracts a target LIN number through its LIN number (LIN _ num) bit field, and then sends the payload part in the ethernet packet into the partition corresponding to the LIN number in the Buffer _1 of 96bits × 6 according to the target LIN number according to the 96bit width.

Each of the LIN cells 110 can transmit and receive in parallel. In each LIN unit 110, the state machine 111 obtains the payload of its own LIN number from the Buffer _1, extracts the relevant information therein according to the bit field (for example, extracts the information of bit fields such as LIN number and id according to the message format), and configures the relevant information to an LIN-Core (an example of a LIN master node) through the judgment logic circuit 113 according to the current state to control the LIN-Core to perform data transmission and reception. LIN control information necessary for LIN-Core data transmission and reception is transmitted from the CPU _ IF to the LIN-Core through the judgment logic circuit 113. After the LIN-Core completes data transmission and reception, the corresponding LIN data is returned to the tax _ IF by the decision logic 113.

In the working process of the interface conversion device, the flow control backpressure module in TAXI _ IF can detect whether each Buffer and FIFO exceed the waterline in real time, and when the Buffer or FIFO exceed the preset waterline, the flow control backpressure module reports a notice that the Ethernet data cannot be continuously received to the front-stage module.

For LIN data returned by each way of LIN unit, TAXI _ IF can be processed in parallel. The encapsulation module in the taii _ IF compiles LIN messages (including Data, LIN numbers and ids) in a message format and buffers the messages in the outgoing 96bits × 6buffer, encapsulates the LIN messages into ethernet messages (Data _0) by adding headers in front of the LIN messages or in another way, and sends the ethernet messages to the taii bus when appropriate, for example, a counter may control when to send out the messages. Here, the multiple LIN ethernet messages may be prioritized, and when the multiple LIN ethernet messages are transmitted in parallel, the multiple LIN ethernet messages are sequentially transmitted to the Taxi _ i bus according to priority, so as to be transmitted to the ethernet. Here, the LIN control information required for the tax _ IF to perform LIN message encapsulation is transmitted from the CPU _ IF to the tax _ IF through the judgment logic circuit 113.

After an interrupt is initiated by the LIN-Core or other part of the LIN unit, it can be directly masked against an interrupt indicating normal. For an interrupt indicating an exception, the state machine sends a corresponding interrupt message to the CPU via the CPU _ IF for continued processing by the CPU, while the state machine 111 may jump to a software processing state described below and the hardware switching function of the interface switching apparatus stops. After the CPU processes the interrupt, an interrupt reset signal is returned, the CPU _ IF decodes the interrupt reset signal, and the error mark in the interrupt reset signal is reset to interrupt reset, so that the reset of the interrupt signal is completed. The interface switching device (e.g., state machine) continues to enable operation after error recovery is detected by monitoring the error flag.

Fig. 5 shows an exemplary processing procedure of the state machine 111. Referring to fig. 5, the operating states of the state machine 111 may include a software processing state, a waiting state, an id state, a Byte _ num state, a Data state, a Transmit (Transmit) state, a Req state, a transceiving state, and an enCAP (enCAP) state.

In the software processing state, the state machine 111 and the LIN master 112 thereof stop working, and the CPU completes the interface conversion between the ethernet interface and the LIN interface. In this state, the process of interface conversion can be seen in fig. 1. In practical applications, when an abnormal interrupt occurs, the hardware interface conversion can be stopped by switching to a software processing state, and the interface conversion can be completed by the CPU.

For example, in the case where the CPU configuration Hardw flag is high, the state machine 111 jumps to a wait state in which the state machine 111 and its LIN master 112 may be in a standby state.

After the taii interface 120 receives the ethernet packet and sends the payload thereof into the corresponding first buffer 1211 of the first buffer 121 according to the LIN number therein, the state machine 111 in the LIN unit 110 corresponding to the LIN number enters an ID state, and in the ID state, the state machine 111 may be configured to intercept the ID bit field of the payload in the ethernet packet and configure the IP of the corresponding LIN master node 112.

After the IP configuration is completed, the state machine 111 jumps to the Byte _ num state. In the Byte _ num state, the state machine 111 may be configured to intercept a Byte _ num bit field of payload in the ethernet packet, and calculate and configure a data length register (data length register) of the LIN master node 112.

After the data length register configuration is completed, the state machine 111 enters the Transmit state. In the Transmit state, the state machine 111 configures a Transmit bit of the corresponding LIN master node 112 according to the count N of the byte counter, where the Transmit bit is used to indicate the transmission state of the LIN master node 112, and if 0 is taken, it indicates that the LIN-Core is in the receiving state, and if 1 is taken, it indicates that the LIN-Core is in the transmitting state. When N is equal to 0, the state machine 111 configures the Transmit bit of the LIN master 112 to be 0, that is, configures the LIN master 112 to be in the receiving state, and when N is greater than 0, configures the Transmit bit of the LIN master 112 to be 1, that is, configures the LIN master 112 to be in the transmitting state.

With the LIN master 112 in the transmit state, the state machine 111 enters the Data state. In the Data state, the state machine 111 may be configured to intercept Data bit fields of payload in the ethernet packet, configure Data in each Data bit field into a corresponding Data register of the LIN master node 112, and set N to N +1, where N represents a count value of the byte counter.

When N in the Transmit bit is 0, the state machine 111 enters the Req state. In the Req state, the state machine 111 configures a transmit-receive flag bit (start Req) of the LIN master node 112, which is used to instruct the LIN master node 112 to perform a transmit-receive action. The LIN master 112 starts transceiving when the start req bit is set.

When N is data length-1, the state machine 111 enters a transceiving state. In the transmit-receive state, the state machine 111 waits for the LIN master node 112 to return an interrupt message, and enters the splicing state after receiving the interrupt message returned by the LIN master node 112.

In the assembly (enCAP) state, the state machine 111 may be configured to assemble LIN data according to an interrupt message returned by the LIN master node 112 and send the LIN data into the corresponding buffer 1221 in the second buffer 122 in the TAXI interface 120. If the interrupt message indicates normal, the state machine 111 sends the payload exchanged between the LIN master 112 and its slave (slave) to the TAXI interface 120 after being assembled. If the interrupt message indicates an abnormality, the state machine 111 assembles error indication information from the LIN master 112, which is used to indicate the abnormality, and sends the assembled error indication information to the tax interface 120.

In some examples, the state machine 111 may be controlled to switch to the software processing state by setting a force bit (e.g., force _ soft). The state machine 111 jumps from the current state to the software processing state when the force bit is high. Thus, hardware of the interface conversion device can be controlled to stop working.

Referring to the examples of fig. 4 and 5, another exemplary operation process of the interface conversion apparatus in the embodiment of the present application is as follows:

the initial configuration of the registers in the interface conversion device can only be performed in the initial state and the software processing state of the state machine 111, and is not allowed to be configured at other times.

In the software processing state, the LIN _ CORE is controlled by the CPU, and a master node, a slave node, a rate, a check type and the like are required to be configured firstly. In the software processing state, the state machine 111 cannot operate the register, and the CPU controls the operation.

In a hardware processing state, the state machine 111 controls the judging logic circuit to read payload from the buffer of the TAXI _ IF, extract relevant LIN configuration information from a corresponding position of the payload, and configure LIN _ CORE, so that LIN _ CORE performs data receiving and transmitting.

When the CPU configures hardw to be high, the CPU enters a waiting state. And in the wait state, when data sent by TAXI _ IF is received, the data enters a configuration state, and is stored into a register of the CTRL module according to 96-bit data, so that the judgment logic circuit reads the data from the register according to the instruction of the state machine, processes the data and sends the processed data to LIN _ CORE. Meanwhile, IF the not _ empty of the TAXI _ IF is high in the wait state, the payload is retrieved from the buffer of the TAXI _ IF, decomposed into flag bit information such as id, data _ length, transmit and data, and sequentially sent to the IP port. Then, the configuration state is entered.

In the configuration state, the state machine 111 intercepts the control fields according to the message format (see fig. 3) and sequentially configures the control fields into the LIN-Core. Here, the register inside the LIN-Core is generally 8bits, supports hardware control, sets a continuous message format, and stores flag bit information such as id, data _ length, transmit, and data, respectively.

In the configuration state, the LIN-Core corresponding registers are configured in sequence as shown in fig. 5 until after start _ req is configured, the transmit-receive state is entered, at which point the state machine 111 waits for the LIN Core to return an interrupt.

If the interrupt of LIN-Core is pulled high, the state register of LIN-Core is read.

If the Error flag (Error) is high and the Error encapsulation flag (ERR _ ena) of the Register of LIN CORE (the flag indicating that Error information is to be encapsulated into ethernet messages when high and indicating that Error information is not to be encapsulated into ethernet messages when low) is high, the Error Register (Error Register) of LIN CORE (the Register for storing the Error information of LIN CORE) is read and stored in the internal Register ERR (i.e., the Register in the state machine 111). When err _ ena is low, no read is needed.

If the completion flag (complete) is high and data is read from the interface between the LIN-Core and its slave node (i.e., transmit is 0), the state machine 111 controls the decision logic module to read the data _ length of the LIN-Core several times. If complete is high and data is sent to the interface between LIN-Core and its slave node (i.e. transmit is 1), no data need be read.

Whether the interface between the LIN-Core and the slave node receives or transmits, for the convenience of uniform processing, after the complete is received, the state machine composes 3 beats of 32bits data and returns to TAXI _ IF. Here, when the interface between LIN-Core and its slave node is in a state of transmitting data, IF there is no return data, the data bit in LIN payload is sent to tax _ IF after being filled with 0.

After the end of the packet splicing, if there is no error (i.e. the interrupt message indicates normal), the message (including data and corresponding LIN number and id) can be edited according to the message format (see 3.1). The bag splicing process: data read from an internal register of the state machine or a memory in a LIN unit (one of CTRL _1 to CTRL _6 in fig. 4), and LIN _ NUM, complete, LIN _ ERR, and id as additional information are sent to the tax _ IF together in a message format. The LIN _ NUM is a LIN number, and can also be used for identifying a LIN unit and taking a fixed value. id is the bit field that is truncated from the payload from TAXI _ IF when sent to LIN-Core. When sending, the above information is sent to the TAXI _ IF in parallel, and no matter which way of complete flag is set high, the message encapsulated in the current LIN unit is edited and sent to the TAXI _ IF. And finally, calculating the CRC5 value of the whole LIN payload frame, and putting the LIN payload frame header into the LIN payload frame header.

IF an error (namely, the interrupt message indicates an exception), the corresponding LIN unit (one of CTRL _1 to CTRL _6 in fig. 4) pulls up the wr interface signal (the wr interface signal is a flag signal for entering the software processing state) and sends the wr interface signal to the tax _ IF, and at the same time, enters the software processing state, and the software controls the LIN-CORE to process the error.

After the LIN data is sent to the tax _ IF, the registers in each LIN cell (CTRL _1 to CTRL _6 in fig. 4) or the status registers of the state machine therein are reset.

Fig. 6 is a schematic structural diagram of a computing device 500 provided in an embodiment of the present application. The computing device 500 includes: the interface conversion apparatus 100 described above. Further, the computing device may also include a processor 510, memory 520, a communication interface 530, and a bus 540.

It is to be appreciated that communication interface 530 in computing device 500 shown in FIG. 6 may be used to communicate with other devices.

The processor 510 may be coupled to the memory 520, among other things. The memory 520 may be used to store the program codes and data. Therefore, the memory 520 may be a storage unit inside the processor 510, may be an external storage unit independent of the processor 510, or may be a component including a storage unit inside the processor 510 and an external storage unit independent of the processor 510.

Optionally, computing device 500 may also include a bus 540. The memory 520 and the communication interface 530 may be connected to the processor 510 via a bus 540. The bus 540 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, a TAXI bus, or the like. The bus 540 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one line is shown in FIG. 6, but it is not intended that there be only one bus or one type of bus.

It should be understood that, in the embodiment of the present application, the processor 510 may adopt a Central Processing Unit (CPU). The processor may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. Or the processor 510 may employ one or more integrated circuits for executing related programs to implement some technical details of the technical solutions provided in the embodiments of the present application, such as processing of interrupts and the like.

The memory 520 may include both read-only memory and random access memory, and provides instructions and data to the processor 510. A portion of processor 510 may also include non-volatile random access memory. For example, processor 510 may also store information of the device type.

In the several embodiments provided in the present application, it should be understood that the disclosed system and apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

Computer program code for carrying out operations for aspects of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + +, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).

It is to be noted that the foregoing is only illustrative of the presently preferred embodiments and application of the principles of the present invention. It will be understood by those skilled in the art that the present application is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the application. Therefore, although the present application has been described in more detail with reference to the above embodiments, the present application is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present application.

Claims

1. An interface conversion apparatus, comprising: the local interconnect network system comprises at least one Local Interconnect Network (LIN) unit, a processor interface and a TAXI interface, wherein each LIN unit comprises a state machine and an LIN main node, the state machines are respectively connected with the LIN main node, the processor interface and the TAXI interface, the TAXI interface is connected with the state machines and the LIN main node and is externally connected with a TAXI bus at the same time, and the processor interface is respectively connected with the state machines and the LIN main node and is externally connected with a Central Processing Unit (CPU) at the same time; the Ethernet message from the TAXI bus is received by the TAXI interface and an effective bearing part in the Ethernet message is cached according to the LIN number in the Ethernet message; the method comprises the steps that an effective bearing part in an Ethernet message enters a state machine in an LIN unit corresponding to an LIN number of the Ethernet message, the state machine configures an LIN main node in the LIN unit by analyzing the effective bearing part in the Ethernet message, the LIN main node returns LIN data corresponding to the Ethernet message to a TAXI interface after receiving and sending according to the configuration and LIN control information from a processor interface, and the TAXI interface utilizes the LIN data and the LIN control information corresponding to the LIN number from the processor interface to package the LIN message and sends the LIN message to the TAXI bus.

2. The interface conversion apparatus according to claim 1, wherein the taii interface comprises: a first buffer configured to buffer an active bearer portion in the Ethernet message according to a LIN number.

3. The interface conversion apparatus according to claim 1, wherein the taii interface includes a second buffer configured to buffer the LIN messages according to the LIN numbers, so as to send the LIN messages of the at least one LIN unit in parallel.

4. The interface conversion apparatus according to claim 1, wherein the state machine is further configured to receive an interrupt initiated by the LIN master, to send an interrupt message to a CPU through the processor interface when the interrupt indicates an anomaly, and to directly mask the interrupt message when the interrupt indicates a normal condition.

5. The interface converting apparatus according to claim 1, wherein the processor interface is further configured to update an error flag to an interrupt reset after receiving an interrupt recovery signal from the CPU, so that each of the LIN units continues to enable the LIN unit by detecting the error flag.

6. The interface conversion apparatus of claim 1, wherein each LIN cell further comprises: a judgment logic circuit; the state machine in the LIN unit is connected with the TAXI interface, the processor interface and the LIN main node through the judging logic circuit, and the TAXI interface and the processor interface are respectively connected with the LIN main node in the LIN unit through the judging logic circuit.

7. The interface conversion apparatus according to claim 1, wherein the state machine is specifically configured to intercept an ID field of a valid bearer portion in the ethernet packet and configure the ID field into the IP of the LIN master node.

8. The interface conversion apparatus according to claim 1, wherein the state machine is specifically configured to intercept a data length bit field of a valid bearer portion of the ethernet packet and configure the data length bit field into a data length register of the LIN master node.

9. Interface conversion arrangement according to claim 1, characterized in that the state machine is configured in particular to intercept the data bit field of the payload part of the ethernet packet and to configure it into a corresponding data register in the LIN master node.

10. A computing device comprising the interface converting apparatus according to any one of claims 1 to 9.