CN112968064A - Low-capacity TVS for 5G and high-speed application and manufacturing method - Google Patents
Low-capacity TVS for 5G and high-speed application and manufacturing method Download PDFInfo
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- CN112968064A CN112968064A CN202110324201.7A CN202110324201A CN112968064A CN 112968064 A CN112968064 A CN 112968064A CN 202110324201 A CN202110324201 A CN 202110324201A CN 112968064 A CN112968064 A CN 112968064A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000002161 passivation Methods 0.000 claims abstract description 7
- 238000001259 photo etching Methods 0.000 claims description 27
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 19
- 229910052721 tungsten Inorganic materials 0.000 claims description 19
- 239000010937 tungsten Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 17
- 238000009792 diffusion process Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 238000007517 polishing process Methods 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 238000004891 communication Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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Abstract
The invention provides a low-capacity TVS for 5G and high-speed applications and a manufacturing method thereof, wherein the TVS comprises the following steps: a substrate layer, the substrate layer being of a P-type; a P-well region formed on the substrate layer; an N-well region formed on the substrate layer; an N + region formed in the P-well region and the N-well region; a P + region formed in the P-well region and the N-well region; the first insulating medium layer is formed on the surface of the substrate layer; the contact hole is formed in the first insulating medium layer and is positioned in the N + region and the P + region; a first layer of metal formed on the first insulating medium layer; a second insulating dielectric layer formed on the first layer of metal; the through hole is formed in the second insulating medium layer; a second layer of metal formed on the second insulating dielectric layer; and the passivation layer is formed on the second layer of metal.
Description
Technical Field
The present invention relates to transient suppression diodes, and more particularly to a low-capacitance TVS for 5G and high speed applications and a method of manufacture.
Background
The TVS diode with low capacitance is used for protecting sensitive electronic equipment from being damaged by high surge, and becomes an ideal circuit passive protection component in 5G communication base stations, high-speed Ethernet communication lines, high-speed interfaces in industrial application and automotive electronic products. Meanwhile, due to the unique low leakage current advantage of the low-capacitance transient TVS diode, the low-leakage current TVS diode is widely applied to the field of high-speed communication, and is beneficial to improving the power efficiency of products such as a CAN (controller area network) system of vehicle-mounted electronics, security monitoring equipment, an intelligent home and an internet of things sensor and prolonging the operation time. The residual voltage of the conventional low-capacitance TVS diode is not very advantageous, the excessive residual voltage causes high power consumption, and even a protected circuit or chip can be damaged, so that the TVS diode with ultralow residual voltage at the same time needs to be designed.
Disclosure of Invention
The invention aims to provide a low-capacity TVS for 5G and high-speed applications and a manufacturing method thereof, so as to improve the response speed and be better applied to 5G and high-speed environments.
The technical scheme adopted by the invention for solving the technical problem is as follows:
a low-capacity TVS for 5G and high-speed applications, comprising:
a substrate layer, the substrate layer being of a P-type;
a P-well region formed on the substrate layer;
an N-well region formed on the substrate layer and adjacent to the P-well region;
an N + region formed in the P-well region and the N-well region;
a P + region formed in the P-well region and the N-well region and adjacent to the N + region;
the first insulating medium layer is formed on the surface of the substrate layer;
the contact hole is formed in the first insulating medium layer and is positioned in the N + region and the P + region, and a tungsten plug is arranged in the contact hole;
a first layer of metal formed on the first insulating medium layer;
a second insulating dielectric layer formed on the first layer of metal;
the through hole is formed in the second insulating medium layer, and a tungsten plug is arranged in the through hole;
a second layer of metal formed on the second insulating dielectric layer;
and the passivation layer is formed on the second layer of metal and is provided with a bonding point.
Further, the resistivity of the underlayer is 50ohm cm or more.
The manufacturing method of the low-capacity TVS for 5G and high-speed applications comprises the following steps:
1) preparing a P-type substrate layer, wherein the resistivity of the P-type substrate layer is more than 50 ohm.cm;
2) forming a P well on the P type substrate sheet by utilizing photoetching, etching, injecting and diffusing: injecting boron element with the concentration of E12-E15 and the diffusion temperature of 1000-1150 ℃;
3) forming an N well on the P-type substrate sheet by utilizing photoetching, etching, injecting and diffusing: injecting phosphorus element with the concentration of E12-E15 and the diffusion temperature of 1000-1150 ℃;
4) and forming N + in the P well and the N well by utilizing photoetching, etching, injecting and diffusing: injecting phosphorus element with the concentration of E12-E15 and the diffusion temperature of 850-1100 ℃;
5) and forming a P + in the P well and the N well by utilizing photoetching, etching, injecting and diffusing: injecting boron element with the concentration of E12-E15 and the diffusion temperature of 850-1100 ℃;
6) a first insulating medium layer is made on the surface of the wafer, and then contact holes are formed in the N + and P + regions by photoetching and dry etching;
7) making a tungsten plug in the contact hole, grinding the tungsten plug by adopting a chemical mechanical polishing process, growing a layer of metal aluminum on the surface of the wafer by using a metal sputtering process, and making metal wiring as a first layer of metal by utilizing photoetching;
8) forming a second insulating medium layer on the first layer of metal by using chemical vapor deposition, and forming a through hole on the second insulating medium layer by using photoetching and dry etching processes;
9) manufacturing a tungsten plug in the through hole, grinding the tungsten plug by adopting a chemical mechanical polishing process, growing a layer of metal aluminum on the surface of the wafer by using a metal sputtering process, and manufacturing metal wiring as a second layer of metal by utilizing photoetching;
10) and (3) making a passivation layer on the second layer of metal by using a chemical vapor deposition method, and defining the position of the bonding point by using photoetching and dry etching processes.
The invention has the advantages that:
1. the material has obvious snapback characteristic and low residual pressure;
2. the ultra-low capacitor is used for protecting the 5G and high-speed application environment;
3. the fluctuation of the capacitance along with the change of the external bias voltage is small, the stability is high, and the integrity of signals is kept;
4. flexible layout design meets the structural design of single-channel or multi-channel, unidirectional or bidirectional TVS;
and 5, I/O is arranged on the front surface of the chip, and the packaging cost can be reduced by using advanced packaging.
Drawings
FIG. 1 is a schematic surface structure diagram of a low volume TVS proposed by the present invention for 5G and high speed applications;
FIG. 2 is a schematic diagram of a longitudinal cross-sectional structure of the TVS;
FIG. 3 is a schematic circuit diagram of the TVS;
fig. 4 is an I/V characteristic test chart of the TVS.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1 to 3, the low-capacity TVS for 5G and high-speed applications proposed by the present invention includes: a substrate layer, the substrate layer being of a P-type; a P-well region formed on the substrate layer; an N-well region formed on the substrate layer and adjacent to the P-well region; an N + region formed in the P-well region and the N-well region; a P + region formed in the P-well region and the N-well region and adjacent to the N + region; the first insulating medium layer is formed on the surface of the substrate layer; the contact hole is formed in the first insulating medium layer and is positioned in the N + region and the P + region, and a tungsten plug is arranged in the contact hole; a first layer of metal formed on the first insulating medium layer; a second insulating dielectric layer formed on the first layer of metal; the through hole is formed in the second insulating medium layer, and a tungsten plug is arranged in the through hole; a second layer of metal formed on the second insulating dielectric layer; and the passivation layer is formed on the second layer of metal and is provided with a bonding point. The substrate layer has a resistivity of 50ohm cm or more.
The manufacturing method of the low-capacity TVS for 5G and high-speed applications comprises the following steps: preparing a P-type substrate layer, wherein the resistivity of the P-type substrate layer is more than 50 ohm.cm; forming a P well on the P type substrate sheet by utilizing photoetching, etching, injecting and diffusing: injecting boron element with the concentration of E12-E15 and the diffusion temperature of 1000-1150 ℃; forming an N well on the P-type substrate sheet by utilizing photoetching, etching, injecting and diffusing: injecting phosphorus element with the concentration of E12-E15 and the diffusion temperature of 1000-1150 ℃; and forming N + in the P well and the N well by utilizing photoetching, etching, injecting and diffusing: injecting phosphorus element with the concentration of E12-E15 and the diffusion temperature of 850-1100 ℃; and forming a P + in the P well and the N well by utilizing photoetching, etching, injecting and diffusing: injecting boron element with the concentration of E12-E15 and the diffusion temperature of 850-1100 ℃; a first insulating medium layer is made on the surface of the wafer, and then contact holes are formed in the N + and P + regions by photoetching and dry etching; making a tungsten plug in the contact hole, grinding the tungsten plug by adopting a chemical mechanical polishing process, growing a layer of metal aluminum on the surface of the wafer by using a metal sputtering process, and making metal wiring as a first layer of metal by utilizing photoetching; forming a second insulating medium layer on the first layer of metal by using chemical vapor deposition, and forming a through hole on the second insulating medium layer by using photoetching and dry etching processes; manufacturing a tungsten plug in the through hole, grinding the tungsten plug by adopting a chemical mechanical polishing process, growing a layer of metal aluminum on the surface of the wafer by using a metal sputtering process, and manufacturing metal wiring as a second layer of metal by utilizing photoetching; and (3) making a passivation layer on the second layer of metal by using a chemical vapor deposition method, and defining the position of the bonding point by using photoetching and dry etching processes.
The TVS structure mainly comprises a P well and an N well which are adjacent and have a certain interval, wherein the P well and the N well are respectively provided with an N + and a P + which are adjacent and have a certain interval. The TVS structure is a circuit structure with higher integration level formed by a plurality of units. When the structure works, the voltage at two ends of the circuit increases along with the increase of the current in the circuit, but the structure triggers the starting when the voltage increases to a certain value, the current passes through the low-impedance channel after the starting, the voltage is reduced, and finally, the stable voltage is maintained. The distance between the P well and the N well, and the distance between the N + and the P + determine the trigger voltage and the maintaining voltage of the circuit structure, and the trigger voltage and the maintaining voltage of various requirements can be obtained by adjusting the distance. Referring to fig. 4, the I/V characteristic of the conventional low-capacitance TVS product is shown as curve a, which represents a diode characteristic. The low-capacitance TVS of the invention has SCR characteristics, as shown by a curve b, has obvious snapback effect and can play a role in greatly reducing clamping voltage. In addition to the spacing between the P well and the N well, and the spacing between the N + and the P + in the TVS structure of the present invention, the spacing between the cells is also required to be considered. In order to save the chip area, the design surface utilizes double-layer metal, mainly combines tungsten plug technology and surface aluminum electrode.
In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", "left", "right", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings, or orientations or positional relationships that the products of the present invention are usually placed in when used, or orientations or positional relationships that are usually understood by those skilled in the art, and are used only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the equipment or the elements that are referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance. In the description of the present invention, it is also to be noted that, unless otherwise explicitly stated or limited, the terms "disposed" and "connected" are to be interpreted broadly, and for example, "connected" may be a fixed connection, a detachable connection, or an integral connection; can be mechanically or electrically connected; the connection may be direct or indirect via an intermediate medium, and may be a communication between the two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Claims (3)
1. A low-capacity TVS for 5G and high-speed applications, comprising:
a substrate layer, the substrate layer being of a P-type;
a P-well region formed on the substrate layer;
an N-well region formed on the substrate layer and adjacent to the P-well region;
an N + region formed in the P-well region and the N-well region;
a P + region formed in the P-well region and the N-well region and adjacent to the N + region;
the first insulating medium layer is formed on the surface of the substrate layer;
the contact hole is formed in the first insulating medium layer and is positioned in the N + region and the P + region, and a tungsten plug is arranged in the contact hole;
a first layer of metal formed on the first insulating medium layer;
a second insulating dielectric layer formed on the first layer of metal;
the through hole is formed in the second insulating medium layer, and a tungsten plug is arranged in the through hole;
a second layer of metal formed on the second insulating dielectric layer;
and the passivation layer is formed on the second layer of metal and is provided with a bonding point.
2. The TVS of claim 1, wherein said TVS is a low-capacity TVS for 5G and high-speed applications, further comprising:
the substrate layer has a resistivity of 50ohm cm or more.
3. The method of claim 1, comprising:
1) preparing a P-type substrate layer, wherein the resistivity of the P-type substrate layer is more than 50 ohm.cm;
2) forming a P well on the P type substrate sheet by utilizing photoetching, etching, injecting and diffusing: injecting boron element with the concentration of E12-E15 and the diffusion temperature of 1000-1150 ℃;
3) forming an N well on the P-type substrate sheet by utilizing photoetching, etching, injecting and diffusing: injecting phosphorus element with the concentration of E12-E15 and the diffusion temperature of 1000-1150 ℃;
4) and forming N + in the P well and the N well by utilizing photoetching, etching, injecting and diffusing: injecting phosphorus element with the concentration of E12-E15 and the diffusion temperature of 850-1100 ℃;
5) and forming a P + in the P well and the N well by utilizing photoetching, etching, injecting and diffusing: injecting boron element with the concentration of E12-E15 and the diffusion temperature of 850-1100 ℃;
6) a first insulating medium layer is made on the surface of the wafer, and then contact holes are formed in the N + and P + regions by photoetching and dry etching;
7) making a tungsten plug in the contact hole, grinding the tungsten plug by adopting a chemical mechanical polishing process, growing a layer of metal aluminum on the surface of the wafer by using a metal sputtering process, and making metal wiring as a first layer of metal by utilizing photoetching;
8) forming a second insulating medium layer on the first layer of metal by using chemical vapor deposition, and forming a through hole on the second insulating medium layer by using photoetching and dry etching processes;
9) manufacturing a tungsten plug in the through hole, grinding the tungsten plug by adopting a chemical mechanical polishing process, growing a layer of metal aluminum on the surface of the wafer by using a metal sputtering process, and manufacturing metal wiring as a second layer of metal by utilizing photoetching;
10) and (3) making a passivation layer on the second layer of metal by using a chemical vapor deposition method, and defining the position of the bonding point by using photoetching and dry etching processes.
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| CN202110324201.7A CN112968064A (en) | 2021-03-26 | 2021-03-26 | Low-capacity TVS for 5G and high-speed application and manufacturing method |
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| CN202110324201.7A CN112968064A (en) | 2021-03-26 | 2021-03-26 | Low-capacity TVS for 5G and high-speed application and manufacturing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023093248A1 (en) * | 2021-11-24 | 2023-06-01 | 无锡中微晶园电子有限公司 | Ultra-low capacitance tvs structure having planar structure and preparation method therefor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023093248A1 (en) * | 2021-11-24 | 2023-06-01 | 无锡中微晶园电子有限公司 | Ultra-low capacitance tvs structure having planar structure and preparation method therefor |
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