CN112965864A - Server power-on fault detection method, system and related device - Google Patents
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Abstract
The application provides a method for detecting a power-on fault of a server, which comprises the following steps: receiving a power-on instruction, and starting the CPLD according to the power-on instruction; monitoring a power-on time sequence by using the CPLD, and storing the power-on time sequence in a register of the CPLD; reading the power-on time sequence by using a BMC and uploading the power-on time sequence to a cloud server; after the cloud server compares the power-on time sequence with the normal time sequence, receiving a comparison result returned by the cloud server; and determining a power-on fault signal according to the comparison result. The method and the device can improve the detection efficiency of the faults in the process of powering on the server. The application also provides a server power-on fault detection method, a server power-on fault detection system, a computer readable storage medium and a server, which have the beneficial effects.
Description
Technical Field
The present disclosure relates to the field of servers, and in particular, to a method, a system, and a related device for detecting a power-on failure of a server.
Background
Regardless of the AMD or Intel platform, the Power Sequence affects the server startup, when the system cannot be started, the engineer needs to measure signals related to the Power Sequence, and these signals are very many, which often takes time and labor, and if the situation that the system cannot be started is very difficult to reproduce, the engineer needs to spend much time for repeatedly observing and measuring. Once the machine cannot be started, the machine is a high-low temperature circulating machine in a test unit, the fault location is more difficult, and the machine can only be repaired by the experience of an engineer.
Disclosure of Invention
The application aims to provide a server power-on fault detection method, a server power-on fault detection system, a computer readable storage medium and a server, which can locate a power-on fault by detecting a power-on time sequence signal of a power supply.
In order to solve the technical problem, the application provides a method for detecting a power-on fault of a server, which has the following specific technical scheme:
receiving a power-on instruction, and starting the CPLD according to the power-on instruction;
monitoring a power-on time sequence by using the CPLD, and storing the power-on time sequence in a register of the CPLD;
reading the power-on time sequence by using a BMC and uploading the power-on time sequence to a cloud server;
after the cloud server compares the power-on time sequence with the normal time sequence, receiving a comparison result returned by the cloud server;
and determining a power-on fault signal according to the comparison result.
Optionally, the power-on sequence includes a main power supply power-on sequence and an auxiliary power supply power-on sequence, and monitoring the power-on sequence by using the CPLD includes:
monitoring a main power supply by using a first counter in the CPLD, and stopping counting when the main power supply is at a high level to obtain a power-on time sequence of the main power supply;
and monitoring the main power supply by using a second counter in the CPLD, and stopping counting when the auxiliary power supply is at a high level to obtain a power-on time sequence of the auxiliary power supply.
Optionally, monitoring the main power source by using the first counter in the CPLD includes:
monitoring a first power supply of the primary power supply using a first set of registers in a first counter in the CPLD;
a second supply of the primary power source is monitored using a second set of registers in a first counter in the CPLD.
Optionally, reading the power-on time sequence and uploading the power-on time sequence to the cloud server by using the BMC includes:
and reading the power-on time sequence in the register by utilizing the BMC through the I2C link, and uploading the power-on time sequence to the cloud server through the I2C link.
Optionally, after the BMC is used to read the power-on time sequence and upload the power-on time sequence to the cloud server, the method further includes:
and the cloud server calculates the difference between adjacent registers in the power-on time sequence according to the register counting sequence, and compares the difference with a preset standard value to obtain the comparison result.
Optionally, the CPLD is further configured to record a flashing state of the LED lamp.
The present application further provides a system for detecting a power-on failure of a server, including:
the starting module is used for receiving a power-on instruction and starting the CPLD according to the power-on instruction;
the monitoring module is used for monitoring a power-on time sequence by utilizing the CPLD and storing the power-on time sequence in a register of the CPLD;
the uploading module is used for reading the power-on time sequence by using the BMC and uploading the power-on time sequence to the cloud server;
the comparison result receiving module is used for receiving a comparison result returned by the cloud server after the cloud server compares the power-on time sequence with the normal time sequence;
and the fault determining module is used for determining a power-on fault signal according to the comparison result.
Optionally, the method further includes:
and the comparison module is arranged on the cloud server and used for calculating the difference value between adjacent registers in the power-on time sequence according to the register counting sequence and comparing the difference value with a preset standard value to obtain the comparison result.
The present application also provides a computer-readable storage medium having stored thereon a computer program which, when being executed by a processor, carries out the steps of the method as set forth above.
The present application further provides a server comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method described above when calling the computer program in the memory.
The application provides a method for detecting a power-on fault of a server, which comprises the following steps: receiving a power-on instruction, and starting the CPLD according to the power-on instruction; monitoring a power-on time sequence by using the CPLD, and storing the power-on time sequence in a register of the CPLD; reading the power-on time sequence by using a BMC and uploading the power-on time sequence to a cloud server; after the cloud server compares the power-on time sequence with the normal time sequence, receiving a comparison result returned by the cloud server; and determining a power-on fault signal according to the comparison result.
According to the method and the device, after the server receives the power-on instruction, the CPLD used for monitoring the power-on time sequence is started, and the CPLD is recorded and uploaded to the cloud server for comparison, so that a detection result aiming at the power-on time sequence is obtained, the fault abnormality in the power-on process can be rapidly determined according to the power-on time sequence, and the detection efficiency of the fault in the power-on process of the server is improved.
The application also provides a server power-on fault detection method, a server power-on fault detection system, a computer readable storage medium and a server, which have the beneficial effects and are not described herein again.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a display status of an LED lamp on a server according to the present application;
fig. 2 is a flowchart of a method for detecting a power-on failure of a server according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a system for detecting a power-on fault of a server according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Currently, as shown in fig. 1, fig. 1 is a schematic diagram of a display state of an LED (Light Emitting Diode) lamp on a server provided in the present application, and a power-on state of the server can be determined only by a state of the LED lamp. In FIG. 1, 0 to 11 are numbers corresponding to the LED lamps, and the lower circle represents the LED lamp. For example, the server shown in fig. 1 may employ a combination of 12 LEDs for representing the power status of the server motherboard, with each three LED lights in a group. The Led lamps with numbers 0-2 represent the Power state of the motherboard, when the three Led lamps are all on, the Power is ready to be turned on, when 0 and 1 are dark, and 2 is light, the Power is ready to be turned on for 1.5V of the BMC, when 1 is light, and 1 and 2 are dark, all the Power is turned on. However, the power state of each component in the server can only be reflected through the LED lamp, and the specific reason causing the power-on fault cannot be determined.
Secondly, in the process of powering on the server, the power timing sequence is important. Taking the Intel platform as an example, the time for turning on between VCCFA _ EHV _ firmware and vccinfan cannot be too close, which needs to exceed 2uS, while the time for turning on between vccinfan and VNN needs to be between 2uS and 2mS, and if the timing sequence is incorrect, no power-on or abnormal power-on will be caused. It is apparent that the power-on failure due to the power-on timing cannot be confirmed only by the LER lamp.
To solve the above-mentioned drawback, please refer to fig. 2, where fig. 2 is a flowchart of a method for detecting a power-on failure of a server according to an embodiment of the present application, the method includes:
s101: receiving a power-on instruction, and starting the CPLD according to the power-on instruction;
this step is intended to receive a power-on command and to activate a CPLD (Complex Programmable Logic Device). The triggering manner of the power-on command is not limited, and generally includes an electronic signal trigger and a hardware trigger. The server can be powered on through a power-on instruction sent by other electronic equipment, and the power-on instruction can also be triggered by a hardware physical switch of the server. Therefore, the instructions that can cause the server to perform the power-on process can be all regarded as power-on instructions. Similarly, the corresponding process of receiving the power-on command should be different because the trigger mode of the power-on command is different. And are not intended to be limiting.
After receiving the power-on instruction, the CPLD needs to be started according to the power-on instruction. Because the main power source of the CPLD is P3V3_ AUX, when the CPLD is started according to the power-on instruction, P3V3_ AUX should be started first. Of course, if the CPLDs in different servers are powered by other power sources, the power supply of the CPLDs should be started according to the power-on instruction. In addition, the CPLD is present in the current server for recording the flashing state of the LED lamp, and the CPLD in this step may directly utilize the existing CPLD in the server, or may be newly added with a CPLD, which is specially used for executing the action of step S102. If the two CPLDs are combined, the CPLD for recording the flashing state of the LED lamp is started when the step is executed in a power supply starting plan of the power-on process of the server.
S102: monitoring a power-on time sequence by using the CPLD, and storing the power-on time sequence in a register of the CPLD;
in this step, the power-on time sequence is monitored by using the CPLD, and the monitored power-on time sequence is stored in the corresponding register. The power-on sequence refers to the starting time and the starting sequence of each signal after the server starts to be powered on, namely the sequence. It should be noted that this step should record the start time and start sequence of all signals. However, in the server, at least one sequence is usually included, that is, when there is no influence on the start of the signal and other signals, two sequences can be considered, but there may be a certain start order relationship between different sequences, that is, when a first sequence starts to a certain signal, the first sequence serves as a start condition of a second sequence. And the like, so that the starting of all signals in the power-on process is completed.
The present embodiments herein provide a power-up sequence monitoring procedure for a primary power source and a secondary power source, the power-up sequence including a primary power-up sequence and a secondary power-up sequence. The auxiliary power supply is mainly provided for ICs such as CPLD, BMC, and PCH (Platform Controller Hub), and the main power supply is mainly provided for the CPU. The step is to monitor the main power source by using the first counter in the CPLD, stop counting when the main power source is at a high level to obtain the power-on timing sequence of the main power source, monitor the main power source by using the second counter in the CPLD, and stop counting when the auxiliary power source is at a high level to obtain the power-on timing sequence of the auxiliary power source. The power-up timing required at this time should include the main power source power-up timing and the auxiliary power source power-up timing.
In addition, the monitoring register for the main power supply can be divided into two groups of registers, one group of registers is counted when the P3V3_ AUX is started, and the RSMSRT signal is stopped when the RSMSRT signal runs, so that the numerical values of all the registers are the same, whether electric leakage exists or the signal is in a floating state can be observed, and the CPLD is prevented from being judged by mistake. The other set of registers starts counting from the SLPS3 signal because the main power supply is turned on sequentially after SLPS3 goes high, so the start counter starts counting according to the SPLS3 signal until the power supply is turned on. Therefore, when the BMC reads the register portion of the main power, the register portion is divided into two groups, one group is P3V3_ AUX enabled, and the other group is SLPS3 signal high, the signal is the signal for correctly turning on the main power. Then, at this time, it is necessary to monitor the first power supply of the main power supply by using the first set of registers in the first counter in the CPLD, and then monitor the second power supply of the main power supply by using the second set of registers in the first counter in the CPLD. Therefore, it can be seen that, according to different power types or purposes, when monitoring the power-on time sequence, the power-on time sequence can be divided into a plurality of time sequences for respective monitoring, and all the obtained time sequences are the power-on time sequences required by the step.
It should be noted that, regardless of the signal of the main power supply or the signal of the auxiliary power supply, the counting needs to be stopped at a high level, and therefore, the larger the counting is, the later the corresponding power supply signal start time is.
S103: reading the power-on time sequence by using a BMC and uploading the power-on time sequence to a cloud server;
after the power-on time sequence is obtained, the BMC is required to read the power-on time sequence and upload the power-on time sequence to the cloud server. The cloud server in this step refers to a server accessing the cloud service, and may be a server located locally, but only needs to receive the power-on sequence uploaded by the local device. How to read the power-on sequence and how to upload the power-on sequence to the cloud server is not limited. It is easy to understand that, the embodiment only requires that a corresponding connection is already established with the cloud server before the step is executed, and a specific connection manner is not limited. For example, the BMC may be used to read the power-on timing sequence in the register through the I2C link and upload the power-on timing sequence to the cloud server through the I2C link. Of course, other connection modes, even wireless communication modes, and the like may be established with the cloud server, which are not limited herein.
In this embodiment, the BMC mainly functions to read the power-on timing sequence from the register of the CPLD and upload the power-on timing sequence to the cloud server.
S104: after the cloud server compares the power-on time sequence with the normal time sequence, receiving a comparison result returned by the cloud server;
for the cloud server, the power-on time sequence and the normal time sequence need to be compared. As described above, during the power-on process of the server, the start sequence and the start time difference between the power sources should have corresponding standards, otherwise, a power-on exception or a power-on failure may result. The standard refers to normal timing, which is typically a range value. Therefore, the cloud server can calculate the difference value between adjacent registers in the power-on time sequence according to the register counting sequence, and compare the difference value with the preset standard value to obtain the comparison result. Or directly judging whether the power-on sequence of each power supply in the power-on time sequence is the same as the power-on sequence in the normal time sequence, thereby obtaining a comparison result. The alignment result typically includes at least one of a power-up sequence alignment result and a power-up differential alignment result. For the server, although both the power-on sequence and the power-on time difference of each power signal can affect the power-on sequence, the two will not affect the power-on sequence. Therefore, when performing the power-on failure backtracking of the server, when the influence of one point is small, the emphasis judgment can be performed only for the other point.
In this embodiment, a normal time sequence is stored in the cloud server by default, and how to obtain the normal time sequence is not limited herein, and a manufacturer of the server generally provides a principle process in the power-on process of the server, which includes the normal time sequence required in this step.
After the cloud server produces the comparison result, the comparison result needs to be received. Accordingly, how to receive the comparison result is not particularly limited, and is generally the same as the connection manner used in the uploading process. Of course, the connection method may be different from the connection method used in the uploading process.
S105: and determining a power-on fault signal according to the comparison result.
After the comparison result is obtained, the power-on fault signal can be directly determined, and the fault position in the power-on process of the server is positioned.
According to the embodiment of the application, after the server receives the power-on instruction, the CPLD used for monitoring the power-on time sequence is started, and the records are uploaded to the cloud server for comparison, so that a detection result aiming at the power-on time sequence is obtained, the fault abnormality in the power-on process can be rapidly determined according to the power-on time sequence, and the detection efficiency of the fault in the power-on process of the server is improved.
In the following, the server power-on fault detection system provided in the embodiment of the present application is introduced, and the server power-on fault detection system described below and the server power-on fault detection method described above may be referred to correspondingly.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a server power-on failure detection system according to an embodiment of the present application, and the present application further provides a server power-on failure detection system, including:
the starting module 100 is configured to receive a power-on instruction, and start the CPLD according to the power-on instruction;
the monitoring module 200 is configured to monitor a power-on sequence by using the CPLD, and store the power-on sequence in a register of the CPLD;
the uploading module 300 is used for reading the power-on time sequence by using the BMC and uploading the power-on time sequence to the cloud server;
a comparison result receiving module 400, configured to receive a comparison result returned by the cloud server after the cloud server compares the power-on time sequence with the normal time sequence;
and a fault determining module 500, configured to determine a power-on fault signal according to the comparison result.
Based on the above embodiment, as a preferred embodiment, the monitoring module 200 includes:
the first monitoring unit is used for monitoring a main power supply by using a first counter in the CPLD, and stopping counting when the main power supply is at a high level to obtain a power-on time sequence of the main power supply;
and the second monitoring unit is used for monitoring the main power supply by using a second counter in the CPLD, and stopping counting when the auxiliary power supply is at a high level to obtain a power-on time sequence of the auxiliary power supply.
Based on the above embodiment, as a preferred embodiment, the first monitoring unit is a first power supply for monitoring the main power supply by using a first set of registers in a first counter in the CPLD; a unit for monitoring a second power supply of the primary power supply using a second set of registers in a first counter in the CPLD.
Based on the above embodiment, as a preferred embodiment, the upload module is a module configured to read the power-on timing sequence in the register through an I2C link by using the BMC, and upload the power-on timing sequence to the cloud server through an I2C link.
Based on the above embodiment, as a preferred embodiment, the method may further include:
and the comparison module is arranged on the cloud server and used for calculating the difference value between adjacent registers in the power-on time sequence according to the register counting sequence and comparing the difference value with a preset standard value to obtain the comparison result.
The present application also provides a computer readable storage medium having stored thereon a computer program which, when executed, may implement the steps provided by the above-described embodiments. The storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The application also provides a server, which may include a memory and a processor, where the memory stores a computer program, and the processor may implement the steps provided by the foregoing embodiments when calling the computer program in the memory. Of course, the server may also include various network interfaces, power supplies, and the like.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system provided by the embodiment, the description is relatively simple because the system corresponds to the method provided by the embodiment, and the relevant points can be referred to the method part for description.
The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A method for detecting a power-on fault of a server is characterized by comprising the following steps:
receiving a power-on instruction, and starting the CPLD according to the power-on instruction;
monitoring a power-on time sequence by using the CPLD, and storing the power-on time sequence in a register of the CPLD;
reading the power-on time sequence by using a BMC and uploading the power-on time sequence to a cloud server;
after the cloud server compares the power-on time sequence with the normal time sequence, receiving a comparison result returned by the cloud server;
and determining a power-on fault signal according to the comparison result.
2. The method according to claim 1, wherein the power-on sequence includes a main power source power-on sequence and an auxiliary power source power-on sequence, and monitoring the power-on sequence using the CPLD includes:
monitoring a main power supply by using a first counter in the CPLD, and stopping counting when the main power supply is at a high level to obtain a power-on time sequence of the main power supply;
and monitoring the main power supply by using a second counter in the CPLD, and stopping counting when the auxiliary power supply is at a high level to obtain a power-on time sequence of the auxiliary power supply.
3. The server power-on failure detection method according to claim 2, wherein monitoring the main power supply by using the first counter in the CPLD comprises:
monitoring a first power supply of the primary power supply using a first set of registers in a first counter in the CPLD;
a second supply of the primary power source is monitored using a second set of registers in a first counter in the CPLD.
4. The method of claim 1, wherein reading the power-on sequence and uploading the power-on sequence to a cloud server by using a BMC comprises:
and reading the power-on time sequence in the register by utilizing the BMC through the I2C link, and uploading the power-on time sequence to the cloud server through the I2C link.
5. The method of claim 1, wherein after the BMC reads the power-on sequence and uploads the power-on sequence to the cloud server, the method further comprises:
and the cloud server calculates the difference between adjacent registers in the power-on time sequence according to the register counting sequence, and compares the difference with a preset standard value to obtain the comparison result.
6. The server power-on failure detection method according to claim 1, wherein the CPLD is further configured to record a flashing state of the LED lamp.
7. A server power-on failure detection system, comprising:
the starting module is used for receiving a power-on instruction and starting the CPLD according to the power-on instruction;
the monitoring module is used for monitoring a power-on time sequence by utilizing the CPLD and storing the power-on time sequence in a register of the CPLD;
the uploading module is used for reading the power-on time sequence by using the BMC and uploading the power-on time sequence to the cloud server;
the comparison result receiving module is used for receiving a comparison result returned by the cloud server after the cloud server compares the power-on time sequence with the normal time sequence;
and the fault determining module is used for determining a power-on fault signal according to the comparison result.
8. The system for detecting a power-on failure of a server according to claim 7, further comprising:
and the comparison module is arranged on the cloud server and used for calculating the difference value between adjacent registers in the power-on time sequence according to the register counting sequence and comparing the difference value with a preset standard value to obtain the comparison result.
9. A computer-readable storage medium, having a computer program stored thereon, the computer program, when being executed by a processor, implementing the steps of the method for power-on failure detection of a server according to any of the claims 1-6.
10. A server, comprising a memory having a computer program stored therein and a processor that implements the steps of the method for power-on failure detection of a server according to any of claims 1-6 when the processor invokes the computer program in the memory.
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| CN113868101A (en) * | 2021-12-06 | 2021-12-31 | 苏州浪潮智能科技有限公司 | Server time sequence detection method, device and system |
| CN114724527A (en) * | 2022-03-18 | 2022-07-08 | 海宁奕斯伟集成电路设计有限公司 | Time sequence control chip, time sequence control system, time sequence monitoring method and display |
| TWI801030B (en) * | 2021-12-01 | 2023-05-01 | 新加坡商鴻運科股份有限公司 | A server power-on sequence debugging system |
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