CN112953562B - Signal processing device and signal processing method - Google Patents
Signal processing device and signal processing method Download PDFInfo
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- CN112953562B CN112953562B CN201911176802.7A CN201911176802A CN112953562B CN 112953562 B CN112953562 B CN 112953562B CN 201911176802 A CN201911176802 A CN 201911176802A CN 112953562 B CN112953562 B CN 112953562B
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- H—ELECTRICITY
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/156—Encoding or decoding using time-frequency transformations, e.g. fast Fourier transformation
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Abstract
A signal processing device comprises a memory device and a processor. The memory device stores at least one phase shift matrix. The processor reads the phase shift matrix from the memory device and generates an output sequence according to an input sequence and the phase shift matrix. The phase shift matrix is generated according to a basic matrix and a preset phase shift amount (k), the basic matrix is used for generating a code sequence, and the output sequence is the result of the input sequence after being subjected to phase shift for k cycles.
Description
Technical Field
The present invention relates to a signal processing apparatus, and more particularly, to a signal processing apparatus capable of performing a rapid sequence rearrangement.
Background
In the data transmission process of the communication system, the timing and frequency of the transmitting end and the receiving end must be synchronized first to execute the subsequent data transmission. A Pseudo random (Pseudorandom Noise, abbreviated PN) or Pseudo Noise (PN) code sequence is a sequence that is often used when timing and frequency synchronization is performed. The transmitting end and the receiving end can generate a PN code sequence according to the same mechanism with the same initial value (also called seed). The transmitting end embeds the PN code sequence in a signal and transmits the signal to the receiving end. The receiving end performs correlation operation on the PN code sequence and one or more phase shifted results of the PN code sequence and the received signal to estimate the timing offset and the frequency offset generated by the transmission channel effect. After compensating the timing offset and the frequency offset, the receiving end can successfully decode the correct data.
Since the PN code sequence is a Cyclic sequence (Cyclic sequence) which is sequentially generated according to the input of seeds into a linear feedback shift register (Linear Feedback Shift Register, abbreviated as LFSR) circuit, wherein the output bits are generally generated according to the values of the previous stage or stages of shift registers, in the prior art, the phase-shifted PN code sequence actually needs to be derived according to the sequentially shifting the values of the shift registers to the next stage. For example, if the PN code sequence (i.e., phase shifted by k frequency cycles) with respect to the time index (n+k) needs to be derived from the current time index (n), the PN code sequence of the time index (n) needs to be pushed forward by k cycles, wherein the LFSR circuit can derive one bit of the PN code sequence at each frequency cycle.
However, when k is a large value, the receiver has to wait for a large number of frequency cycles to obtain the required PN code sequence, thus resulting in a problem of poor efficiency.
Disclosure of Invention
The present invention is directed to a signal processing method and a related signal processing apparatus, so as to solve the above-mentioned problem of poor efficiency. According to the signal processing method and the signal processing device provided by the invention, PN code sequences can be rearranged (permutation) according to the required phase shift amount rapidly, and the required PN code sequences can be obtained without waiting for a plurality of frequency cycles as in the prior art, thus effectively solving the problem of poor efficiency in the prior art.
An embodiment of the present invention provides a signal processing method for a signal processing apparatus including a processor, the signal processing method including the steps of, performed by the processor: generating a base matrix according to at least one set of base coefficients, wherein the base coefficients are used to generate at least one bit of a code sequence; generating a phase shift matrix according to a preset phase shift amount and the basic matrix; and generating an output sequence according to an input sequence and the phase shift matrix, wherein the output sequence is a result of the input sequence after being subjected to phase shift for k cycles, and k is the preset phase shift amount.
Another embodiment of the present invention provides a signal processing method for a signal processing apparatus, the signal processing apparatus including a processor and a memory device, the signal processing method including the steps performed by the processor of: storing a plurality of phase shift matrices in the memory device, wherein the phase shift matrices are generated according to a base matrix and different phase shift amounts, and the base matrix is used for generating a code sequence; selecting a corresponding phase shift matrix from the phase shift matrices according to a preset phase shift amount; and generating an output sequence according to an input sequence and a corresponding phase shift matrix, wherein the output sequence is a result of the input sequence after being phase-shifted by k cycles, and k is the preset phase shift amount.
In another embodiment of the present invention, a signal processing apparatus includes a memory device and a processor. The memory device stores at least one phase shift matrix. The processor is coupled to the memory device, reads the phase shift matrix from the memory device, and generates an output sequence according to an input sequence and the phase shift matrix. The phase shift matrix is generated according to a base matrix and a preset phase shift amount, the base matrix is used for generating a code sequence, and the output sequence is the result of the input sequence after being phase-shifted by k cycles, wherein k is the preset phase shift amount.
Drawings
Fig. 1 is an exemplary block diagram illustrating a signal processing apparatus according to an embodiment of the present invention.
Fig. 2 is an exemplary circuit diagram illustrating a linear feedback shift register circuit according to one embodiment of the present invention.
Fig. 3 is an exemplary diagram illustrating a base matrix according to one embodiment of the invention.
Fig. 4 is an exemplary schematic diagram illustrating a phase shift matrix according to one embodiment of the present invention.
Fig. 5 is an exemplary diagram illustrating a base matrix according to another embodiment of the present invention.
Fig. 6 is an exemplary schematic diagram illustrating a phase shift matrix according to another embodiment of the present invention.
Fig. 7 is an example flowchart showing a signal processing method according to the first embodiment of the present invention.
Fig. 8 is an example flowchart showing a signal processing method according to a second embodiment of the present invention.
Fig. 9 is an example flowchart showing a signal processing method according to a third embodiment of the present invention.
Detailed Description
Fig. 1 is an exemplary block diagram illustrating a signal processing apparatus according to an embodiment of the present invention. The signal processing device 100 may at least include a processor 110 and a memory device 120. According to an embodiment of the present invention, the processor 110 may directly generate an output sequence according to an input sequence and a predetermined phase shift amount (k), wherein the output sequence is a result of shifting the input sequence by k frequency cycles, where k is a positive integer.
Generally, a Cyclic sequence (e.g., a PN code sequence) is generated by a Linear Feedback Shift Register (LFSR) circuit, wherein the generated Cyclic sequence has a corresponding period N according to a feedback mechanism and a connection relationship of each stage of registers in the LFSR circuit. That is, after the input sequence is pushed for N frequency cycles, the output sequence begins to produce a repetitive bit pattern.
In the embodiment of the present invention, the output sequence is generated by not feeding the input sequence into the LFSR circuit and continuously pushing the input sequence for a plurality of frequency cycles, but can be rapidly derived directly from the operation of the matrix. More specifically, in an embodiment of the present invention, the processor 110 may derive a sequence generation matrix (the base matrix) according to a mechanism (e.g., at least one polynomial) for generating a code sequence, where the polynomial may be derived according to a circuit design (i.e., a design of a connection relationship between a feedback mechanism of the circuit and each stage, etc.) of the LFSR circuit for generating the code sequence. The processor 110 may then directly derive the desired output sequence from multiplying the input sequence by the power of the base matrix. Assuming that the desired output sequence is the result of the input sequence being phase shifted by k frequency cycles, the processor 110 directly obtains the desired output sequence by multiplying the input sequence by the k-th power of the basis matrix.
Fig. 2 is an exemplary circuit diagram illustrating a linear feedback shift register circuit according to one embodiment of the present invention. The Linear Feedback Shift Register (LFSR) circuit 200 includes 10-bit shift registers SR (0) to SR (9). The shift registers SR (0) -SR (9) may be respectively assigned an initial value, wherein the initial value of the shift registers is called a seed. Next, the LFSR circuit 200 sequentially generates output bits in response to a clock unit (clock) of the clock signal CLK to become an output sequence seq_out. Assuming that the current time index is n, the following relationship can be derived according to the circuit design of the LFSR circuit 200:
x0 (n+1) =x2 (n) +x9 (n) formula (1)
Formula (2) of x1 (n+1) =x0 (n)
x2 (n+1) =x1 (n) formula (3)
Formula (4) of x3 (n+1) =x2 (n)
x4 (n+1) =x3 (n) formula (5)
Formula (6) of x5 (n+1) =x4 (n)
Formula (7) of x6 (n+1) =x5 (n)
Formula (8) of x7 (n+1) =x6 (n)
Formula (9) of x8 (n+1) =x7 (n)
Formula x9 (n+1) =x8 (n) (10)
Wherein x0 (n) to x9 (n) are values of the shift registers SR (0) to SR (9) at the time point n, respectively, and x0 (n+1) to x9 (n+1) are values of the shift registers SR (0) to SR (9) at the time point n+1, respectively.
Equation (1) through equation (10) show the relationship of the values buffered in the shift register when the bit data is shifted forward (forward), where the forward direction is the direction in which the bit data is pushed, and can also be considered as the direction in which the bit data flows with increasing time index value (i.e., the bit data moves toward the next stage shift register with increasing time index value).
Fig. 3 is an exemplary diagram illustrating a base matrix according to an embodiment of the present invention. The base matrix 310 is generated based on a polynomial derived based on the circuit design of the LFSR circuit 200, for example, the relationship equations (1) to (10) described above. Thus, in this embodiment, the base matrix 310 generates a matrix for a forward sequence. More specifically, the processor 110 may take the coefficients of each of the relationships (1) to (10) into a plurality of row vectors (row vectors), and generate the base matrix 310 according to the row vectors. As shown in fig. 3, the base coefficient 300 is a row vector (row vector) constituting the base matrix 310, and the base coefficient 300 is generated according to the relational formula (1) to generate at least one bit of the code sequence. According to one embodiment of the present invention, the base coefficient 300 is the first row vector (Top row vector) of the base matrix 310, and the other sets of coefficients generated according to the relationship formulas (2) to (10) sequentially form the second to last row vectors (Bottom row vector) of the base matrix 310.
Fig. 3 also shows a method of generating an output sequence from an input sequence and a basis matrix. According to one embodiment of the invention, the processor 110 may directly multiply the input sequence 320 with the base matrix 310 to produce the output sequence 330.
In accordance with one embodiment of the present invention, assuming that the desired output sequence is the result of the input sequence being phase shifted by k frequency cycles, the processor 110 directly obtains the desired output sequence by multiplying the input sequence by the k power of the base matrix.
Fig. 4 is an exemplary schematic diagram illustrating a phase shift matrix according to one embodiment of the present invention. In this embodiment, the processor 110 generates the sequences x0 (n+2) to x9 (n+2) after 2 frequency cycles of forward phase shift according to the sequences x0 (n) to x9 (n), so that the processor 110 directly obtains the desired output sequence 430 by multiplying the input sequence 420 with the phase shift matrix 410, wherein the phase shift matrix 410 is the power of the 2 nd of the base matrix 310 (i.e., the phase shift matrix 410 is the result of squaring the base matrix 310).
In other words, in the embodiment of the present invention, if a sequence of k frequency cycles is to be generated, the k th power of the basic matrix is only needed to be deduced as the phase shift matrix, so that the PN code sequence can be rearranged according to the required phase shift k, without waiting for the LFSR circuit to push k frequency cycles according to the initial seed as in the prior art, so as to obtain the required PN code sequence.
The base matrix 310 shown in fig. 3 and the phase shift matrix 410 shown in fig. 4 are both forward sequence generating matrices. In the embodiment of the present invention, the relation between the shift register values of each stage when the bit data is shifted in the reverse direction (backward) can be derived from the same LFSR circuit. Also taking the circuit diagram shown in fig. 2 as an example, assuming that the current time index is n, the following relationship can be derived according to the circuit design of the LFSR circuit 200:
x0 (n-1) =x1 (n) formula (11)
x1 (n-1) =x2 (n) formula (12)
x2 (n-1) =x3 (n) formula (13)
x3 (n-1) =x4 (n) formula (14)
x4 (n-1) =x5 (n) formula (15)
x5 (n-1) =x6 (n) formula (16)
x6 (n-1) =x7 (n) formula (17)
x7 (n-1) =x8 (n) formula (18)
x8 (n-1) =x9 (n) formula (19)
x9 (n-1) =x0 (n) +x3 (n) formula (20)
Wherein x0 (n-1) to x9 (n-1) are values of the shift registers SR (0) to SR (9) at the time point n-1, respectively.
Equation (11) through equation (20) show the relationship of the values buffered in the shift register when the bit data is shifted in the opposite direction to the direction in which the bit data is pushed.
Fig. 5 is an exemplary diagram illustrating a base matrix according to another embodiment of the present invention. The base matrix 510 is generated based on a polynomial derived from the circuit design of the LFSR circuit 200, for example, the above-mentioned relational expressions (11) to (20). Thus, in this embodiment, the base matrix 510 is a reverse sequence generation matrix. More specifically, the processor 110 may take the coefficients of each of the relations (11) to (20) into a plurality of row vectors, and generate the base matrix 510 according to the row vectors. As shown in fig. 5, the base coefficient 500 is a row of vectors constituting the base matrix 510, and the base coefficient 500 is generated according to the relation (20) to generate at least one bit of the code sequence. According to one embodiment of the present invention, the base coefficient 500 is the last vector of the base matrix 510, and each set of coefficients generated according to the relations (11) to (20) sequentially form the first to last row vectors of the base matrix 510.
Fig. 5 also illustrates a method of generating an output sequence from an input sequence and a base matrix, and the processor 110 may directly multiply the input sequence 520 with the base matrix 510 to generate an output sequence 530.
Fig. 6 is an exemplary schematic diagram illustrating a phase shift matrix according to another embodiment of the present invention, wherein the phase shift matrix 610 also generates a matrix for the reverse sequence. In this embodiment, the processor 110 generates the sequences x0 (n-2) to x9 (n-2) after 2 frequency cycles of the reverse phase shift according to the sequences x0 (n) to x9 (n), so that the processor 110 directly obtains the desired output sequence 630 by multiplying the input sequence 620 with the phase shift matrix 610, wherein the phase shift matrix 610 is the power of the base matrix 510 (i.e., the phase shift matrix 610 is the result of squaring the base matrix 510).
Based on the above concepts, the present invention may further comprise a variety of different embodiments. According to the first embodiment of the present invention, the memory device 120 may store a base matrix derived from a generation mechanism of a predetermined code sequence. The processor 110 may read the base matrix from the memory device 120 and generate an output sequence based on the input sequence and the base matrix as described above. For example, to generate a sequence of phase shifted k frequency cycles, the processor 110 simply multiplies the input sequence by the k-th power of the base matrix to directly obtain the desired output sequence.
Fig. 7 is an exemplary flowchart illustrating a signal processing method according to a first embodiment of the present invention, which includes the following steps performed by the processor 110:
step 702, a base matrix is generated according to at least one set of base coefficients, wherein the base coefficients are used to generate at least one bit of a code sequence.
In step S704, the basic matrix is stored in the memory device 120.
Step S706, generating a phase shift matrix according to the required phase shift amount (k) and the base matrix.
Step 708, an output sequence is generated according to the input sequence and the phase shift matrix, wherein the output sequence is a result of the input sequence after being phase-shifted by k cycles.
Note that if substantially the same result is obtained, other steps may be interposed therebetween, or one or more steps may be omitted. For example, if the base matrix has been derived, or the memory device 120 already has the base matrix stored, step S702 may be omitted, and step S704 may be adapted to read the base matrix from the memory device 120 for the processor 110 to perform subsequent calculations. In addition, as can be seen from the formulas (2) to (10), the future values of the shift registers of the 2 nd to 10 th stages are the current values of the shift registers of the previous stage, so in step S702, the base matrix can be derived only according to a set of base coefficients, wherein the remaining content of the base matrix (for example, the second to last row vectors when the base matrix is a forward sequence generating matrix) only needs to be correspondingly filled with the coefficients 0 and 1 at the position. However, if the mechanism for generating the code sequence or the corresponding polynomial is complex, in step S702, the base matrix may be derived from more than one set of base coefficients, wherein the base coefficients are also derived from the code sequence generation mechanism.
According to the second embodiment of the present invention, the memory device 120 may store one or more phase shift matrices derived from the base matrix. The processor 110 may read a desired phase shift matrix from the memory device 120 based on the desired amount of phase shift (k) and generate an output sequence based on the input sequence and the phase shift matrix as described above. For example, to generate a sequence of phase shift k frequency cycles, the processor 110 simply multiplies the input sequence by a phase shift matrix corresponding to the phase shift k to directly obtain the desired output sequence.
Fig. 8 is an exemplary flowchart illustrating a signal processing method according to a second embodiment of the present invention, which includes the following steps performed by the processor 110:
step S802 stores one or more phase shift matrices in the memory device 120, wherein the phase shift matrices are generated according to a base matrix and different phase shift amounts as described above.
Step S804, selecting a corresponding phase shift matrix according to a preset phase shift amount (k).
Step S806, an output sequence is generated according to the input sequence and the phase shift matrix, wherein the output sequence is the result of the input sequence after being phase-shifted by k cycles.
Note that if substantially the same result is obtained, other steps may be interposed therebetween, or one or more steps may be omitted. For example, if the memory device 120 already has a phase shift matrix, step S802 may be omitted. In addition, the selection in step S804 may include an operation of reading the memory device 120.
In addition to the above embodiments of dynamically/real-time calculating the output sequence according to the input sequence or dynamically/real-time deriving the phase shift matrix according to the base matrix, the present invention may also store the calculation result in the memory device 120 in advance and directly obtain the required output sequence according to the table look-up method.
According to the third embodiment of the present invention, the memory device 120 may also store various results of phase shifting an input sequence for different amounts of phase shift (and/or for different input sequences). The processor 110 can directly read the corresponding output sequence from the memory device 120 according to the required phase shift amount (k) and the input sequence. For example, if a sequence of k frequency cycles is to be generated, the processor 110 only needs to query a pre-established table according to the content of the input sequence and the corresponding phase shift k to obtain what the corresponding output sequence is, so as to directly obtain the required output sequence.
Fig. 9 is an exemplary flowchart illustrating a signal processing method according to a third embodiment of the present invention, which includes the following steps performed by the processor 110:
in step S902, one or more output sequences corresponding to different phase shift amounts of the input sequences are derived in advance, wherein the deriving method can use the matrix operation.
Step S904, the above-mentioned deriving result is stored in the memory device 120, and a look-up table is correspondingly established, wherein an input sequence can establish an independent look-up table for recording the output sequence corresponding to each phase shift.
Step S906, the lookup table is queried according to the content of the input sequence and the required phase shift k to obtain a corresponding output sequence. More specifically, the processor 110 can determine which address of the memory device 120 the corresponding output sequence is stored in according to the lookup table, and then access the corresponding address of the memory device 120 to obtain the required output sequence.
Note that if substantially the same result is obtained, other steps may be interposed therebetween, or one or more steps may be omitted. For example, after steps S902 and S904 are completed, in the case that the generation mechanism of the input sequence and the code sequence is not changed, the subsequent operation only needs to execute step S906.
To sum up, in the embodiment of the present invention, if a sequence of phase-shifted k frequency cycles is to be generated, the required sequence can be obtained rapidly only by the operation of the matrix or by the table look-up method. Therefore, the PN code sequence can be rearranged according to the required phase shift k and the matrix generated by the corresponding sequence, and the required PN code sequence can be obtained without waiting for the LFSR circuit to push k frequency cycles according to the initial seed in the prior art, thereby effectively solving the problem of poor efficiency in the prior art.
In particular, when the value of k is very close to the period N of the cyclic sequence, for example, k= (N-1), it takes a lot of computation time to generate the required output sequence if the LFSR circuit can only wait for (N-1) frequency cycles to run out in the prior art. This problem is often plagued by system designers with timing and frequency synchronization operations in communication systems. This is because when timing and frequency synchronization are performed, the timing offset and frequency offset are accurately estimated by attempting to perform correlation operation on the seed sequence and the received signal as a result of the seed sequence being phase-shifted by a plurality of different phase shifts. In addition, the LFSR circuit in the prior art cannot generate the sequence in the opposite direction. Therefore, in the prior art, the synchronization operation consumes too much time because the value of k is large. However, since the forward phase shift (N-1) of the seed sequence is equivalent to the reverse phase shift of the seed sequence by 1 cycle, the signal processing method and the signal processing device provided by the present invention can directly obtain the required output sequence by directly multiplying the seed sequence by the reverse sequence generating matrix, so that the above-mentioned problem of too long operation time for generating the required sequence can be effectively solved.
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
[ symbolic description ]
100. Signal processing device
110. Processor and method for controlling the same
120. Memory device
200. Linear feedback shift register circuit
300. Base coefficient 500
310. 510 basis matrix
320. 420, 520, 620 input sequence
410. 610 phase shift matrix
CLK frequency signal
The sequence is output by seq_Out, 330, 430, 530, 630
SR(0)、SR(1)、SR(2)、SR(3)、SR(4)、
SR(5)、SR(6)、SR(7)、SR(8)、SR(9)x0(n)、
x1(n)、x2(n)、x3(n)、x4(n)、x5(n)、x6(n)、
Shift register value
x7(n)、x8(n)、x9(n)、x0(n+1)、x1(n+1)、
x2(n+1)、x3(n+1)、x4(n+1)、x5(n+1)、
x6(n+1)、x7(n+1)、x8(n+1)、x9(n+1)
Claims (4)
1. A signal processing method for a signal processing apparatus, the signal processing apparatus comprising a processor, the signal processing method comprising the steps performed by the processor of:
generating a base matrix according to a plurality of base coefficients, wherein the base coefficients are used for generating at least one bit of a code sequence;
generating a phase shift matrix according to a preset phase shift amount and the basic matrix; and
generating an output sequence based on an input sequence and the phase shift matrix,
wherein the output sequence is the result of the input sequence after being phase shifted by k cycles, wherein k is the preset phase shift amount,
wherein a set of said basis coefficients is a row of vectors constituting said basis matrix,
and wherein the phase shift matrix is to the power of the k of the base matrix, and the step of generating the output sequence from the input sequence and the phase shift matrix further comprises:
the input sequence is multiplied by the phase shift matrix to produce the output sequence.
2. A signal processing method for a signal processing apparatus, the signal processing apparatus comprising a processor and a memory device, the signal processing method comprising the steps of, performed by the processor:
storing a plurality of phase shift matrices in the memory device, wherein the phase shift matrices are generated according to a base matrix and different phase shift amounts, and the base matrix is used for generating a code sequence;
selecting a corresponding phase shift matrix from the plurality of phase shift matrices according to a preset phase shift amount; and
generating an output sequence according to an input sequence and the phase shift matrix,
wherein the output sequence is the result of the input sequence after being phase shifted by k cycles, wherein k is the preset phase shift amount,
wherein the base matrix is generated from a plurality of sets of base coefficients, the base coefficients being used to generate at least one bit of the code sequence, and a set of the base coefficients being a row of vectors constituting the base matrix,
and wherein the corresponding phase shift matrix is the k power of the base matrix, and the step of generating the output sequence from the input sequence and the corresponding phase shift matrix further comprises:
multiplying the input sequence with the corresponding phase shift matrix to produce the output sequence.
3. A signal processing apparatus comprising:
a memory device storing at least one phase shift matrix; and
a processor coupled to the memory device, reading the phase shift matrix from the memory device, and generating an output sequence based on an input sequence and the phase shift matrix,
wherein the phase shift matrix is generated according to a base matrix and a predetermined phase shift amount, the base matrix is used for generating a code sequence, and the output sequence is the result of the input sequence after being phase-shifted by k cycles, wherein k is the predetermined phase shift amount,
wherein the processor further generates the base matrix based on a plurality of sets of base coefficients, the base coefficients being used to generate at least one bit of the code sequence, and a set of the base coefficients being a row of vectors constituting the base matrix,
and wherein the phase shift matrix is the kth power of the base matrix, and the processor multiplies the input sequence with the phase shift matrix to produce the output sequence.
4. The signal processing device of claim 3 wherein the processor further generates a plurality of phase shift matrices based on the different amounts of phase shift and the base matrix and stores the phase shift matrices in the memory device.
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