CN112953507B - Physical unclonable function circuit based on level shifter and control method thereof - Google Patents
Physical unclonable function circuit based on level shifter and control method thereof Download PDFInfo
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Abstract
The invention provides a physical unclonable function circuit based on a level shifter and a control method thereof, wherein the circuit comprises: the mode control module is used for sending out a mode control signal according to the control signal, wherein the mode control signal comprises a level conversion mode control signal and a PUF output mode control signal; and the mode switching module is connected with the mode control module and is used for shifting and converting the input signal into a power level signal of a second voltage and outputting the power level signal from the output end when receiving the level conversion mode control signal and outputting a level signal of 0 or 1 from the output end when receiving the PUF output mode control signal so as to generate a physical unclonable random number, wherein the first voltage is smaller than the second voltage. The circuit allows the working mode to be switched between the level shifter and the PUF, and can be improved on the basis of the level shifter circuit, and has a simple structure.
Description
Technical Field
The invention relates to the technical field of electric technology, in particular to a physical unclonable function circuit based on a level shifter and a control method of the physical unclonable function circuit based on the level shifter.
Background
In the internet of things era, security and privacy have attracted widespread attention. The challenges facing implementing security functions on resource-limited internet of things devices have prompted researchers to develop more advanced, lighter-weight solutions.
Physical unclonable functions (PUFs, physical Unclonable Function) are used as an emerging lightweight hardware to protect management keys and verify device security, beyond traditional cryptographic algorithms that store confidential key information in non-volatile memory (NVM), increasingly being applied to internet of things devices.
In addition, in the electronic circuit design of the new generation of internet of things equipment, with the introduction of low-voltage logic, the problem of uncoordinated input/output logic often occurs in the system, so that the complexity of the system design is improved. For example, when a 1.8V digital circuit communicates with an analog circuit operating at 3.3V, the problem of switching between the two levels needs to be solved first, and a level shifter is needed.
In the related art, a level conversion function and a PUF function are generally implemented by a level shifter and a PUF circuit, respectively. This would undoubtedly increase the hardware facilities and structural complexity of the internet of things device.
Disclosure of Invention
The first object of the present invention is to solve the above-mentioned technical problems, and to provide a physical unclonable function circuit based on a level shifter, which allows the operation mode to be switched between the level shifter (differential mode input) and the PUF (common mode input), and which can be improved on the basis of the level shifter circuit, and which has a simple structure, i.e. the level shifter and PUF functions can be realized by a simple circuit, and the integration of related devices is improved.
A second object of the present invention is to provide a method for controlling a physical unclonable function circuit of a level shifter.
The technical scheme adopted by the invention is as follows:
An embodiment of the first aspect of the present invention proposes a physical unclonable function circuit based on a level shifter, comprising: the mode control module is used for receiving a control signal and sending out a mode control signal according to the control signal, wherein the mode control signal comprises a level conversion mode control signal and a PUF output mode control signal; the mode switching module is connected with the mode control module, and is used for shifting and converting an input signal of an input end into a power level signal of a second voltage and outputting the power level signal from an output end when receiving the level conversion mode control signal and outputting a level signal of 0 or 1 from the output end when receiving the PUF output mode control signal so as to generate a physical unclonable random number, wherein the first voltage is smaller than the second voltage.
The physical unclonable function circuit based on the level shifter provided by the invention can also have the following additional technical characteristics:
According to one embodiment of the invention, the mode control module comprises: the control electrode of the first NMOS tube is used for receiving the control signal, the first electrode of the first NMOS tube is connected with the input end, and the second electrode of the first NMOS tube is connected with the inverting input end.
According to one embodiment of the invention, the on voltage of the first NMOS transistor is 0.3V-0.4V.
According to one embodiment of the invention, the mode switching module comprises: the control electrode of the second NMOS tube is used as an input end, and the conduction voltage of the second NMOS tube is the first voltage; the control electrode of the third NMOS tube is used as the input end of the inverting input end; the input end of the first inverter is connected with the substrate lead of the second NMOS tube, the output end of the first inverter is connected with the substrate lead of the third NMOS tube, and the power supply end of the first inverter is connected with the power level signal of the first voltage; the cross-coupled PMOS pair comprises a first PMOS tube and a second PMOS tube, wherein a first pole of the first PMOS tube is connected with a first pole of the second PMOS tube and then connected with a power level signal of the second voltage, a second pole of the first PMOS tube is connected with a control pole of the second PMOS tube and then connected with a first pole of the second NMOS tube, a second pole of the second NMOS tube is grounded, a second pole of the second PMOS tube is connected with a control pole of the first PMOS tube and then connected with a first pole of the third NMOS tube, and a second pole of the third NMOS tube is grounded; the input end of the second inverter is connected with the first pole of the second NMOS tube, the output end of the second inverter is used as the output end, and the power supply end of the second inverter is connected with the power supply level signal of the second voltage; and the input end of the third inverter is connected with the first pole of the third NMOS tube, the output end of the third inverter is used as the inverting output end, and the power end of the third inverter is connected with the power level signal of the second voltage.
According to one embodiment of the present invention, when the control signal received by the control electrode of the first NMOS transistor is a low level signal, the mode switching module shifts and converts the input signal into a power level signal of a second voltage and outputs the power level signal from the output terminal; when the control signal received by the control electrode of the first NMOS tube is a high-level signal, the mode switching module outputs the level signal of 0 or 1 from the output end so as to generate the physical unclonable random number.
An embodiment of the second aspect of the present invention proposes a control method of a physical unclonable function circuit based on a level shifter, comprising the steps of: receiving a control signal and sending a mode control signal according to the control signal, wherein the mode control signal comprises a level conversion mode control signal and a PUF output mode control signal; when the level conversion mode control signal is received, when an input signal of an input end is a logic signal of a first voltage, the input signal is shifted and converted into a power level signal of a second voltage and is output from an output end; upon receiving the PUF output mode control signal, a level signal of "0" or "1" is output from the output terminal to generate a physically unclonable random number, wherein the first voltage is smaller than the second voltage.
The invention has the beneficial effects that:
The invention allows the working mode to be switched between the level shifter (differential mode input) and the PUF (common mode input), can be improved on the basis of a level shifter circuit, has simple structure, can realize the level shift and PUF functions through a simple circuit, and improves the integration of related equipment.
Drawings
FIG. 1 is a block schematic diagram of a level shifter based physical unclonable function circuit in accordance with one embodiment of the present invention;
FIG. 2 is a circuit topology of a level shifter based physical unclonable function circuit in accordance with one embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a second inverter A2 and a third inverter A3 according to one embodiment of the invention;
fig. 4 is a circuit schematic of a first inverter A1 according to one embodiment of the invention;
FIG. 5 is an output waveform diagram of the circuit shown in FIG. 2;
FIG. 6 is a schematic diagram of a simulated waveform of a level shifter according to one specific example of the present invention;
FIG. 7 is a diagram of an inter-chip Hamming distance distribution according to one specific example of the present invention;
FIG. 8 is a schematic representation of BER over a range of temperatures according to one specific example of the present invention;
FIG. 9 is a schematic representation of BER over a range of supply voltages according to one specific example of the present invention;
FIG. 10 is a schematic illustration of autocorrelation test results in accordance with one specific example of the present invention; .
Fig. 11 is a diagram of power consumption and energy consumption at different bit rates according to a specific example of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a block schematic diagram of a level shifter based physical unclonable function circuit in accordance with one embodiment of the present invention. As shown in fig. 1, the circuit includes: a mode control module 1 and a mode switching module 2.
The mode control module 1 is configured to receive a control signal Vctr and send out a mode control signal according to the control signal, where the mode control signal includes a level conversion mode control signal and a PUF output mode control signal; the mode switching module 2 is connected to the mode control module 1, and the mode switching module 2 is configured to shift and convert an input signal into a power level signal of a second voltage and output the power level signal from the output terminal out when receiving a level conversion mode control signal and output a level signal of "0" or "1" from the output terminal when receiving a PUF output mode control signal, so as to generate a physical unclonable random number, where the first voltage is smaller than the second voltage.
Specifically, the operation mode of the circuit can be switched by changing the control signal received by the mode control module 1 according to the actual requirement. When the mode switching module 2 receives the level shift mode control signal, the mode switching module 2 may shift-convert the low input voltage logic signal to a higher power supply level signal. When the mode switching module 2 receives the PUF output mode control signal, it can output a level signal of "0" or "1" based on random uncertainty of the circuit node metastable state to the PMOS transistor for sequential conduction, thereby generating a physical unclonable random number. And the mode switching module 2 is improved on the basis of the level shifter. Therefore, the circuit allows the working mode to be switched between the level shifter (differential mode input) and the PUF (common mode input), can be improved on the basis of the level shifter circuit, has a simple structure, can realize the level shift and the PUF functions through a simple circuit, and improves the integration of related equipment.
According to one embodiment of the present invention, as shown in fig. 2, the mode control module 1 may include: the first NMOS tube N1, the control electrode of the first NMOS tube N1 is a signal receiving end, the control electrode of the first NMOS tube N1 is used for receiving the control signal Vctr, the first electrode of the first NMOS tube N1 is connected with the input end in, and the second electrode of the first NMOS tube N1 is connected with the inverting input endAre connected. The control signal Vctr may be a high level signal or a low level signal.
According to an embodiment of the present invention, the on voltage of the first NMOS transistor N1 may be 0.3V to 0.4V.
Specifically, the first NMOS transistor N1 may employ a low threshold device for attenuating voltage drop due to the transmission resistor of the first NMOS transistor N1 to enable the input in and the inverting input terminalThe signals of (2) are extremely symmetrical, and the output reliability of the PUF can be effectively improved.
According to one embodiment of the present invention, as shown in fig. 2, the mode switching module 2 may include: the second NMOS tube N2, the third NMOS tube N3, the first inverter A1, the cross-coupled PMOS pair, the second inverter A2 and the third inverter A3, wherein the cross-coupled PMOS pair comprises a first PMOS tube P1 and a second PMOS tube P2,
The control electrode of the second NMOS tube N2 is used as an input end in, and the conducting voltage of the second NMOS tube N2 is the first voltage; the control electrode of the third NMOS transistor N3 is used as an inverting input endThe input end of the first inverter A1 is connected with the substrate lead of the second NMOS tube, the output end of the first inverter A1 is connected with the substrate lead of the third NMOS tube N3, and the power supply end of the first inverter A1 is connected with the power supply level signal VDDL of the first voltage; the cross-coupled PMOS pair comprises a first PMOS tube P1 and a second PMOS tube P2, wherein a first pole of the first PMOS tube P1 is connected with a first pole of the second PMOS tube P2 and then is connected with a power level signal VDDH of a second voltage, a second pole of the first PMOS tube P1 is connected with a control pole of the second PMOS tube P2 and then is connected with a first pole of the second NMOS tube N2, a second pole of the second NMOS tube N2 is grounded, a second pole of the second PMOS tube P2 is connected with a control pole of the first PMOS tube P1 and then is connected with a first pole of the third NMOS tube N3, and a second pole of the third NMOS tube N3 is grounded; the input end of the second inverter A2 is connected with the first pole of the second NMOS tube N2, the output end of the second inverter A2 is used as an output end out, and the power supply end of the second inverter A2 is connected with a power supply level signal VDDH of a second voltage; the input end of the third inverter A3 is connected with the first pole of the third NMOS tube N3, and the output end of the third inverter A3 is used as an inverting output endThe power supply terminal of the third inverter is connected to the power level signal VDDH of the second voltage.
Specifically, as shown in fig. 2, a first node a exists between the second pole of P1, the input terminal of A2 and the first pole of N2, a second node B exists between the second pole of P2, the input terminal of A3 and the first pole of N3, and the second NMOS transistor N2 may be a low threshold device. In the level conversion mode, the Vctr terminal is at a low level, when the input terminal "in" is inputted at a high level, N1 is turned off, N2 and P2 are turned on, N3 and P1 are turned off, and due to the positive feedback effect of the cross-coupled PMOS on the P1 and P2 tubes, the low input voltage "in" terminal (its logic high is V DDL) can output the high level of VDDH at the node B, thereby realizing the movement of the logic high level from VDDL to VDDH. Subsequently, if the low input voltage "in" terminal goes low, N3 and P1 will be activated, resulting in the output of node B being low. Thus, a level shifter with a differential common-source voltage logic gate may convert a low input voltage logic signal to a higher power supply level signal.
In the PUF mode, vctr is high, and when the input terminal "in" is low, N1 is turned on, and the input terminal "in" and the inverting input terminalThe same is low and N2 and N3 are off, which will cause nodes a and B to be in a metastable state. Depending on the conduction current between N2 and N3, the level states of nodes a and B latch up with the supply Voltage (VDDH) or Ground (GND), i.e. the level of nodes a and B may be high or low. When the input in rises from a low level to a high level, N2 and N3 are theoretically turned on, so the voltages at nodes a and B will drop simultaneously. However, due to the slightly different on-currents I 1 and I 2 during the change in conduction of N2 and N3, P1 or P2 is activated faster than the other, which in turn results in positive feedback to promote the output response to stabilize at '0' or '1'.
In the present invention, the main entropy source of the PUF comes from the NMOS transistor pair (N2, N3). Optimizing the size of the NMOS transistor pairs can reduce power consumption, area, and increase randomness due to process variations. Furthermore, to avoid the effect of unbalance on the PUF output, an inverter may be added as a buffer at both nodes A, B. At the same time, N1 adopts a low threshold device for attenuating the voltage drop formed by the transmission resistance of N1, so that the input terminal 'in' and the inverting input terminalThe signals of (2) are extremely symmetrical, and the output reliability of the PUF can be effectively improved.
In very large scale integrated circuit designs, level shifters are used to connect signals between different power domains, and since the power consumption of a circuit is proportional to the square of the current, the method of reducing the power consumption by optimizing the operating current of the circuit cells at different voltages is very effective. As shown in fig. 2, the only overhead per response bit of the level shifter circuit is the overhead of turning on a single NMOS rectifier and allowing the operating mode of the circuit to switch between level shifter (differential mode input) and PUF (common mode input).
In the present invention, the circuit schematic of the second inverter A2 and the third inverter A3 (i.e. the inverter with logic high level VDDH) can be shown in fig. 3, MP3 is PMOS, MN3 is PMOS; the circuit schematic of the first inverter A1 (i.e. the inverter with logic high level VDDL) can be shown in fig. 4, MP4 is PMOS, and MN4 is PMOS. The output waveform diagram of the circuit shown in fig. 2 can be seen with reference to fig. 5.
And (3) experimental verification:
The performance of the above proposed level shifter based physical unclonable function circuit of the present invention in terms of PUF uniqueness, reliability, randomness, speed and power consumption will be described and analyzed experimentally. The proposed PUF was simulated by Cadence Virtuoso Spectre under a commercial 65nm CMOS process. The collected data is further processed by MATLAB scripts.
The transfer characteristics of the level-shifting function are first verified before testing the performance of the PUF. As shown in FIG. 6, the simulation waveform diagram of converting the input signal of 20MHz and 0.6V into 1.2V shows that the invention can well convert the sub-threshold voltage into the standard voltage, vin represents the input signal, vout represents the output signal and tin represents the time.
The uniqueness, reliability, randomness, speed and power consumption of PUF functions are verified as follows.
1. Uniqueness of the product
The degree of difference between CRPs (stimulus pairs) generated by different PUF instances is measured uniqueness, estimated by averaging the inter-chip hamming distances (HAMMING DISTANCE, HD). The uniqueness U of the PUF is expressed as follows:
where m is the total number of PUF devices, ru and Rv are random output bit streams of two different PUF devices with the same stimulus C, n is the bit length, where n=128.
In an ideal case, the uniqueness of the PUF should be 50%, which means that PUF instances can be completely distinguished and have the greatest decorrelation. Under nominal conditions (1.2 v,27 ℃) an MC simulation of 1000 iterations was performed to evaluate the uniqueness of the PUF. Fig. 7 shows the HD distribution of the proposed PUF, count representing the number of PUFs at a hamming distance, histogram representing the Histogram and Fitted representing the fit value. The gaussian distribution curve with standard deviation δ=4.42% fits well with the mean μ= 49.11%.
2. Reliability of
Another characteristic of PUFs is reliability, which evaluates whether CRP generated by one PUF under the same stimulus is stable under different operating conditions (e.g. different supply voltages, temperatures, etc.), typically expressed in Bit Error Rate (BER). BER refers to the percentage of the number of bits in error relative to the total number of bits in the generated bit stream. The reliability S is typically calculated as follows:
Where Ri is the response of random stimulus C under nominal conditions (1.2 v,27 ℃). Ri, j is the response at different operating conditions, the same stimulus C. k is the number of times the same stimulus C evaluates the same PUF. An ideal PUF must have 100% reliability.
The reliability of the PUF is evaluated by BER (temperature range-20-100 ℃ c, power supply voltage range 1.0V-1.5V) under different conditions. 1000 CRPs were collected under each condition to calculate reliability. Fig. 8 and 9 plot simulation results with worst case reliability at 100 ℃ and 1.0V. The normalized BER per 10℃and 0.1V was 1.98% and 2.2%, respectively.
3. Randomness of
Randomness estimates are the uncertainties or unpredictabilities of CRPs generated by PUFs. Good PUFs have a high randomness, which means that an attacker has difficulty in successfully predicting with a small amount of CRPs collected. To evaluate randomness, the national institute of standards Technology (National Institute of STANDARDS AND Technology, NIST) randomness test and autocorrelation test were performed.
1) NIST randomness test: the NIST SP800 statistical test suite is an important test suite for randomness analysis. 10000 original PUF response bits were collected in the experiment and the NIST test results are shown in table 1. The P-values are used to measure the degree of randomness and all P-values should be greater than 0.01 to achieve 99% confidence in any random source. It can be seen from the table that the PUF passes all NIST tests (other items not shown are not performed due to the limited bit stream length), which means that the random bit sequence generated by the PUF has a high randomness.
2) Autocorrelation test: autocorrelation is the cross-correlation of a signal with itself at different points in time. An autocorrelation function (autocorrelation function, ACF) may be used to calculate the autocorrelation of the random bit sequence to determine whether it is independent and uniformly distributed. Fig. 10 shows the ACF test results for 50000CRP with a confidence interval of ± 0.0089 at a confidence level of 95% and a lower limit that proves to be not vulnerable to correlation power analysis attacks, LAG LENGTH representing the hysteresis length.
4. Speed and power
In order to further evaluate the performance of the new PUF designed, its power consumption and bit rate are measured. Fig. 11 shows the relationship between power consumption, energy consumption per bit and bit rate at 27 c and 1.2V. In this design, the maximum bit rate that enables normal operation in both modes of operation is 20Mbps, at which time the power consumption is 14.39W and the power consumption per bit is 0.72pJ/b.
5. Performance comparison
The PUF performance presented herein is compared to the latest weak PUF design. In comparison to several PUFs based on existing hardware resources, we can conclude that the PUFs presented herein are significantly superior to other PUFs in terms of reliability and uniqueness over the temperature and supply voltage range. The energy consumption per bit (0.72 pJ) of the proposed PUF is reduced by 1% compared to the structure in ISCAS'19[6], and has a higher operating frequency of 20MHz. In addition to this, it is most notable that we succeeded for the first time in creating a weak PUF pattern using the idea of a level shifter. In the PUF structure based on the cross-coupled level shifter, the cost of each response bit is only a single NMOS transistor, which can be ignored in the overall layout, so that the proposed design has the characteristics of low energy consumption and low cost of each response bit.
6. Conclusion(s)
A high performance, low overhead weak PUF circuit structure is presented that extracts entropy for the first time from commercial level shifter designs. Based on the original level shifter circuit, the NMOS switch transistor is the only cost of each response bit when the PUF works, so that the traditional cross-coupling level shifter circuit can be easily switched between a differential mode and a common mode. The proposed PUF cell extracts entropy by exploiting the inherent process variations of two NMOS transistors controlled by common mode signals, resulting in a random response sequence, and performs MC simulation with 49.11% uniqueness using a standard 65nm CMOS process. In the worst case, the reliability is 95.31% and 96.09% respectively in the range of the power supply voltage of 1.0V to 1.5V at the temperature of-20 ℃ to 100 ℃. The maximum bit rate and the optimal energy consumption per bit are 20Mbps and 0.72pJ/b. The design can be improved on the original level shifter circuit, and the low cost and low energy efficiency of only one additional NMOS transistor per bit make the design a promising hardware security primitive of the Internet of things equipment.
From the foregoing, it can be seen that the present invention extracts differential information from inherent process variations of cross-coupled level shifters (CCLSs) in existing integrated circuit chips. The CCLS may convert voltages between different levels to allow different circuit modules to operate in different power domains with optimized energy efficiency. In the circuit of the present invention, a single switching transistor is embedded in the level shifter, i.e., each response bit changes the operating mode of the CCLS from differential to common mode. By exploiting the uncertainty of the output voltage due to the different switching times of the two PMOS in the cross-coupled network, the serial number of the PUF can be extracted at common mode action. Experiments show that the PUF circuit can generate serial number uniqueness 49.11%, reliability 96.09%, power supply voltage 1.0V-1.5V and temperature 95.31% fluctuation between-20 deg.C and 100 deg.C by using standard 65 nm analog CMOS process. At a high load of 20Mbps,1.2V,27 ℃, the energy per bit is only 0.72pJ/b.
In summary, the physical unclonable function circuit based on the level shifter according to the embodiment of the present invention allows the working mode to be switched between the level shifter (differential mode input) and the PUF (common mode input), and can be improved on the basis of the level shifter circuit, so that the level shifter and PUF functions can be realized through a simple circuit, the integration of related devices is improved, and experiments prove that the sub-threshold voltage can be well converted into the standard voltage when the level shifter circuit works in the level shifter mode, and the performance in terms of PUF uniqueness, reliability, randomness, speed, power consumption and the like is better when the PUF output mode works.
Based on the physical unclonable function circuit based on the level shifter, the invention also provides a control method of the physical unclonable function circuit based on the level shifter. Since the control method of the present invention is based on the above-mentioned circuit, details not disclosed in the method can be referred to the above-mentioned circuit embodiment, and the details of the present invention will not be described in detail.
The control method of the physical unclonable function circuit based on the level shifter comprises the following steps:
S1, receiving a control signal and sending a mode control signal according to the control signal, wherein the mode control signal comprises a level conversion mode control signal and a PUF output mode control signal.
S2, when the level conversion mode control signal is received, and the input signal of the input end is a logic signal of a first voltage, the input signal is shifted and converted into a power level signal of a second voltage, and the power level signal is output from the output end.
S3, when the PUF output mode control signal is received, a level signal of 0 or 1 is output from an output end to generate a physical unclonable random number, wherein the first voltage is smaller than the second voltage.
According to the control method of the physical unclonable function circuit based on the level shifter, disclosed by the embodiment of the invention, the working mode is allowed to be switched between the level shifter (differential mode input) and the PUF (common mode input), the improvement can be performed on the basis of the level shifter circuit, the structure is simple, the level shifting and PUF functions can be realized through a simple circuit, and the integration of related equipment is improved.
In the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. The meaning of "a plurality of" is two or more, unless specifically defined otherwise.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction. In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and additional implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order from that shown or discussed, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present invention.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. As with the other embodiments, if implemented in hardware, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.
The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like. While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (4)
1. A physical unclonable function circuit based on a level shifter, characterized by comprising the following steps:
The mode control module is used for receiving a control signal and sending out a mode control signal according to the control signal, wherein the mode control signal comprises a level conversion mode control signal and a PUF output mode control signal;
The mode switching module is connected with the mode control module and is used for shifting and converting an input signal of an input end into a power level signal of a second voltage and outputting the power level signal from an output end when receiving the level conversion mode control signal and outputting a level signal of 0 or 1 from the output end when receiving the PUF output mode control signal so as to generate a physical unclonable random number, wherein the first voltage is smaller than the second voltage;
Wherein, the mode control module includes: the control electrode of the first NMOS tube is used for receiving the control signal, the first electrode of the first NMOS tube is connected with the input end, and the second electrode of the first NMOS tube is connected with the inverting input end;
the mode switching module includes:
The control electrode of the second NMOS tube is used as an input end, and the conduction voltage of the second NMOS tube is the first voltage;
The control electrode of the third NMOS tube is used as the inverting input end;
The input end of the first inverter is connected with the substrate lead of the second NMOS tube, the output end of the first inverter is connected with the substrate lead of the third NMOS tube, and the power supply end of the first inverter is connected with the power level signal of the first voltage;
the cross-coupled PMOS pair comprises a first PMOS tube and a second PMOS tube, wherein a first pole of the first PMOS tube is connected with a second pole of the first PMOS tube and then connected with a power level signal of the second voltage, a second pole of the first PMOS tube is connected with a control pole of the second PMOS tube and then connected with a first pole of the second NMOS tube, a second pole of the second NMOS tube is grounded, a second pole of the second PMOS tube is connected with a control pole of the first PMOS tube and then connected with a first pole of the third NMOS tube, and a second pole of the third NMOS tube is grounded;
The input end of the second inverter is connected with the first pole of the second NMOS tube, the output end of the second inverter is used as the output end, and the power supply end of the second inverter is connected with the power supply level signal of the second voltage;
And the input end of the third inverter is connected with the first pole of the third NMOS tube, the output end of the third inverter is used as an inverting output end, and the power supply end of the third inverter is connected with the power level signal of the second voltage.
2. The level shifter-based physical unclonable function circuit of claim 1, wherein the turn-on voltage of the first NMOS transistor is 0.3V-0.4V.
3. The level shifter-based physical unclonable function circuit of claim 1, wherein,
When the control signal received by the control electrode of the first NMOS tube is a low-level signal, the mode switching module shifts and converts the input signal into a power level signal of a second voltage and outputs the power level signal from the output end;
When the control signal received by the control electrode of the first NMOS tube is a high-level signal, the mode switching module outputs the level signal of 0 or 1 from the output end so as to generate the physical unclonable random number.
4. A method of controlling a level shifter based physical unclonable function circuit according to any of claims 1-3, comprising the steps of:
Receiving a control signal and sending a mode control signal according to the control signal, wherein the mode control signal comprises a level conversion mode control signal and a PUF output mode control signal;
when the level conversion mode control signal is received, when an input signal of an input end is a logic signal of a first voltage, the input signal is shifted and converted into a power level signal of a second voltage and is output from an output end;
upon receiving the PUF output mode control signal, a level signal of "0" or "1" is output from the output terminal to generate a physically unclonable random number, wherein the first voltage is smaller than the second voltage.
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| US8583710B2 (en) * | 2010-09-17 | 2013-11-12 | Infineon Technologies Ag | Identification circuit and method for generating an identification bit using physical unclonable functions |
| WO2012069545A2 (en) * | 2010-11-24 | 2012-05-31 | Intrinsic Id B.V. | Physical unclonable function |
| CN103198267B (en) * | 2013-03-18 | 2015-12-09 | 宁波大学 | A kind of restructural multiport PUF circuit unit |
| CN103198268B (en) * | 2013-03-18 | 2016-06-08 | 宁波大学 | A kind of restructural multiport physics can not be cloned functional circuit |
| US9577637B2 (en) * | 2014-02-19 | 2017-02-21 | Altera Corporation | Stability-enhanced physically unclonable function circuitry |
| KR101799905B1 (en) * | 2016-02-17 | 2017-11-21 | 충북대학교 산학협력단 | Security chip for physical unclonable function using memory |
| CN110210257B (en) * | 2019-04-22 | 2023-06-27 | 深圳大学 | High-reliability physical unclonable function circuit based on two-tube structure voltage reference source |
| CN111130536B (en) * | 2019-12-09 | 2023-04-28 | 宁波大学 | Circuit with ageing detection and PUF functions |
| CN112017721B (en) * | 2020-07-07 | 2022-03-18 | 温州大学 | Weak physical unclonable function circuit based on leakage current |
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