CN112953187A - Method and system for inhibiting direct current bus capacitor current pulsation of double three-phase permanent magnet synchronous motor - Google Patents
Method and system for inhibiting direct current bus capacitor current pulsation of double three-phase permanent magnet synchronous motor Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/493—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode the static converters being arranged for operation in parallel
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P21/00—Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation
- H02P21/0003—Control strategies in general, e.g. linear type, e.g. P, PI, PID, using robust control
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P25/00—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details
- H02P25/02—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details characterised by the kind of motor
- H02P25/022—Synchronous motors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P25/00—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details
- H02P25/16—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details characterised by the circuit arrangement or by the kind of wiring
- H02P25/22—Multiple windings; Windings for more than three phases
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P29/00—Arrangements for regulating or controlling electric motors, appropriate for both AC and DC motors
- H02P29/50—Reduction of harmonics
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P2207/00—Indexing scheme relating to controlling arrangements characterised by the type of motor
- H02P2207/05—Synchronous machines, e.g. with permanent magnets or DC excitation
Abstract
The invention discloses a method and a system for inhibiting direct current bus capacitor current pulsation of a double three-phase permanent magnet synchronous motor, wherein the method comprises the steps of collecting current six-phase current of the double three-phase permanent magnet synchronous motor; respectively obtaining the direct current bus current I of the first inverter in each sector according to a preset relation table of the direct current bus current and the phase current under different voltage vectorsdc1A direct bus current I of a second inverterdc2(ii) a For each oneSector for converting the DC bus current I of the first inverterdc1A direct bus current I of a second inverterdc2And sequencing according to the magnitude of the amplitude, wherein the sequencing modes of the magnitude of the amplitude and the amplitude are opposite, and sequencing the switching vectors in the voltage vector sequences of the first inverter and the second inverter according to the sequenced sequence. The invention can ensure that the sum I of the currents of two independent inverters of the double three-phase permanent magnet synchronous motordcThe pulsation is minimum, thereby achieving the purpose of inhibiting the pulsation of the capacitance current of the direct current bus.
Description
Technical Field
The invention relates to a control technology of a double three-phase permanent magnet synchronous motor, in particular to a method and a system for inhibiting direct current bus capacitance current pulsation of the double three-phase permanent magnet synchronous motor.
Background
The double three-phase permanent magnet synchronous motor has advantages in fault tolerance, torque pulsation, power density and the like, and is widely applied to the high-power fields of electric automobiles, air conditioning systems and the like. The dual three-phase permanent magnet synchronous motor driving system is generally controlled by two independent first inverters and second inverters, and the two inverters are connected in parallel to the same dc bus capacitor, as shown in fig. 1. In the figure IdcIs a DC bus capacitor current equal to the two inverter DC currents Idc1And Idc2Sum, i.e. Idc＝Idc1+Idc2。
In the driving circuit, the bus capacitor of the double three-phase permanent magnet synchronous motor needs a large installation space, which increases the cost and reduces the power density of the system. The design criteria for the size of the dc bus capacitor are mainly determined by the operating current, the ambient temperature, and the voltage and current ripple. High frequency bus current ripple and conduction loss generally cause the bus capacitor to heat, and the increase of the working environment temperature requires more installation space and jeopardizes the stable operation of the system. Secondly, harmonic waves on the bus capacitor flow through the whole system connected with the direct current bus, the oscillation phenomenon of the system can be caused, and serious electromagnetic interference can be generated on the whole system. Therefore, the suppression of the harmonic wave of the capacitance current of the direct current bus is important for the stable operation of the driving system.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: aiming at the problems in the prior art, the invention provides a method and a system for inhibiting the direct current bus capacitor current pulsation of a double three-phase permanent magnet synchronous motordcThe pulsation is minimum, thereby achieving the purpose of inhibiting the pulsation of the capacitance current of the direct current bus.
In order to solve the technical problems, the invention adopts the technical scheme that:
a method for suppressing capacitor current ripple of a direct current bus of a double three-phase permanent magnet synchronous motor comprises the following steps of sequencing and optimizing voltage vector sequences of a first inverter and a second inverter in each switching period:
1) acquiring current six-phase current of a double three-phase permanent magnet synchronous motor;
2) respectively obtaining direct current bus currents corresponding to switching vectors of the voltage vector sequences of the first inverter and the second inverter in each sector according to a preset relation table of the direct current bus currents and phase currents under different voltage vectors, and obtaining direct current bus currents I of the first inverter in each sectordc1A direct bus current I of a second inverterdc2；
3) Respectively converting the direct current bus current I of the first inverter for each sectordc1A direct bus current I of a second inverterdc2Sequencing according to the amplitude and the sequencing mode of the amplitude are opposite, so that the direct current bus current I of the first inverterdc1A direct bus current I of a second inverterdc2The maximum value of one of the two is equal to the minimum value of the otherLaminated DC bus capacitor current Idc；
4) For each sector, respectively enabling the switching vector in the voltage vector sequence of the first inverter to be in accordance with the direct current bus current I of the first inverterdc1Sequencing the sequence after sequencing, wherein the switching vectors in the voltage vector sequence of the second inverter are according to the direct current bus current I of the second inverterdc2And sequencing the sequenced sequence to obtain a new voltage vector sequence of the first inverter and the second inverter.
Optionally, the six-phase current collected in step 1) of the dual three-phase permanent magnet synchronous motor includes three-phase current i corresponding to a first inverter of the dual three-phase permanent magnet synchronous motorA,iB,iCAnd the three-phase current i corresponding to the second inverterD,iE,iF。
Optionally, the relationship table of the dc bus current and the phase current preset in step 2) under different voltage vectors includes: when the voltage vectors of the first inverter are V respectively0～V7Time, direct bus current I of the first inverterdc1Are respectively 0, iA,-iC,iB,-iA,iC,-i B0, wherein iA,iB,iCRespectively refers to three-phase current corresponding to a first inverter of the three-phase permanent magnet synchronous motor, and when voltage vectors of a second inverter are respectively V0～V7Time, direct bus current I of the second inverterdc2Are respectively 0, iD,-iF,iE,-iD,iF,-i E0, wherein iD,iE,iFRespectively, the three-phase currents corresponding to the second inverter of the three-phase permanent magnet synchronous motor.
Optionally, the direct bus current I of the first inverter is respectively adjusted in step 3)dc1A direct bus current I of a second inverterdc2The ordering according to the magnitude of the amplitude and the opposite ordering mode of the two means that: direct bus current I of the first inverterdc1Arranging the direct current bus current I of the second inverter from small to large according to the amplitudedc2From large according to magnitude of amplitudeTo a small order.
Optionally, the direct bus current I of the first inverter is respectively adjusted in step 3)dc1A direct bus current I of a second inverterdc2The ordering according to the magnitude of the amplitude and the opposite ordering mode of the two means that: direct bus current I of the first inverterdc1Arranging the direct current bus current I of the second inverter according to the sequence of the magnitude of the amplitude from large to smalldc2The amplitudes are arranged in the order of small amplitude to large amplitude.
Optionally, step 1) is preceded by determining a dq-axis reference voltage vector
Reference voltage vector according to dq axis
Determining a voltage vector sequence of the first inverter and the second inverter and a duration of a switching vector in the voltage vector sequence; step 4) is followed by a step of outputting the new voltage vector sequence of both the first inverter and the second inverter, and the duration of the switching vector in the new voltage vector sequence as a control signal for the next switching period.
In addition, the invention also provides a device for inhibiting the direct current bus capacitance current ripple of the double three-phase permanent magnet synchronous motor, which comprises a microprocessor and a memory which are connected with each other, wherein the microprocessor is programmed or configured to execute the steps of the method for inhibiting the direct current bus capacitance current ripple of the double three-phase permanent magnet synchronous motor.
In addition, the invention also provides a computer readable storage medium, wherein a computer program programmed or configured to execute the method for suppressing the ripple of the direct current bus capacitance current of the double three-phase permanent magnet synchronous motor is stored in the computer readable storage medium.
In addition, the invention also provides a device for inhibiting the direct current bus capacitance current pulsation of the double three-phase permanent magnet synchronous motor, which comprises:
the current acquisition program unit is used for acquiring the current six-phase current of the double three-phase permanent magnet synchronous motor;
a direct current bus current calculation program unit, configured to obtain, according to a preset relationship table of direct current bus current and phase current under different voltage vectors, direct current bus currents corresponding to switching vectors of initial voltage vector sequences of the first inverter and the second inverter in each sector, and obtain a direct current bus current I of the first inverter in each sectordc1A direct bus current I of a second inverterdc2；
A direct current bus current sequencing program unit for sequencing the direct current bus current I of the first inverter for each sectordc1A direct bus current I of a second inverterdc2Sequencing in reverse order to make the direct bus current I of the first inverterdc1A direct bus current I of a second inverterdc2The maximum value of one of the two is overlapped with the minimum value of the other to form the direct current bus capacitance current Idc；
A voltage vector sequencing program unit for each sector according to the DC bus current I of the first inverterdc1A direct bus current I of a second inverterdc2The switching vectors in the initial voltage vector sequences of the first inverter and the second inverter are sequenced according to the same sequence to obtain new voltage vector sequences of the first inverter and the second inverter.
In addition, the invention also provides a system for inhibiting the capacitance current ripple of the direct current bus of the double three-phase permanent magnet synchronous motor, which comprises the double three-phase permanent magnet synchronous motor with an encoder, a control unit, a PWM generator and an inverter, wherein the speed acquisition input end of the control unit is connected with the encoder, the current acquisition input end of the control unit is respectively connected with the output lines of the double three-phase permanent magnet synchronous motor, the control unit is used for generating voltage vector sequences of a first inverter and a second inverter according to input signals, the PWM generator is used for executing the steps of the method for inhibiting the capacitance current ripple of the direct current bus of the double three-phase permanent magnet synchronous motor, and the duration time of a switching vector in a new voltage vector sequence is used as a control signal of the next switching period to be output to the inverter so as to realize.
Compared with the prior art, the invention has the following advantages: due to the capacitance current I of the DC busdcBy direct bus current I of the first inverterdc1A direct bus current I of a second inverterdc2The direct current bus current I of the first inverter is sequenced and optimized for each sector when the voltage vector sequences of the first inverter and the second inverter are sequenced and optimized in each switching perioddc1A direct bus current I of a second inverterdc2Sequencing in reverse order to make the direct bus current I of the first inverterdc1A direct bus current I of a second inverterdc2The maximum value of one of the two is overlapped with the minimum value of the other to form the direct current bus capacitance current IdcNamely: direct bus current I of the first inverterdc1Will be equal to the dc bus current I of the second inverterdc2Is overlapped by the maximum value of the direct bus current I of the first inverterdc1Will be equal to the dc bus current I of the second inverterdc2So that the direct bus capacitance current I can be enableddcThe ripple waves can be effectively inhibited, and the purpose of inhibiting the direct current bus capacitor current pulsation of the double three-phase permanent magnet synchronous motor can be achieved.
Drawings
Fig. 1 is a schematic circuit structure diagram of a conventional double three-phase permanent magnet synchronous motor.
Fig. 2 is a schematic diagram showing the projection of 64 voltage vectors onto the α - β and x-y sub-planes of the prior art maximum four-vector modulation.
Fig. 3 is an example of a PWM output waveform of a conventional maximum four vector modulation.
Fig. 4 is a current waveform simulation diagram of a conventional double three-phase permanent magnet synchronous motor.
Fig. 5 shows the voltage vector sequence and dc bus capacitance current of two inverters at time point K in the first sector shown in fig. 3 and 4.
FIG. 6 is a schematic diagram of a basic flow of a method according to an embodiment of the present invention.
Fig. 7 shows a sequence of voltage vectors and dc bus capacitance currents of two inverters at time K in the first sector according to an embodiment of the present invention.
Fig. 8 is a schematic structural diagram of a system according to an embodiment of the present invention.
Detailed Description
Fig. 1 is a schematic circuit diagram of a conventional double three-phase permanent magnet synchronous motor, and as can be seen from fig. 1, the double three-phase permanent magnet synchronous motor includes A, B, C, D, E, F common six phases, and is connected to a power grid through a first inverter (denoted as inverter 1) and a second inverter (denoted as inverter 2). The double three-phase permanent magnet synchronous motor can be represented in a rotating synchronous d-q coordinate system and an x-y subspace as follows:
in the above formula, ud,uq,Ld,Lq,id,iqStator voltage, inductance and current on the d-q axis, respectively; u. ofx,uy,ix,iyIs the voltage and current on the x-y axis; rsIs the stator resistance, wrIs the electrical angular velocity of the rotor, LlIs a leakage inductance, p is a differential operator,
is a permanent magnet flux linkage.
In the maximum four-vector modulation of the double three-phase permanent magnet synchronous motor, 2 is provided664 voltage vectors, in octal system SASBSC]-[SDSESF]Counting, when the upper bridge arm of the inverter is conducted, Si1(i ═ a, B, C, D, E, F); when the lower bridge arm of the inverter is conducted, S i0. These 64 voltage vectors can be projected onto the α - β sub-plane and the x-y sub-plane as shown in fig. 2, where sub-diagram (a) is the α - β sub-plane and sub-diagram (b) is the x-y sub-plane.
The maximum four-vector modulation method utilizes 12 maximum amplitude voltage vectors in an alpha-beta subspace to synthesize a reference voltage vector, and the vectors have the minimum voltage amplitude in an x-y subspace, so that the harmonic current problem of the x-y subspace can be restrained, and the method is widely applied to a double three-phase permanent magnet synchronous motor driving system at present. In maximum four vector modulation, the modulation duration of each voltage vector can be expressed as:
in the above formula, TsIs the switching period, Tk(k is 0,1,2,3,4) represents the kth time in the switching period,
is a voltage vector of d-q axis and x-y axis in the kth period,
is a reference voltage vector.
The action time and voltage vector of the maximum four-vector modulation shown in equation (3) can be used to synthesize the reference voltage. To simplify the analysis, the inverter switch numbers are arranged in a natural order and are illustrated as the first sector. The maximum four vector modulated PWM output waveform is given in fig. 3, where in one switching period TsThe interior is divided into six sections. It can be seen that each maximum four-vector is composed of two three-phase voltage vectors, e.g., T2Voltage vector V over a period of time45Vector V from the first inverter1(100)Vector V to second inverter6(101)And (4) forming. The relationship between the direct current bus current and the phase current of the double three-phase permanent magnet motor under different voltage vectors is shown in table 1:
table 1: the direct bus current and the phase current are in relation under different voltage vectors.
| Vector | V0(000) | V1(100) | V2(110) | V3(010) | V4(011) | V5(001) | V6(101) | V7(111) |
| Idc1 | 0 | iA | -iC | iB | -iA | iC | -iB | 0 |
| Idc2 | 0 | iD | -iF | iE | -iD | iF | -iE | 0 |
In addition, in a double three-phase permanent magnet synchronous motor driving system, the direct current bus current is the sum of two inverter bus currents, namely Idc＝Idc1+Idc2For voltage vector V45The DC bus current can be represented as Idc＝iA-iEAnd the other voltage vectors are analogized. The current waveform simulation diagram of the double three-phase permanent magnet synchronous motor is shown in fig. 4. In the figure, a dual three-phase permanent magnet synchronous machine operating at a current amplitude of 5.1A and a frequency of 25Hz, it can be seen that the DEF phase current lags the ABC phase current by 30 °. The reason for the dc bus capacitance current ripple will be described by taking the phase current at K point at 0.01s as an example.
The switching sequence and dc bus capacitance current for the two inverters at time point K in the first sector shown in fig. 3 and 4 are given in fig. 5. It can be seen that at different voltage vectors and durations, the dc bus current follows the rules of table 1 and is equal to the corresponding phase current. As shown in FIG. 5(c), under maximum four vector modulation, the DC current I of the first inverterdc1Maximum and DC current I of second inverterd2Overlap of the maximum values of, the direct current I of the first inverterdc1Minimum value and DC current I of second inverterdc2So that such a switching sequence causes large dc bus capacitance current ripple. In addition, the voltage vector changes from a zero vector to an active vector, or from an active vector to a zero vector, which causes the dc bus current to pulsate more frequently.
Based on the traditional maximum four-vector modulation theory, researches show that the direct current bus capacitance current pulsation can be reduced by the method described in the embodiment through analyzing the relation between the direct current bus capacitance current and the phase current of the double three-phase permanent magnet synchronous motor.
As shown in fig. 6, the method for suppressing ripple of dc bus capacitance current of a dual three-phase permanent magnet synchronous motor in this embodiment includes a step of performing sequencing optimization on voltage vector sequences (PWM switching vector sequences) of a first inverter and a second inverter in each switching cycle:
1) acquiring current six-phase current of a double three-phase permanent magnet synchronous motor;
2) respectively obtaining direct current bus currents corresponding to switching vectors of the voltage vector sequences of the first inverter and the second inverter in each sector according to a preset relation table of the direct current bus currents and phase currents under different voltage vectors, and obtaining direct current bus currents I of the first inverter in each sectordc1A direct bus current I of a second inverterdc2；
3) Respectively converting the direct current bus current I of the first inverter for each sectordc1A direct bus current I of a second inverterdc2Sequencing according to the amplitude and the sequencing mode of the amplitude are opposite, so that the direct current bus current I of the first inverterdc1A direct bus current I of a second inverterdc2The maximum value of one of the two is overlapped with the minimum value of the other to form the direct current bus capacitance current Idc；
4) For each sector, respectively enabling the switching vector in the voltage vector sequence of the first inverter to be in accordance with the direct current bus current I of the first inverterdc1Sequencing the sequence after sequencing, wherein the switching vectors in the voltage vector sequence of the second inverter are according to the direct current bus current I of the second inverterdc2And sequencing the sequenced sequence to obtain a new voltage vector sequence of the first inverter and the second inverter.
The six-phase current collected in the step 1) of the double three-phase permanent magnet synchronous motor comprises three-phase current i corresponding to a first inverter of the double three-phase permanent magnet synchronous motorA,iB,iCAnd the three-phase current i corresponding to the second inverterD,iE,iF。
With reference to table 1, see the drawings,the relationship table of the dc bus current and the phase current preset in step 2) of this embodiment under different voltage vectors includes: when the voltage vectors of the first inverter are V respectively0～V7Time, direct bus current I of the first inverterdc1Are respectively 0, iA,-iC,iB,-iA,iC,-i B0, wherein iA,iB,iCRespectively refers to three-phase current corresponding to a first inverter of the three-phase permanent magnet synchronous motor, and when voltage vectors of a second inverter are respectively V0～V7Time, direct bus current I of the second inverterdc2Are respectively 0, iD,-iF,iE,-iD,iF,-i E0, wherein iD,iE,iFRespectively, the three-phase currents corresponding to the second inverter of the three-phase permanent magnet synchronous motor.
As an alternative embodiment, the dc bus current I of the first inverter is respectively adjusted in step 3)dc1A direct bus current I of a second inverterdc2The ordering according to the magnitude of the amplitude and the opposite ordering mode of the two means that: direct bus current I of the first inverterdc1Arranging the direct current bus current I of the second inverter from small to large according to the amplitudedc2The amplitudes are arranged in the order of magnitude from large to small. In this way, the direct bus current I of the first inverter can be enableddc1Will be equal to the dc bus current I of the second inverterdc2Is overlapped by the maximum value of the direct bus current I of the first inverterdc1Will be equal to the dc bus current I of the second inverterdc2So that the direct bus capacitance current I can be enableddcThe ripple waves can be effectively inhibited, and the purpose of inhibiting the direct current bus capacitor current pulsation of the double three-phase permanent magnet synchronous motor can be achieved.
For convenience of illustration of the maximum four vector modulation of the proposed optimal switching sequence, the current at point K in the first sector in fig. 4 is still taken as an example. According to the rule of step 2), in inverter 1, Idc1_V1＝iA＝4.83A,Idc1_V2＝-iC＝1.84A,Idc1_V6＝iBThus, according to the proposed optimal switching sequence, the switching order of the voltage vector is Idc1_V2<Idc1_V6<Idc1_V1(ii) a In the inverter 2, Idc2_V1＝iD＝4.05A,Idc2_V6＝-iE4.65A, the switching order of the voltage vector is therefore Idc2_V6>Idc2_V1. Wherein, Idc1_V1,Idc1_V2,Idc1_V6Respectively representing a voltage vector V1,V2,V6Corresponding DC bus current I of the first inverterdc1，Idc2_V1，Idc2_V6Respectively representing a voltage vector V1,V6Corresponding DC bus current I of the second inverterdc2. The new voltage vector sequence for these two independent inverters is shown in table 2.
Fig. 7 shows the dc current at point K under maximum four vector modulation of the proposed optimal switching sequence. As shown in FIG. 7(c), Idc1Minimum value of (1) anddc2superposition of maximum values, Idc1Maximum value of (1) anddc2the minimum values are superposed to ensure that the current I on the direct current bus capacitordcThe ripple is much smoother than the conventional maximum four vector modulation method. This shows that optimizing the sequence of voltage vectors for the first inverter and the second inverter in each switching cycle reduces dc bus capacitor current ripple. Thus, in the first sector, there are 6 possible voltage vector sequences for the first inverter, as shown in table 3. For inverters, there are only two possible voltage vector sequences, Idc2_V6＞Idc2_V1Or Idc2_V6＜Idc2_V1. Therefore, the PWM pulse is generated by 2 × 6-12 switching sequences and other fansAs are the zones.
| Possible voltage vector sequences | Voltage vector | Duration of time | |
| 1 | Idc1_V6＜Idc1_V1＜Idc1_V2 | V6，V1，V1，V2 | T1，T2，T3，T4 |
| 2 | Idc1_V1＜Idc1_V6＜Idc1_V2 | V1，V1，V6，V2 | T2，T3，T1，T4 |
| 3 | Idc1_V6＜Idc1_V2＜Idc1_V1 | V6，V2，V1，V1 | T1，T4，T2，T3 |
| 4 | Idc1_V2＜Idc1_V6＜Idc1_V1 | V2，V6，V1，V1 | T4，T1，T2，T3 |
| 5 | Idc1_V1＜Idc1_V2＜Idc1_V6 | V1，V1，V2，V6 | T2，T3，T4，T1 |
| 6 | Idc1_V2＜Idc1_V1＜Idc1_V6 | V2，V1，V1，V6 | T4，T2，T3，T1 |
As another alternative, the dc bus current I of the first inverter is respectively adjusted in step 3)dc1A direct bus current I of a second inverterdc2The ordering according to the magnitude of the amplitude and the opposite ordering mode of the two means that: direct bus current I of the first inverterdc1Arranging the direct current bus current I of the second inverter according to the sequence of the magnitude of the amplitude from large to smalldc2The amplitudes are arranged in the order of small amplitude to large amplitude. . In this way, the direct bus current I of the first inverter can likewise be madedc1Will be equal to the dc bus current I of the second inverterdc2Is overlapped by the maximum value of the direct bus current I of the first inverterdc1Will be equal to the dc bus current I of the second inverterdc2So that the direct bus capacitance current I can be enableddcThe ripple waves can be effectively inhibited, and the purpose of inhibiting the direct current bus capacitor current pulsation of the double three-phase permanent magnet synchronous motor can be achieved.
Referring to fig. 6, determining the dq-axis reference voltage vector is further included before step 1) in this embodiment
Reference voltage vector according to dq axis
Determining a voltage vector sequence of the first inverter and the second inverter and a duration of a switching vector in the voltage vector sequence;
in this embodiment, step 4) is followed by a step of outputting a new voltage vector sequence of both the first inverter and the second inverter, and a duration of a switching vector in the new voltage vector sequence as a control signal of a next switching period.
In addition, the present embodiment further provides a device for suppressing ripple of dc bus capacitance current of a dual three-phase permanent magnet synchronous motor, which includes a microprocessor and a memory connected to each other, where the microprocessor is programmed or configured to execute the steps of the method for suppressing ripple of dc bus capacitance current of a dual three-phase permanent magnet synchronous motor.
Furthermore, the present embodiment also provides a computer-readable storage medium, in which a computer program programmed or configured to execute the aforementioned method for suppressing the ripple of the dc bus capacitance current of the dual three-phase permanent magnet synchronous motor is stored.
In addition, this embodiment still provides a two three-phase PMSM direct current bus capacitor current ripple suppression device, includes:
the current acquisition program unit is used for acquiring the current six-phase current of the double three-phase permanent magnet synchronous motor;
a DC bus current calculating program unit for calculating the DC bus current according to the presetThe direct current bus current and the phase current under different voltage vectors are respectively obtained from the relation table of the direct current bus current and the phase current under different voltage vectors, the direct current bus current corresponding to the switching vector of the initial voltage vector sequence of the first inverter and the second inverter in each sector is obtained, and the direct current bus current I of the first inverter in each sector is obtaineddc1A direct bus current I of a second inverterdc2；
A direct current bus current sequencing program unit for sequencing the direct current bus current I of the first inverter for each sectordc1A direct bus current I of a second inverterdc2Sequencing in reverse order to make the direct bus current I of the first inverterdc1A direct bus current I of a second inverterdc2The maximum value of one of the two is overlapped with the minimum value of the other to form the direct current bus capacitance current Idc；
A voltage vector sequencing program unit for each sector according to the DC bus current I of the first inverterdc1A direct bus current I of a second inverterdc2The switching vectors in the initial voltage vector sequences of the first inverter and the second inverter are sequenced according to the same sequence to obtain new voltage vector sequences of the first inverter and the second inverter.
As shown in fig. 8, this embodiment further provides a dual three-phase permanent magnet synchronous motor dc bus capacitance current ripple suppression system, which includes a dual three-phase permanent magnet synchronous motor 1 with an encoder, a control unit 2, a PWM generator 3 and an inverter 4, where a speed acquisition input end of the control unit 2 is connected to the encoder, and a current acquisition input end of the control unit is connected to an output line of the dual three-phase permanent magnet synchronous motor 1, the control unit 2 is configured to generate a voltage vector sequence of a first inverter and a second inverter according to an input signal, and the PWM generator 3 is configured to execute the steps of the aforementioned dual three-phase permanent magnet synchronous motor dc bus capacitance current ripple suppression method, and output a duration time of a switching vector in the new voltage vector sequence as a control signal of a next switching cycle to the inverter 4 to achieve dc bus capacitance current ripple suppression. Wherein, the control unit 2 is most similar to the traditional double three-phase permanent magnet synchronous motorThe large four-vector modulation method is the same and comprises the step of adopting Vector Space Decoupling (VSD) control, i in figure 8a～ifThree-phase current i corresponding to first inverter of double three-phase permanent magnet synchronous motorA,iB,iCAnd the three-phase current i corresponding to the second inverterD,iE,iFAnd θ e represents a phase. It should be noted that the method of the present embodiment is not dependent on the control algorithm in the specific control unit 2, but may be another control algorithm which is unexpected for the control algorithm shown in fig. 8.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (10)
1. A method for suppressing capacitor current ripple of a direct current bus of a double three-phase permanent magnet synchronous motor is characterized by comprising the following steps of sequencing and optimizing voltage vector sequences of a first inverter and a second inverter in each switching period:
1) acquiring current six-phase current of a double three-phase permanent magnet synchronous motor;
2) respectively obtaining direct current bus currents corresponding to switching vectors of the voltage vector sequences of the first inverter and the second inverter in each sector according to a preset relation table of the direct current bus currents and phase currents under different voltage vectors, and obtaining direct current bus currents I of the first inverter in each sectordc1A direct bus current I of a second inverterdc2；
3) Respectively converting the direct current bus current I of the first inverter for each sectordc1A direct bus current I of a second inverterdc2Sequencing according to the amplitude and the sequencing mode of the amplitude are opposite, so that the direct current bus current I of the first inverterdc1A direct bus current I of a second inverterdc2The maximum value of one of the two is overlapped with the minimum value of the other to form the direct current bus capacitance current Idc；
4) For each sector, respectively enabling the switching vector in the voltage vector sequence of the first inverter to be in accordance with the direct current bus current I of the first inverterdc1Sequencing the sequence after sequencing, wherein the switching vectors in the voltage vector sequence of the second inverter are according to the direct current bus current I of the second inverterdc2And sequencing the sequenced sequence to obtain a new voltage vector sequence of the first inverter and the second inverter.
2. The method for suppressing the capacitor current ripple of the direct current bus of the dual three-phase permanent magnet synchronous motor according to claim 1, wherein the step 1) of collecting the six-phase current of the dual three-phase permanent magnet synchronous motor comprises a three-phase current i corresponding to a first inverter of the dual three-phase permanent magnet synchronous motorA，iB，iCAnd the three-phase current i corresponding to the second inverterD，iE，iF。
3. The method for suppressing the ripple of the dc bus capacitance current of the dual three-phase permanent magnet synchronous motor according to claim 1, wherein the relationship table of the dc bus current and the phase current preset in step 2) under different voltage vectors includes: when the voltage vectors of the first inverter are V respectively0～V7Time, direct bus current I of the first inverterdc1Are respectively 0, iA，-iC，iB，-iA，iC，-iB0, wherein iA，iB，iCRespectively refers to three-phase current corresponding to a first inverter of the three-phase permanent magnet synchronous motor, and when voltage vectors of a second inverter are respectively V0～V7Time, direct bus current I of the second inverterdc2Are respectively 0, iD，-iF，iE，-iD，iF，-iE0, wherein iD，iE，iFRespectively, the three-phase currents corresponding to the second inverter of the three-phase permanent magnet synchronous motor.
4. According to the rightThe method for suppressing the direct current bus capacitance current ripple of the dual three-phase permanent magnet synchronous motor according to claim 1, wherein the direct current bus current I of the first inverter is respectively set in the step 3)dc1A direct bus current I of a second inverterdc2The ordering according to the magnitude of the amplitude and the opposite ordering mode of the two means that: direct bus current I of the first inverterdc1Arranging the direct current bus current I of the second inverter from small to large according to the amplitudedc2The amplitudes are arranged in the order of magnitude from large to small.
5. The method for suppressing the ripple of the dc bus capacitance current of the dual three-phase permanent magnet synchronous motor according to claim 1, wherein the dc bus current I of the first inverter is respectively adjusted in step 3)dc1A direct bus current I of a second inverterdc2The ordering according to the magnitude of the amplitude and the opposite ordering mode of the two means that: direct bus current I of the first inverterdc1Arranging the direct current bus current I of the second inverter according to the sequence of the magnitude of the amplitude from large to smalldc2The amplitudes are arranged in the order of small amplitude to large amplitude.
6. The method for suppressing the capacitor current ripple of the direct current bus of the double three-phase permanent magnet synchronous motor according to claim 1, wherein the step 1) is preceded by determining a dq-axis reference voltage vector
Reference voltage vector according to dq axis
Determining a voltage vector sequence of the first inverter and the second inverter and a duration of a switching vector in the voltage vector sequence; step 4) is followed by a step of outputting the new voltage vector sequence of both the first inverter and the second inverter, and the duration of the switching vector in the new voltage vector sequence as a control signal for the next switching period.
7. A device for suppressing capacitor current ripple of a DC bus of a dual three-phase permanent magnet synchronous motor, comprising a microprocessor and a memory which are connected with each other, wherein the microprocessor is programmed or configured to perform the steps of the method for suppressing capacitor current ripple of the DC bus of the dual three-phase permanent magnet synchronous motor according to any one of claims 1 to 6.
8. A computer readable storage medium having stored thereon a computer program programmed or configured to perform the method of suppression of ripple of DC bus capacitance current of a dual three-phase PMSM according to any of claims 1-6.
9. The utility model provides a two three-phase PMSM direct current bus capacitor current ripple suppression device which characterized in that includes:
the current acquisition program unit is used for acquiring the current six-phase current of the double three-phase permanent magnet synchronous motor;
a direct current bus current calculation program unit, configured to obtain, according to a preset relationship table of direct current bus current and phase current under different voltage vectors, direct current bus currents corresponding to switching vectors of initial voltage vector sequences of the first inverter and the second inverter in each sector, and obtain a direct current bus current I of the first inverter in each sectordc1A direct bus current I of a second inverterdc2；
A direct current bus current sequencing program unit for sequencing the direct current bus current I of the first inverter for each sectordc1A direct bus current I of a second inverterdc2Sequencing in reverse order to make the direct bus current I of the first inverterdc1A direct bus current I of a second inverterdc2The maximum value of one of the two is overlapped with the minimum value of the other to form the direct current bus capacitance current Idc；
A voltage vector sequencing program unit for each sector according to the DC bus current I of the first inverterdc1A direct bus current I of a second inverterdc2The switching vectors in the initial voltage vector sequences of the first inverter and the second inverter are sequenced according to the same sequence to obtain new voltage vector sequences of the first inverter and the second inverter.
10. A double three-phase permanent magnet synchronous motor direct current bus capacitance current pulsation suppression system is characterized by comprising a double three-phase permanent magnet synchronous motor (1) with an encoder, a control unit (2), a PWM generator (3) and an inverter (4), the speed acquisition input end of the control unit (2) is connected with the encoder, the current acquisition input end is respectively connected with the output circuit of the double three-phase permanent magnet synchronous motor (1), the control unit (2) is used for generating a voltage vector sequence of the first inverter and the second inverter according to an input signal, the PWM generator (3) is used for executing the steps of the method for suppressing the DC bus capacitance current ripple of the double three-phase permanent magnet synchronous motor according to any one of claims 1 to 6, and the duration of the switching vector in the new voltage vector sequence is used as a control signal of the next switching period and is output to the inverter (4) so as to realize the suppression of the current ripple of the direct current bus capacitor.
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