CN112951922A - SiC power MOSFET device integrated with ESD and preparation method - Google Patents
SiC power MOSFET device integrated with ESD and preparation method Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims abstract description 164
- 238000002513 implantation Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 97
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 97
- 150000002500 ions Chemical class 0.000 claims description 48
- 239000000758 substrate Substances 0.000 claims description 35
- 239000004065 semiconductor Substances 0.000 claims description 25
- 210000000746 body region Anatomy 0.000 claims description 22
- 239000002019 doping agent Substances 0.000 claims 7
- 239000012535 impurity Substances 0.000 claims 5
- 230000015556 catabolic process Effects 0.000 abstract description 15
- 230000010354 integration Effects 0.000 abstract description 4
- 238000000206 photolithography Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000003466 welding Methods 0.000 description 21
- 238000002347 injection Methods 0.000 description 15
- 239000007924 injection Substances 0.000 description 15
- 230000001413 cellular effect Effects 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
- H10D84/141—VDMOS having built-in components
- H10D84/143—VDMOS having built-in components the built-in components being PN junction diodes
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- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/01—Manufacture or treatment
- H10D12/031—Manufacture or treatment of IGBTs
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
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Abstract
本发明提供了一种集成ESD的SiC功率MOSFET器件及其制备方法，由于用于ESD的PN结二极管是集成在MOSFET器件本身需要的栅极压焊区下方，不需要额外的芯片面积，不会影响芯片的集成度。且栅极压焊区的面积较大，使得PN结二极管的面积也可以较大，PN结二极管环绕在栅极压焊区的下方，可以利用栅极压焊区的面积，增大PN结二极管的面积提高ESD泄放能力；由于通过调节PN结边缘的形貌和掺杂浓度就可以调节PN结二极管的击穿电压，因此通过在第一掺杂离子重注入区和第二掺杂离子注入区的边缘设置多个尖峰角，就可以调节PN结二极管的击穿电压；且所述PN结二极管的形成是和形成MOSFET器件的工艺步骤同步进行，不额外增加光刻掩膜步骤，不会增加芯片制作成本。
The invention provides an ESD-integrated SiC power MOSFET device and a preparation method thereof. Since the PN junction diode used for ESD is integrated under the gate pressure-bonding region required by the MOSFET device itself, no additional chip area is required, and no additional chip area is required. Affect the integration of the chip. And the area of the gate pressure bonding area is large, so that the area of the PN junction diode can also be larger. The PN junction diode is surrounded under the gate pressure bonding area, and the area of the gate pressure bonding area can be used to increase the PN junction diode. The area of the PN junction improves the ESD discharge capability; because the breakdown voltage of the PN junction diode can be adjusted by adjusting the morphology and doping concentration of the PN junction edge, the first doping ion re-implantation region and the second doping ion implantation By setting multiple peak angles at the edge of the region, the breakdown voltage of the PN junction diode can be adjusted; and the formation of the PN junction diode is performed synchronously with the process steps of forming the MOSFET device, without additional photolithography mask steps, no Increase the cost of chip fabrication.
Description
Technical Field
The invention relates to the field of SiC power devices, in particular to an ESD (electro-static discharge) integrated SiC power MOSFET device and a preparation method thereof.
Background
In the semiconductor field, electrostatic discharge (ESD) can damage devices in a chip, particularly devices with an extremely thin gate dielectric such as MOSFET devices, and a high electric field is generated at a gate, so that the gate dielectric is subjected to insulation breakdown under the high electric field, and the device fails. The electrostatic protection means that when an object or a human body with static electricity contacts the chip, voltage or current generated by the static electricity can be rapidly eliminated, so that the purpose of protecting a chip device is achieved. Among various reliability test standards, there is a standard for electrostatic discharge (ESD), so electrostatic protection is also an important criterion in device design.
In the existing silicon-based MOSFET and IGBT devices, it is a common design to use a diode as an integrated ESD, please refer to fig. 1, a diode D1 is connected between the gate and the source of the MOSFET device M1, when electrostatic discharge generates a high electric field at the gate of the MOSFET device M1, before the gate dielectric is subjected to insulation breakdown under the action of the high electric field, the PN junction of the diode D1 is preferentially broken down, so that the gate of the MOSFET device M1 is prevented from being broken down, thereby achieving the purpose of protecting the chip device.
However, in the existing silicon-based MOSFET and IGBT devices, since the breakdown voltage of the silicon-based PN junction diode is very low, the silicon-based ESD diode is usually disposed in polysilicon of a gate, and the diode is obtained by doping polysilicon of N-type and P-type. However, this method not only requires an additional photolithography plate and increases the cost of the product, but also affects the gate oxide characteristics of the MOSFET and the IGBT due to the integration of the diode in the polysilicon of the gate.
Disclosure of Invention
The invention provides an ESD integrated SiC power MOSFET device and a preparation method thereof, aiming at overcoming the defects of the prior art, a PN junction diode can be integrated at two ends of a grid electrode and a source electrode of a silicon carbide MOSFET device under the condition of not increasing a photoetching mask, the electrostatic protection of the grid electrode is realized by utilizing the higher breakdown voltage (usually more than 40V) of the SiC PN junction diode, the PN junction diode and a body region and a source region of the MOSFET device are injected together, and the breakdown voltage of the PN junction diode can be adjusted by adjusting the appearance and doping concentration of the edge of the PN junction.
In order to achieve the above object, an embodiment of the present invention provides an ESD integrated SiC power MOSFET device, including a silicon carbide semiconductor substrate, where the silicon carbide semiconductor substrate includes a MOSFET cell region and a gate bonding region, and includes a silicon carbide substrate and a silicon carbide epitaxial layer located on a surface of the silicon carbide substrate; a drain electrode on the other surface of the silicon carbide semiconductor substrate;
the gate structure is positioned on the surface of the silicon carbide epitaxial layer of the MOSFET cellular region, and the gate-source dielectric covers the gate structure; the first doped ion implantation base region is positioned on two sides of the grid structure and in the silicon carbide epitaxial layer of the MOSFET cellular region; a first doped ion re-implantation body region and a second doped ion implantation source region which are positioned in the first doped ion implantation base region, and source electrodes positioned on the surfaces of the first doped ion re-implantation body region and the second doped ion implantation source region; the first doped ion implantation region and the second doped ion implantation region are positioned in the silicon carbide epitaxial layer of the grid electrode pressure welding region, the first doped ion implantation region and the second doped ion implantation region of the grid electrode pressure welding region form a PN junction diode, the first doped ion implantation region of the grid electrode pressure welding region and the first doped ion re-implantation body region or the first doped ion implantation base region of the MOSFET cellular region are formed and connected at the same time, the second doped ion implantation region of the grid electrode pressure welding region and the second doped ion implantation source region of the MOSFET cellular region are formed at the same time, and the edges of the first doped ion implantation region and the second doped ion implantation region have a plurality of sharp peak angles; the gate structure of the bonding area is positioned on the surface of the silicon carbide epitaxial layer of the gate bonding area, the gate electrode is positioned on the surface of the gate structure of the bonding area, the gate structure of the bonding area is connected with the gate structure, an opening is formed in the gate structure of the bonding area and exposes out of the surface of the second doped ion injection area, and the gate electrode covers the exposed surface of the second doped ion injection area and the surface of the gate structure of the bonding area.
Optionally, the angle of the peak angle is greater than 0 degrees and less than 180 degrees.
Optionally, the number of the second doped ion implantation regions in the first doped ion implantation region is one or more.
Optionally, the edges of the first doped ion implantation region and the second doped ion implantation region are zigzag.
Optionally, the second doped ion implantation region is in a shape of a square ring or a rectangle ring, a square or a rectangle.
Optionally, the PN junction diode is a ring edge PN junction diode.
The embodiment of the invention also provides a preparation method of the ESD integrated SiC power MOSFET device, which comprises the following steps:
providing a silicon carbide semiconductor substrate, wherein the silicon carbide semiconductor substrate comprises a MOSFET cellular region and a grid electrode pressure welding region, and the silicon carbide semiconductor substrate comprises a silicon carbide substrate and a silicon carbide epitaxial layer positioned on the surface of the silicon carbide substrate;
forming a drain electrode on the other surface of the silicon carbide semiconductor substrate;
forming a first doped ion implantation base region in the silicon carbide epitaxial layer of the MOSFET cellular region and at the positions on two sides of the gate structure;
forming a first doped ion re-injection body region in the first doped ion injection base region, forming a first doped ion injection region in the silicon carbide epitaxial layer of the grid electrode pressure welding region, and simultaneously forming and connecting the first doped ion injection region of the grid electrode pressure welding region and the first doped ion re-injection body region or the first doped ion injection base region of the MOSFET cellular region;
forming a second doped ion implantation source region in the first doped ion implantation base region at two sides of the grid structure, forming a second doped ion implantation region in the first doped ion implantation region corresponding to the opening position of the grid structure in the pressure welding region, simultaneously forming the second doped ion implantation region of the grid pressure welding region and the second doped ion implantation source region of the MOSFET cellular region, wherein the edges of the first doped ion implantation region and the second doped ion implantation region are provided with a plurality of sharp peak angles, and the first doped ion implantation region and the second doped ion implantation region form a PN junction diode;
forming a grid structure on the surface of the silicon carbide epitaxial layer of the MOSFET cellular area, forming a pressure welding area grid structure on the surface of the silicon carbide epitaxial layer of the grid pressure welding area, wherein the grid structure and the pressure welding area grid structure are formed and connected at the same time, and the pressure welding area grid structure is provided with an opening to expose the silicon carbide epitaxial layer at the position of the first doped ion injection area at the bottom;
forming a grid source electrode medium covering the surface of the grid structure, forming source electrode on the surfaces of the first doped ion re-injection body region and the second doped ion injection source region, forming a grid electrode on the surface of the grid structure of the pressure welding region of the grid, and simultaneously covering the exposed surface of the second doped ion injection region and the surface of the grid structure of the pressure welding region with the grid electrode.
Optionally, the PN junction diode is a ring edge PN junction diode.
Optionally, the gate structure and the gate structure in the bonding area are formed simultaneously, and in summary, the invention has the following beneficial effects:
the embodiment of the invention provides an ESD integrated SiC power MOSFET device and a preparation method thereof, and a PN junction diode is integrated below a grid electrode bonding area required by the MOSFET device, so that extra chip area is not required, and the integration level of a chip is not influenced. The area of the grid electrode pressure welding area is large, so that the area of the PN junction diode can be large, the PN junction diode surrounds the lower portion of the grid electrode pressure welding area, the area of the grid electrode pressure welding area can be utilized, the area of the PN junction diode is increased, the ESD discharge capacity is improved, and the breakdown voltage of the PN junction diode can be adjusted by adjusting the appearance and the doping concentration of the edge of the PN junction. And the PN junction diode is formed synchronously with the process step of forming the MOSFET device, so that the photoetching mask step is not additionally added, and the manufacturing cost of the chip is not increased.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a circuit configuration diagram showing a SiC power MOSFET device with ESD according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of an ESD integrated SiC power MOSFET device according to an embodiment of the present invention;
fig. 3 to 10 are schematic top-view structural diagrams of gate bonding areas BB' according to different embodiments of the present invention;
fig. 10 to 13 are schematic flow structure diagrams illustrating a method for manufacturing an ESD integrated SiC power MOSFET device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below with reference to specific examples in order to facilitate understanding by those skilled in the art.
An embodiment of the present invention provides an ESD integrated SiC power MOSFET device, as shown in fig. 2, including a silicon carbide semiconductor substrate, where the silicon carbide semiconductor substrate includes a MOSFET cell area AA 'and a gate bonding area BB', and the silicon carbide semiconductor substrate includes a silicon carbide substrate 10 and a silicon carbide epitaxial layer 20 located on a surface of the silicon carbide substrate 10; a drain electrode 70 on the other surface of the silicon carbide semiconductor substrate; the gate structure 30 is positioned on the surface of the silicon carbide epitaxial layer 20 of the MOSFET cellular area AA', and the gate structure 30 comprises a gate dielectric layer 31 and a polysilicon gate 32;
the first doped ion implantation base region 50 is positioned on two sides of the gate structure 30 and positioned in the silicon carbide epitaxial layer 20 of the MOSFET cellular region AA'; a first doped ion re-implantation body region 51 and a second doped ion implantation source region 52 which are positioned in the first doped ion implantation base region 50, and a source electrode 80 which is positioned on the surface of the first doped ion re-implantation body region 51 and the second doped ion implantation source region 52;
a first doped ion implantation region 61 located in the silicon carbide epitaxial layer 20 of the gate bonding area BB' and a second doped ion implantation region 62 located in the first doped ion implantation region 61, the first and second doped ion implantation regions 61 and 62 of the gate bonding area BB' constitute a PN junction diode, the first doped ion implantation region 61 of the gate bonding area BB ' and the first doped ion re-implantation body region 51 of the MOSFET cell area AA ' or the first doped ion implantation base region 50 of the MOSFET cell area AA ' are formed and connected at the same time, the second doped ion implantation region 62 of the gate bonding area BB 'is formed simultaneously with the second doped ion implantation source region 52 of the MOSFET cell area AA', in this embodiment, the first doped ion implantation region 61 of the gate bonding area BB 'and the first doped ion implantation base region 50 of the MOSFET cell area AA' are formed and connected at the same time;
a bonding area gate structure 40 positioned on the surface of the silicon carbide epitaxial layer 20 of the gate bonding area BB' and a gate electrode 90 positioned on the surface of the bonding area gate structure 40, wherein the bonding area gate structure 40 comprises a gate dielectric layer 41 and a polysilicon gate 42; the gate structure 40 of the bonding area is connected to the gate structure 30, the gate structure 40 of the bonding area has an opening 45 therein to expose the surface of the second doped ion implantation area 62, and the gate electrode 90 covers the surface of the second doped ion implantation area 62 and the surface of the gate structure 40 of the bonding area.
Specifically, the SiC power MOSFET device of the embodiment of the invention is an ESD integrated SiC power MOSFET device, and a PN junction diode is connected in parallel between a gate and a source of the MOSFET device. In this embodiment, the PN junction diode is a first doped ion implantation region 61 and a second doped ion implantation region 62 of the gate bonding region BB'. The second doped ion implantation region 62 serves as a cathode of the diode, and the first doped ion implantation region 61 serves as an anode of the diode. And because a PN junction diode is connected in parallel between the grid and the source of the MOSFET device, the first doped ion implantation region 61 located in the grid bonding region BB 'is connected with the first doped ion implantation base region 50 located in the MOSFET cellular region AA' to realize electrical connection. And since the bonding pad gate structure 40 is itself connected to the gate structure 30, the second doped ion implantation region 62 can be electrically connected to the polysilicon gate of the gate structure 30.
Because the PN junction diode is integrated in the grid electrode bonding area, extra chip area is not needed, and the integration level of the chip is not influenced. And the area of the grid electrode pressure welding area is larger, so that the area of the PN junction diode can also be larger, the PN junction diode surrounds the lower part of the grid electrode pressure welding area, and the area of the grid electrode pressure welding area can be utilized to increase the area of the PN junction diode and improve the ESD discharge capacity.
And the PN junction diode is formed synchronously with the process step of forming the MOSFET device, so that the photoetching mask step is not additionally added, and the manufacturing cost of the chip is not increased.
In this embodiment, the first doped ions are P-type doped ions, and the second doped ions are N-type doped ions, that is, the first doped ion implantation base region is a P-type implantation base region, the first doped ion implantation body region 50 is a P-type implantation body region, and the first doped ion implantation region 61 is a P-type implantation region; the second doped ion implantation source region 62 is an N-type implantation source region, and the second doped ion implantation region 62 is an N-type implantation region.
In other embodiments, the first doping ions may also be N-type doping ions, and the second doping ions are P-type doping ions.
Referring to fig. 3, a schematic top view of a gate bonding area BB' according to a first embodiment of the present invention is shown (for convenience of understanding, the gate electrode and the gate structure of the bonding area are not shown), the first doped ion implantation area 61 is disposed at the periphery of the second doped ion implantation area 62, the second doped ion implantation area 62 is square, the opening of the gate structure of the bonding area is disposed at a corresponding position (not shown) of the second doped ion implantation area 62, a ring-shaped edge diode is formed between the first doped ion implantation area 61 and the second doped ion implantation area 62, the edges of the first doped ion implantation area 61 and the second doped ion implantation area 62 have 4 sharp peak angles, and each sharp peak angle is 90 degrees. The breakdown voltage of the PN junction diode in the silicon carbide epitaxial layer is high, the breakdown voltage of the PN junction diode is adjusted by adjusting the appearance and doping concentration of the edge of the PN junction, the injection concentration of the first doping ion injection region 61 and the second doping ion injection region 62 is determined by MOSFET cells, so that the shape of the edge of the annular edge diode can be changed by setting the sharp peak angle, the PN junction is broken down in advance by introducing the sharp peak angle, the breakdown voltage can be controlled by the angle of the sharp peak angle and the number of the sharp peak angles, the sharp peak angle is 0-180 degrees, the angle can be 60 degrees, 90 degrees, 120 degrees and the like, and the breakdown voltage of the PN junction diode is larger than the normal grid conduction voltage but smaller than the grid breakdown voltage. Since the positions of the PN junction diode breakdown in this embodiment are mainly distributed at the annular edge, particularly the peak angle position, where the first doped ion implantation region 61 and the second doped ion implantation region 62 contact in the device top view state, the diode formed between the first doped ion implantation region 61 and the second doped ion implantation region 62 in this embodiment is called an annular edge diode.
In this embodiment, the depth of the first doped ion implantation region 61 is greater than the depth of the second doped ion implantation region 62, and in other embodiments, the depth of the first doped ion implantation region 61 may also be less than or equal to the depth of the second doped ion implantation region 62.
Referring to fig. 4, which is a schematic top view of a gate bonding area BB' according to a second embodiment of the present invention, the first doped ion implantation area 61 is disposed at the periphery of the second doped ion implantation area 62, and the second doped ion implantation area 62 surrounds a portion of the first doped ion implantation area 61, so that the second doped ion implantation area 62 forms a circular square shape, an opening of the gate structure of the bonding area is disposed at a corresponding position (not shown) of the circular square of the second doped ion implantation area 62, so as to form two circular edge diodes, edges of the first doped ion implantation area 61 and the second doped ion implantation area 62 have 8 peak angles, and each peak angle is 90 degrees.
Referring to fig. 5, which is a schematic top view of a gate bonding area BB' according to a third embodiment of the present invention, the first doped ion implantation area 61 is disposed at the periphery of the second doped ion implantation area 62, and the second doped ion implantation area 62 surrounds a portion of the second doped ion implantation area 62, such that the second doped ion implantation area 62 forms an annular square shape, the peripheral edge of the second doped ion implantation area 62 is zigzag, and an angle of each zigzag is 60 degrees. The breakdown voltage of the ring edge diode can be reduced because the angle of each sawtooth is smaller, the PN junction is easy to break down in advance, and the number of the sawteeth is increased.
Referring to fig. 6, which is a schematic top view of a gate bonding area BB' according to a fourth embodiment of the present invention, the second doped ion implantation area 62 is two rectangular areas, the first doped ion implantation area 61 is disposed at the periphery of the second doped ion implantation area 62 to form a plurality of ring-shaped edge diodes, each ring-shaped edge diode has four sharp peak angles, and each sharp peak angle is 90 degrees.
Referring to fig. 7, which is a schematic top view of a gate bonding area BB' according to a fifth embodiment of the present invention, the second doped ion implantation area 62 is two rectangular areas, the first doped ion implantation area 61 is disposed at the periphery of the second doped ion implantation area 62 to form a plurality of ring-shaped edge diodes, the edge of each rectangular area is saw-toothed, and the angle of each saw-toothed is 60 degrees.
Referring to fig. 8, which is a schematic top view of a gate bonding area BB' according to a sixth embodiment of the present invention, the second doped ion implantation area 62 is a plurality of small square areas, the first doped ion implantation area 61 is disposed at the periphery of the second doped ion implantation area 62 to form a plurality of ring-shaped edge diodes, each diode has four sharp peak angles, and each sharp peak angle is 90 degrees.
Referring to fig. 9, which is a schematic top view of a gate bonding area BB' according to a seventh embodiment of the present invention, the second doped ion implantation area 62 is a plurality of small square areas, the first doped ion implantation area 61 is disposed at the periphery of the second doped ion implantation area 62 to form a plurality of diodes, the edge of each small square area has a saw-tooth shape, and the angle of each saw-tooth is 60 degrees.
The embodiment of the invention also provides a preparation method of the ESD integrated SiC power MOSFET device, which comprises the following steps:
referring to fig. 10, a silicon carbide semiconductor substrate is provided, the silicon carbide semiconductor substrate includes a MOSFET cell area AA 'and a gate bonding area BB', the silicon carbide semiconductor substrate includes a silicon carbide substrate 10 and a silicon carbide epitaxial layer 20 on a surface of the silicon carbide substrate 10, and a drain electrode 70 is formed on another surface of the silicon carbide semiconductor substrate. In other embodiments, the front device may be formed first, and then the drain electrode may be formed on the other surface of the silicon carbide semiconductor substrate.
Referring to fig. 11, a first doped ion implantation base region 50 is formed in the silicon carbide epitaxial layer 20 of the MOSFET cell region AA 'and at positions on both sides of the gate structure, and a first doped ion implantation region 61 is formed in the silicon carbide epitaxial layer 10 of the gate bonding area BB'. In this embodiment, the first doped ion implantation base region 50 and the first doped ion implantation region 61 are both P-type implantation regions and are formed simultaneously. In other embodiments, the first doped ion implantation region is formed simultaneously with a subsequent first doped ion re-implantation body region.
Referring to fig. 12, a first doped ion heavily-implanted body 51 is formed in the first doped ion implanted base region 50; forming a second doped ion implantation source region 52 in the first doped ion implantation base region 50 at the two sides of the gate structure, forming a second doped ion implantation region 62 in the first doped ion implantation region 61 corresponding to the opening position of the gate structure in the bonding region, so that the second doped ion implantation region 62 is surrounded by the first doped ion implantation region 61 to form a ring-shaped edge diode, wherein the second doped ion implantation region 62 of the gate bonding region BB 'and the second doped ion implantation source region 52 of the MOSFET cell region AA' are formed simultaneously, and the edges of the first doped ion implantation region 61 and the second doped ion implantation region 62 have a plurality of sharp peak angles.
The first doped ion implantation area and the second doped ion implantation area form a PN junction diode, and the PN junction diode is formed synchronously with the process step of forming the MOSFET device, so that the step of photoetching a mask is not additionally added, and the manufacturing cost of a chip is not increased.
In this embodiment, since the first doping ions are P-type ions and the second doping ions are N-type ions, after the P-type implantation base region and the P-type implantation region 61 are formed, the P + implantation body region 51 is formed by re-implanting the P-type ions through the first mask layer, the N-type implantation source region 52 and the N-type implantation region 62 are formed by implanting the N-type ions through the second mask layer, and then the gate structure and the bonding pad gate structure are formed on the surface of the silicon carbide epitaxial layer.
In other embodiments, after the P-type implanted base region, the P-type implanted region, and the P + implanted body region are formed, a gate structure and a bonding pad gate structure are formed on the surface of the silicon carbide epitaxial layer, the bonding pad gate structure has an opening, and self-aligned ion implantation is performed by using the opening of the bonding pad gate structure and the gate structure to form an N-type implanted source region and an N-type implanted region.
In this embodiment, the peak angle is 60 degrees or 90 degrees, and the ion implantation may be performed through a mask layer.
Referring to fig. 13, a gate structure 30 is formed on the surface of the silicon carbide epitaxial layer 10 in the MOSFET cell area AA ', a bonding area gate structure 40 is formed on the surface of the silicon carbide epitaxial layer 10 in the gate bonding area BB', the gate structure 30 and the bonding area gate structure 40 are formed and connected at the same time, and the bonding area gate structure 40 has an opening 45 exposing the silicon carbide epitaxial layer 10 at the position of the first doped ion implantation area at the bottom. And forming a source electrode 80 on the surfaces of the first doped ion re-implantation body region 51 and the second doped ion implantation source region 52, forming a gate electrode 90 on the surface of the gate structure 40 of the bonding region of the gate bonding region BB', and covering the surface of the second doped ion implantation region 52 exposed by the opening and the surface of the gate structure 40 of the bonding region when the gate electrode 90 is covered.
Finally, it is to be noted that any modifications or equivalent substitutions of some or all of the features may be made by means of the structure of the device according to the invention and the technical solutions of the examples described, without departing from the corresponding technical solutions of the invention, and the obtained essence falls within the scope of the structure of the device according to the invention and the claims of the embodiments described.
Claims (9)
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