CN112951851B - Display substrate and display device - Google Patents
Display substrate and display device Download PDFInfo
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- CN112951851B CN112951851B CN202110230986.1A CN202110230986A CN112951851B CN 112951851 B CN112951851 B CN 112951851B CN 202110230986 A CN202110230986 A CN 202110230986A CN 112951851 B CN112951851 B CN 112951851B
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- 239000000758 substrate Substances 0.000 title claims abstract description 125
- 239000002184 metal Substances 0.000 claims abstract description 93
- 239000004065 semiconductor Substances 0.000 claims abstract description 75
- 230000000903 blocking effect Effects 0.000 claims description 14
- 239000010409 thin film Substances 0.000 claims description 11
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 230000008439 repair process Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 160
- 238000000034 method Methods 0.000 description 17
- 238000010586 diagram Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides a display substrate and a display device. The display substrate comprises a substrate, a source-drain metal layer, a semiconductor layer and a gate metal layer, wherein the source-drain metal layer is formed on the substrate, the source-drain metal layer comprises a data line pattern, the data line pattern is connected with the semiconductor layer, the semiconductor layer is located at one side, far away from the substrate, of the source-drain metal layer, and the gate metal layer is located at one side, far away from the substrate, of the semiconductor layer. According to the embodiment of the invention, the semiconductor layer is arranged on one side of the source-drain metal layer away from the substrate, the gate metal layer is arranged on one side of the semiconductor layer away from the substrate, that is, the source-drain metal layer is closer to the substrate, in the manufacturing process, firstly the source-drain metal layer is manufactured, then the semiconductor layer is manufactured, and finally the gate metal layer is manufactured, the structure between the source-drain metal layer and the substrate is relatively less, if the source-drain metal layer remains, the influence on other structures caused by the repair of the source-drain metal layer is relatively less, and the repairability of the display substrate is improved, so that the yield of products is improved.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display substrate and a display device.
Background
The display substrate generally includes a thin film transistor on a substrate, and generally, the thin film transistor includes a semiconductor layer, a gate insulating layer, a gate layer, and a source drain metal layer disposed in a direction away from the substrate, wherein the source drain metal layer includes a data line, and the data line is generally made of a metal material that is easily conductive to transmit a data signal. However, the metal material may have some residues during the etching process, and these residues may bring adverse effects such as structural short circuit. The short circuit can be repaired by a repairing method, however, the repairing operation on the overlapped area of the data line and the gate layer can cause damage to the gate layer, so that the product cannot be repaired, and the etching residues of the source and drain metal layers can cause the reduction of the yield of the display substrate.
Disclosure of Invention
The embodiment of the invention provides a display substrate and a display device, which are used for solving the problem that the etching residues of source and drain metal layers may cause the reduction of the yield of the display substrate.
In a first aspect, an embodiment of the present invention provides a display substrate, including a substrate, a source drain metal layer, a semiconductor layer, and a gate metal layer, where the source drain metal layer is formed on the substrate, the source drain metal layer includes a data line pattern, the data line pattern is connected to the semiconductor layer, the semiconductor layer is located at a side of the source drain metal layer away from the substrate, and the gate metal layer is located at a side of the semiconductor layer away from the substrate.
Optionally, the source-drain metal layer is in direct contact with the substrate.
Optionally, the gate metal layer includes a gate signal line, where an overlapping area exists between an orthographic projection of the gate signal line on the substrate and an orthographic projection of the semiconductor layer on the substrate, and the source drain metal layer further includes a light blocking pattern, where the light blocking pattern is located between the semiconductor layer and the substrate, where the orthographic projection of the light blocking pattern on the substrate covers the overlapping area, and where the light blocking pattern is separated from the data line pattern.
Optionally, the display substrate includes a first insulating layer and a second insulating layer, the first insulating layer is located between the semiconductor layer and the source drain metal layer, the second insulating layer is located between the semiconductor layer and the gate metal layer, the gate metal layer includes a first conductive structure, and the semiconductor layer is connected with the source drain metal layer through the first conductive structure.
Optionally, the display substrate includes a first via hole, the first via hole penetrates through the first insulating layer, the semiconductor layer and the second insulating layer, the first conductive structure is connected with a surface of a side, far away from the substrate, of the source drain metal layer through the first via hole, the semiconductor layer includes a first conductive pattern and a second conductive pattern, the semiconductor layer further includes an active layer of a thin film transistor, the first conductive pattern, the active layer and the second conductive pattern are sequentially connected, and the first conductive structure is connected with the first conductive pattern.
Optionally, a front projection of a portion of the first conductive structure on a side of the semiconductor layer away from the substrate and a front projection of the first via on the substrate are overlapped, and the first conductive structure is in contact with a surface of the side of the semiconductor layer away from the substrate.
Optionally, the display substrate further includes a common electrode layer, a third insulating layer, and a pixel electrode layer, which are sequentially stacked along a direction away from the substrate, and the gate metal layer further includes a second conductive structure, where the second conductive structure is connected to the pixel electrode layer, and the second conductive structure is connected to the second conductive pattern.
Optionally, the display substrate includes a second via hole, where the second via hole penetrates through the semiconductor layer and the second insulating layer, the second conductive structure is connected to the pixel electrode layer through the second via hole, and the second conductive structure is connected to the semiconductor layer through the second via hole.
Optionally, the source-drain metal layer further includes a dummy electrode pattern, the dummy electrode pattern is connected to the second conductive structure, orthographic projection of the dummy electrode pattern on the substrate covers orthographic projection of a surface of the second conductive structure, which is close to the dummy electrode pattern, on the substrate, and the dummy electrode pattern is separated from the data line pattern.
In a second aspect, an embodiment of the present invention provides a display module, including the display substrate according to any one of the first aspects.
According to the embodiment of the invention, the semiconductor layer is arranged on one side of the source-drain metal layer away from the substrate, and the gate metal layer is arranged on one side of the semiconductor layer away from the substrate, namely, the source-drain metal layer is closer to the substrate, so that in the manufacturing process, firstly, the source-drain metal layer is manufactured, then the semiconductor layer is manufactured, and finally, the gate metal layer is manufactured, the structure between the source-drain metal layer and the substrate is relatively less, if the source-drain metal layer remains, the influence on other structures caused by the repair of the source-drain metal layer is relatively less, and the repairability of the display substrate is improved, so that the yield of products is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a stacked layer of a source/drain metal layer, a semiconductor layer and a gate metal layer according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a structure of a source/drain metal layer according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a semiconductor layer according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a gate metal layer according to an embodiment of the present invention;
FIG. 5 is a schematic illustration of an intermediate process of a display substrate according to an embodiment of the invention;
FIG. 6 is a schematic illustration of yet another intermediate process of the display substrate according to an embodiment of the invention;
FIG. 7 is a schematic illustration of yet another intermediate process of the display substrate according to an embodiment of the invention;
FIG. 8 is a schematic illustration of yet another intermediate process of a display substrate according to an embodiment of the invention;
FIG. 9 is a schematic illustration of yet another intermediate process of the display substrate according to an embodiment of the invention;
FIG. 10 is a schematic illustration of an intermediate process of a display substrate according to another embodiment of the invention;
FIG. 11 is a schematic illustration of yet another intermediate process of a display substrate according to another embodiment of the invention;
FIG. 12 is a schematic illustration of yet another intermediate process of a display substrate according to another embodiment of the invention;
FIG. 13 is a schematic illustration of yet another intermediate process of a display substrate according to another embodiment of the invention;
FIG. 14 is a schematic illustration of yet another intermediate process of a display substrate according to another embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a display substrate.
As shown in fig. 1, 9 and 14, the display substrate includes a substrate 10, a source drain metal layer 20, a semiconductor layer 30 and a gate metal layer 40, wherein the source drain metal layer 20 is formed on the substrate 10.
As shown in fig. 2, the source drain metal layer 20 includes a data line pattern 201, and the data line pattern 201 is connected to the semiconductor layer 30.
As shown in fig. 9 and 14, the semiconductor layer 30 is located on a side of the source drain metal layer 20 away from the substrate 10, and the gate metal layer 40 is located on a side of the semiconductor layer 30 away from the substrate 10.
In the embodiment of the invention, the semiconductor layer 30 is arranged on the side of the source-drain metal layer 20 away from the substrate 10, and the gate metal layer 40 is arranged on the side of the semiconductor layer 30 away from the substrate 10, that is, the source-drain metal layer 20 is closer to the substrate 10, so that in the manufacturing process, the source-drain metal layer 20 is firstly manufactured on the substrate 10, then the semiconductor layer 30 is manufactured, and finally the gate metal layer 40 is manufactured, the structure between the source-drain metal layer 20 and the substrate 10 is relatively less, if the source-drain metal layer 20 remains, the influence on other structures caused by the repair of the source-drain metal layer 20 is relatively less, and the repairability of the display substrate is improved, so that the yield of products is improved.
In some embodiments, the source-drain metal layer 20 is in direct contact with the substrate 10, that is, the source-drain metal layer 20 is directly formed on the substrate 10, so that if the etching residue of the source-drain metal layer 20 needs to be repaired on the substrate 10, the repair process does not affect or damage other structures, so that the repairability of the product is significantly improved, and the yield of the product is improved.
In some of these embodiments, as shown in fig. 4, the gate metal layer 40 includes a gate signal line 401, where there is an overlapping region between the front projection of the gate signal line 401 on the substrate 10 and the front projection of the semiconductor layer 30 on the substrate 10, and as shown in fig. 2, the source drain metal layer 20 further includes a light blocking pattern 202, the light blocking pattern 202 is located between the semiconductor layer 30 and the substrate 10, the front projection of the light blocking pattern 202 on the substrate 10 covers the overlapping region, and the light blocking pattern 202 is separated from the data line pattern 201.
In this embodiment, there is an overlapping area between the front projection of the gate signal line 401 on the substrate 10 and the front projection of the semiconductor layer 30 on the substrate 10, and as shown in fig. 3, the semiconductor layer 30 corresponding to the overlapping area may be understood as the active layer 301 of the thin film transistor, more specifically, may be a channel region of the active layer 301, and the source region and the drain region of the active layer 301 may be located outside the overlapping area. Other portions of semiconductor layer 30 may be understood to primarily perform conductive functions. The gate signal line 401 corresponding to the overlapping region may be understood as a gate electrode of the thin film transistor, and other portions of the gate signal line 401 may be understood as mainly realizing signal transmission.
The light blocking pattern 202 is further fabricated in this embodiment to block light, so as to prevent light from directly irradiating the active layer 301 of the thin film transistor, which is helpful for improving the reliability of the thin film transistor. In this embodiment, the light blocking pattern 202 is located on the source/drain metal layer 20, that is, a separate step is not required to manufacture the light blocking layer, which helps to save the process and the manufacturing cost.
In some of these embodiments, the display substrate includes a first insulating layer 51 and a second insulating layer 52, the first insulating layer 51 is located between the semiconductor layer 30 and the source drain metal layer 20, the second insulating layer 52 is located between the semiconductor layer 30 and the gate metal layer 40, and as shown in fig. 4, the gate metal layer 40 includes a first conductive structure 402, and the semiconductor layer 30 is connected to the source drain metal layer 20 through the first conductive structure 402.
In the present embodiment, the first insulating layer 51 is used to realize insulation between the semiconductor layer 30 and the source-drain metal layer 20, and the second insulating layer 52 is used to realize insulation between the semiconductor layer 30 and the gate signal line 401.
In some embodiments, the display substrate includes a first via penetrating the first insulating layer 51, the semiconductor layer 30, and the second insulating layer 52, and the first conductive structure 402 is connected to a surface of the source drain metal layer 20, which is far from the substrate 10, through the first via.
In this embodiment, as shown in fig. 3, the semiconductor layer 30 further includes a first conductive pattern 302 and a second conductive pattern 303, the first conductive pattern 302, the active layer 301, and the second conductive pattern 303 are sequentially connected, and the first conductive structure 402 is connected to the first conductive pattern 302, thereby realizing connection of the data line and the thin film transistor.
In some of these embodiments, the orthographic projection of the portion of the first conductive structure 402 on the substrate 10 at the side of the semiconductor layer 30 remote from the substrate 10 and the orthographic projection of the covered first via on the substrate 10, and the first conductive structure 402 is in contact with the surface of the side of the semiconductor layer 30 remote from the substrate 10.
In this embodiment, a portion of the surface of the first conductive structure 402 contacts the upper surface of the semiconductor layer 30, which helps to increase the contact area between the first conductive structure 402 and the semiconductor layer 30 and improve the signal transmission effect.
In some of these embodiments, the display substrate further includes a common electrode layer 54, a third insulating layer, and a pixel electrode layer 60 sequentially stacked in a direction away from the substrate 10, and as shown in fig. 4, the gate metal layer 40 further includes a second conductive structure 403, the second conductive structure 403 being connected to the pixel electrode layer 60, and the second conductive structure 403 being connected to the second conductive pattern 303.
In this embodiment, the pixel electrode layer 60 is connected to the semiconductor layer 30 through the second conductive structure 403 to transfer the data signal transmitted by the data line to the pixel electrode through the thin film transistor.
In some embodiments, the display substrate includes a second via penetrating the semiconductor layer 30 and the second insulating layer 52, the second conductive structure 403 is connected to the pixel electrode layer 60 through the second via, and the second conductive structure 403 is connected to the semiconductor layer 30 through the second via.
Similar to the first via hole, in this embodiment, the second via hole is used to implement connection between the second conductive structure 403 and the semiconductor layer 30 and the pixel electrode, so as to improve uniformity of different positions of the display substrate, and simplify process steps, in this embodiment, the first via hole and the second via hole are patterned by using substantially the same process, and accordingly, thicknesses of the first conductive structure 402 and the second conductive structure 403 in a direction perpendicular to the substrate 10 are substantially equal, where substantially equal refers to that dimensions thereof are equal under a condition that a process error is ignored. By providing the first conductive structure 402 and the second conductive structure 403, connection between the data line and the semiconductor layer 30 and connection between the semiconductor and the pixel electrode can be achieved.
In some embodiments, as shown in fig. 2, the source-drain metal layer 20 further includes a dummy electrode pattern 203, where the dummy electrode pattern 203 is connected to the second conductive structure 403, and an orthographic projection of the dummy electrode pattern 203 on the substrate 10 covers an orthographic projection of a surface of the second conductive structure 403, which is adjacent to the dummy electrode pattern 203, on the substrate 10, and the dummy electrode pattern 203 is separated from the data line pattern 201.
In this embodiment, the dummy electrode pattern 203 is mainly used to support the second conductive structure 403, and it should be understood that the thin film transistor is connected to the pixel electrode layer 60 through the second conductive pattern 303 and the second conductive structure 403 in turn, so that the second conductive structure 403 is not used to implement a conductive function, but is mainly used to support the second conductive structure 403, and by setting the second conductive structure 403, the second via hole can be prevented from being etched, so that the depth of the second via hole is substantially consistent with that of the first via hole, and further, the distances between the first conductive structure 402 and the second conductive structure 403 and the substrate 10 are substantially consistent, which is helpful to improve the uniformity of the structure thickness at different positions of the display substrate.
As shown in fig. 5 and 10, in this embodiment, first, a source-drain metal layer 20 is fabricated on a substrate 10 by a patterning process; as shown in fig. 6 and 11, next, a first insulating layer 51 is formed to cover the source-drain metal layer 20; as shown in fig. 7 and 12, next, the semiconductor layer 30 and the second insulating layer 52 are sequentially formed, and the first via hole and the second via hole are opened at specified positions; as shown in fig. 8 and 13, a gate metal layer 40 is next fabricated; as shown in fig. 9 and 14, subsequent structures such as the flat layer 53, the common electrode layer 54, the protective layer 55, and the pixel electrode layer 60 are next fabricated, and thus, fabrication of the display substrate is completed.
The embodiment of the invention provides a display module, which comprises the display substrate.
Because the technical solution of the present embodiment includes all the technical solutions of the embodiments of the display substrate, at least all the technical effects can be achieved, and the description thereof is omitted herein.
The foregoing is merely illustrative embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present invention, and the invention should be covered. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (7)
1. The display substrate is characterized by comprising a substrate, a source-drain metal layer, a semiconductor layer and a gate metal layer, wherein the source-drain metal layer is formed on the substrate, the source-drain metal layer comprises a data line pattern, the data line pattern is connected with the semiconductor layer, the semiconductor layer is positioned on one side of the source-drain metal layer away from the substrate, and the gate metal layer is positioned on one side of the semiconductor layer away from the substrate;
The display substrate comprises a first insulating layer and a second insulating layer, the first insulating layer is positioned between the semiconductor layer and the source-drain metal layer, the second insulating layer is positioned between the semiconductor layer and the gate metal layer, the gate metal layer comprises a first conductive structure, and the semiconductor layer is connected with the source-drain metal layer through the first conductive structure;
The display substrate comprises a first via hole, the first via hole penetrates through the first insulating layer, the semiconductor layer and the second insulating layer, the first conductive structure is connected with one side surface of the source drain metal layer, far away from the substrate, through the first via hole, the semiconductor layer comprises a first conductive pattern and a second conductive pattern, the semiconductor layer further comprises an active layer of a thin film transistor, the first conductive pattern, the active layer and the second conductive pattern are sequentially connected, and the first conductive structure is connected with the first conductive pattern;
The front projection of the part of the first conductive structure, which is positioned on the side, far away from the substrate, of the semiconductor layer on the substrate is in contact with the front projection of the part of the first conductive structure, which is covered by the first via hole, on the substrate, and the surface of the first conductive structure, which is positioned on the side, far away from the substrate, of the semiconductor layer is in contact with the first conductive structure, and the first conductive structure is separated from the gate signal line.
2. The display substrate of claim 1, wherein the source drain metal layer is in direct contact with the substrate.
3. The display substrate according to claim 1, wherein the gate metal layer includes a gate signal line, an overlapping region exists between a front projection of the gate signal line on the substrate and a front projection of the semiconductor layer on the substrate, the source drain metal layer further includes a light blocking pattern between the semiconductor layer and the substrate, the front projection of the light blocking pattern on the substrate covers the overlapping region, and the light blocking pattern is separated from the data line pattern.
4. The display substrate according to claim 1, further comprising a common electrode layer, a third insulating layer, and a pixel electrode layer which are sequentially stacked in a direction away from the substrate, wherein the gate metal layer further comprises a second conductive structure connected to the pixel electrode layer, and wherein the second conductive structure is connected to the second conductive pattern.
5. The display substrate according to claim 4, wherein the display substrate comprises a second via hole penetrating the semiconductor layer and the second insulating layer, the first conductive structure is connected to the pixel electrode layer through the second via hole, and the first conductive structure is connected to the semiconductor layer through the second via hole.
6. The display substrate according to claim 4 or 5, wherein the source-drain metal layer further comprises a dummy electrode pattern connected to the second conductive structure, an orthographic projection of the dummy electrode pattern on the substrate covers an orthographic projection of a side surface of the second conductive structure adjacent to the dummy electrode pattern on the substrate, and the dummy electrode pattern is separated from the data line pattern.
7. A display module comprising the display substrate of any one of claims 1 to 6.
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| CN202110230986.1A CN112951851B (en) | 2021-03-02 | 2021-03-02 | Display substrate and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110230986.1A CN112951851B (en) | 2021-03-02 | 2021-03-02 | Display substrate and display device |
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| CN112951851A CN112951851A (en) | 2021-06-11 |
| CN112951851B true CN112951851B (en) | 2024-05-17 |
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| JPH08181325A (en) * | 1994-12-27 | 1996-07-12 | Sharp Corp | Manufacture of semiconductor element and manufacture of substrate for display device |
| CN1828963A (en) * | 2005-01-15 | 2006-09-06 | 三星Sdi株式会社 | A thin film transistor, a method for preparing the same and a flat panel display employing the same |
| CN105206570A (en) * | 2015-10-27 | 2015-12-30 | 深圳市华星光电技术有限公司 | Display panel and production method thereof |
| CN106981478A (en) * | 2017-04-07 | 2017-07-25 | 京东方科技集团股份有限公司 | Top gate type thin film transistor and preparation method thereof, array base palte, display panel |
| CN111312731A (en) * | 2020-02-28 | 2020-06-19 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105702744B (en) * | 2016-04-05 | 2020-07-28 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
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- 2021-03-02 CN CN202110230986.1A patent/CN112951851B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08181325A (en) * | 1994-12-27 | 1996-07-12 | Sharp Corp | Manufacture of semiconductor element and manufacture of substrate for display device |
| CN1828963A (en) * | 2005-01-15 | 2006-09-06 | 三星Sdi株式会社 | A thin film transistor, a method for preparing the same and a flat panel display employing the same |
| CN105206570A (en) * | 2015-10-27 | 2015-12-30 | 深圳市华星光电技术有限公司 | Display panel and production method thereof |
| CN106981478A (en) * | 2017-04-07 | 2017-07-25 | 京东方科技集团股份有限公司 | Top gate type thin film transistor and preparation method thereof, array base palte, display panel |
| CN111312731A (en) * | 2020-02-28 | 2020-06-19 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
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