CN112951843A - Electronic device and method for manufacturing the same - Google Patents

Electronic device and method for manufacturing the same Download PDF

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Publication number
CN112951843A
CN112951843A CN202110075162.1A CN202110075162A CN112951843A CN 112951843 A CN112951843 A CN 112951843A CN 202110075162 A CN202110075162 A CN 202110075162A CN 112951843 A CN112951843 A CN 112951843A
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region
drain
source
channel
electrode
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黄景亮
叶家宏
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AU Optronics Corp
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AU Optronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention provides an electronic device and a manufacturing method thereof. The electronic device comprises a substrate, a first active element, a second active element, a protective layer and a control electrode. The first active device and the second active device are located on the substrate. The first active element comprises a first source region, a first channel region, a first drain region, a first gate, a first source and a first drain. The second active element comprises a second source region, a second channel region, a second drain region, a second gate, a second source and a second drain. The material of the first channel region is different from the material of the second channel region. The materials of the first source region, the first drain region, the second source region and the second drain region are the same. The control electrode is electrically connected with the second drain electrode.

Description

Electronic device and method for manufacturing the same
The application is a divisional application.
Application date of the original application: 2019.04.01 application No.: 201910257765.6
The invention name is as follows: electronic device and method for manufacturing the same
Technical Field
The present invention relates to an electronic device, and more particularly, to an electronic device including a first active device and a second active device and a method of manufacturing the same.
Background
Electronic devices often include a plurality of active devices, and in order to meet various functional requirements, the electronic devices may include more than one active device. For example, in a display device, in order to obtain better performance, the active devices in the driving circuit may have different impedances than the active devices in the pixels.
In the prior art, active elements with different impedances can be obtained by adjusting the length of the channel region. However, it is difficult to cope with different functional requirements by merely adjusting the length of the channel region of the active device. In order to form active devices with large performance differences, many additional process steps are required, which results in a significant increase in the manufacturing cost of the electronic device.
Disclosure of Invention
The invention provides an electronic device which has the advantages of low manufacturing cost and easiness in manufacturing.
The invention provides a manufacturing method of an electronic device, which has the advantages of low manufacturing cost and easy manufacturing.
At least one embodiment of the invention provides an electronic device including a substrate, a first active device, a second active device, a passivation layer, and a control electrode. The first active device and the second active device are located on the substrate. The first active element comprises a first source region, a first channel region, a first drain region, a first gate, a first source and a first drain. The first gate is arranged corresponding to the first channel region, and a gate insulating layer is arranged between the first gate and the first channel region. The first source electrode and the first drain electrode correspond to the first source region and the first drain region respectively and are electrically connected to the first source region and the first drain region. The second active element comprises a second source region, a second channel region, a second drain region, a second gate, a second source and a second drain. The material of the first channel region is different from the material of the second channel region. The materials of the first source region, the first drain region, the second source region and the second drain region are the same. The second grid is arranged corresponding to the second channel region, and a grid insulating layer is clamped between the second grid and the second channel region. The second source and the second drain correspond to the second source region and the second drain region, respectively, and are electrically connected to the second source region and the second drain region. The protective layer is located on the first active device and the second active device. The control electrode is electrically connected with the second drain electrode.
At least one embodiment of the present invention provides a method for manufacturing an electronic device, including: providing a substrate; forming a first source region, a first channel region, a first drain region, a second source region, a second channel region and a second drain region on the substrate, wherein the material of the first channel region is different from that of the second channel region, and the materials of the first source region, the first drain region, the second source region and the second drain region are the same; forming a gate insulating layer on the substrate; forming a first grid and a second grid on the substrate; forming a first source electrode, a first drain electrode, a second source electrode and a second drain electrode on the substrate, wherein the first source electrode and the first drain electrode correspond to and are electrically connected to the first source electrode region and the first drain electrode region respectively, and the second source electrode and the second drain electrode correspond to and are electrically connected to the second source electrode region and the second drain electrode region respectively; forming a protective layer on the first source electrode, the first drain electrode, the second source electrode and the second drain electrode; and forming a control electrode to be electrically connected with the second drain electrode.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to fig. 1E are schematic cross-sectional views illustrating a method for manufacturing an electronic device according to an embodiment of the invention.
Fig. 2 is a schematic top view of an electronic device according to an embodiment of the invention.
Fig. 3 is a schematic partial circuit diagram of an electronic device according to an embodiment of the invention.
Fig. 4A-4C are schematic cross-sectional views of a treatment process according to an embodiment of the invention.
Fig. 5A-5C are schematic cross-sectional views of a treatment process according to an embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of an electronic device according to an embodiment of the invention.
Fig. 7A to 7F are schematic cross-sectional views illustrating a method for manufacturing an electronic device according to an embodiment of the invention.
Fig. 8 is a schematic cross-sectional view of an electronic device according to an embodiment of the invention.
Wherein, the reference numbers:
10. 20, 30, 40: an electronic device AA: display area
BA: non-display area CH: channel region
CH 1: first channel region CH 2: second channel region
CL: signal line D1: a first drain electrode
D2: the second drain electrode DA: drain region
DA 1: first drain region DA 2: second drain region
DL: a data line E: control electrode
G1: first gate G2: second grid
GI: gate insulating layers H1, H2, H3, H4, O: opening of the container
I0, I1: an insulating layer M: lightly doped region
PL: protective layer S1: a first source electrode
S2: second source SA: source region
SA 1: first source region SA 2: second source region
SB: substrate SH: shielding layer
SH': patterning the shield layer SL: scanning line
SM 1: first active layer SM 2: a second active layer
SR: drive circuit T1: a first active element
T2: second active element t1, t 2: thickness of
y: direction of rotation
Detailed Description
Fig. 1A to fig. 1E are schematic cross-sectional views illustrating a method for manufacturing an electronic device according to an embodiment of the invention.
Referring to fig. 1A, a substrate SB is provided. The first channel region CH1 is formed on the substrate SB.
In the embodiment, the insulating layer I0 may be selectively disposed between the substrate SB and the first channel CH1, but the invention is not limited thereto.
Referring to fig. 1B, a first source region SA1, a first drain region DA1, a second source region SA2, a second channel region CH2 and a second drain region DA2 are formed on a substrate SB. The first channel region CH1 is located between the first source region SA1 and the first drain region DA1, and the second channel region CH2 is located between the second source region SA2 and the second drain region DA 2. The second source region SA2, the second channel region CH2, and the second drain region DA2 are sequentially connected, and the first source region SA1, the first channel region CH1, and the first drain region DA1 are sequentially connected.
In the embodiment, the first channel CH1 is formed on the substrate SB, and then the first source region SA1, the first drain region DA1, the second source region SA2, the second channel region CH2 and the second drain region DA2 are formed on the substrate SB. The material of the first channel region CH1 is different from that of the second channel region CH 2. The materials of the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2 are the same. In the present embodiment, the material of the first channel CH1 includes silicon, such as amorphous silicon, polysilicon, microcrystalline silicon, or single crystal silicon. For example, the material of the first channel CH1 includes polysilicon, and the process for forming the first channel CH1 includes a Low Temperature Polysilicon (LTPS) process. The materials of the second channel region CH2, the first source region SA1, the first drain region DA1, the second source region SA2, and the second drain region DA2 include metal oxides. In the embodiment, the material of the second channel region CH2, the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2 includes indium gallium zinc oxide.
In some embodiments, the method of forming the second channel region CH2, the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2 includes, for example, forming a metal oxide layer, and then patterning the metal oxide layer by acid etching to form the second channel region CH2, the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA 2. The acid etching is, for example, using oxalic acid or other suitable etching solution.
Referring to fig. 1C, the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2 are processed such that the resistances of the first source region SA1 and the first drain region DA1 are smaller than the resistance of the first channel region CH1, and the resistances of the second source region SA2 and the second drain region DA2 are smaller than the resistance of the second channel region CH 2. In the present embodiment, the treatment process includes a plasma treatment process (e.g., a hydrogen plasma treatment process or other plasma treatment processes).
In some embodiments, the process further includes forming a patterned mask layer on the second channel CH2 before the treatment process to prevent the plasma treatment process from directly affecting the resistance of the second channel CH 2. In some embodiments, the plasma treatment process is a hydrogen plasma treatment process, and the hydrogen plasma treatment process is performed on the first channel region CH1 while the plasma treatment process is performed on the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2, so as to repair the silicon bonding in the first channel region CH1, but the invention is not limited thereto. The patterned shielding layer may also be formed on the first channel CH 1.
Referring to fig. 1D, a gate insulating layer GI is formed on a substrate SB. In the present embodiment, the gate insulating layer GI is formed on the first source region SA1, the first drain region DA1, the second source region SA2, the second drain region DA2, the first channel region CH1 and the second channel region CH 2.
A first gate G1 and a second gate G2 are formed on the substrate SB. In the present embodiment, the first gate G1 and the second gate G2 are formed on the gate insulating layer GI. The first gate G1 is disposed corresponding to the first channel CH1, and has a gate insulating layer GI sandwiched between the first channel CH1 and the gate G1. The second gate G2 is disposed corresponding to the second channel CH2, and has a gate insulating layer GI sandwiched between the second channel CH2 and the gate G2. The first gate G1 and the second gate G2 are located on the same plane or the same insulating layer and are formed of the same conductive material, for example, thereby reducing the number of masks required for the manufacturing process.
An insulating layer I1 is formed on the first gate G1 and the second gate G2. A first source S1, a first drain D1, a second source S2 and a second drain D2 are formed on the substrate SB, wherein the first source S1 and the first drain D1 respectively correspond to and are electrically connected to the first source region SA1 and the first drain region DA1, and the second source S2 and the second drain D2 respectively correspond to and are electrically connected to the second source region SA2 and the second drain region DA 2. For example, a first source S1, a first drain D1, a second source S2 and a second drain D2 are formed on the insulating layer I1, the first source S1 and the first drain D1 are respectively connected to the first source region SA1 and the first drain region DA1 through the openings H1 and H2, and the second source S2 and the second drain D2 are respectively connected to the second source region SA2 and the second drain region DA2 through the openings H3 and H4. The openings H1, H2, H3, and H4 at least penetrate through the insulating layer I1, and in the present embodiment, the openings H1, H2, H3, and H4 penetrate through the insulating layer I1 and the gate insulating layer GI. The first source S1, the first drain D1, the second source S2 and the second drain D2 are disposed on the same plane or on the same insulating layer and are formed of the same conductive material, for example, so that the number of masks required for the manufacturing process can be reduced.
Although the insulating layer I1 is formed after the processing is performed in the embodiment, the invention is not limited thereto. In other embodiments, the insulating layer I1 is an interlayer dielectric (interlayer dielectric), and the insulating layer I1 is in contact with the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2, and the resistance of the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2 can be reduced by hydrogen or other elements in the interlayer dielectric. In other words, the process for reducing the resistance of the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2 is not necessarily a plasma process, and may be performed after the insulating layer I1 is formed.
To this end, the first active device T1 and the second active device T2 are substantially completed. The first active device T1 and the second active device T2 are disposed on the substrate SB. The first active device T1 includes a first active layer SM1, a first gate G1, a first source S1 and a first drain D1. The first active layer SM1 includes a first source region SA1, a first drain region DA1, and a first channel region CH1 between the first source region SA1 and the first drain region DA 1. The second active device T2 includes a second active layer SM2, a second gate G2, a second source S2 and a second drain D2. The second active layer SM2 includes a second source region SA2, a second drain region DA2, and a second channel region CH2 between the second source region SA2 and the second drain region DA 2.
In the present embodiment, the first channel CH1 is located between the substrate SB and the first gate G1, and the second channel CH2 is located between the substrate SB and the second gate G2, and the first active device T1 and the second active device T2 are top-gate thin film transistors, but the invention is not limited thereto. In other embodiments, the first active device T1 and the second active device T2 may be bottom gate thin film transistors or other types of thin film transistors.
Referring to fig. 1E, a passivation layer PL is formed on the first source S1, the first drain D1, the second source S2 and the second drain D2. In other words, the passivation layer PL is disposed on the first active device T1 and the second active device T2. The control electrode E is formed to be electrically connected to the second drain D2. In the present embodiment, the control electrode E is formed on the protection layer PL and electrically connected to the second drain D2 of the second active device T2 through the opening O of the protection layer PL. Thus, the electronic device 10 is substantially completed. In some embodiments, the first active device T1 and the second active device T2 are both N-type tfts, and another P-type tft may be additionally formed to form a Complementary Metal-Oxide-Semiconductor (CMOS) device together with the first active device T1 or the second active device T2.
Based on the above, since the materials of the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2 are the same, the resistances of the first active layer SM1 and the second active layer SM2 can be adjusted by the same process, and the first active device T1 and the second active device T2 having different performances can be manufactured without performing other processes on the first active layer SM1 (e.g., without performing an ion implantation process on silicon in the first active layer SM 1). Therefore, the use of the mask can be saved, and the electronic device 10 has the advantages of low manufacturing cost and easy manufacturing.
Fig. 2 is a schematic top view of an electronic device according to an embodiment of the invention. It should be noted that the embodiment of fig. 2 follows the element numbers and partial contents of the embodiment of fig. 1A to 1E, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.
Referring to fig. 1E and fig. 2, in the present embodiment, the electronic device 10 is a display device.
The substrate SB includes a display area AA and a non-display area BA adjacent to the display area AA. The non-display area BA has a driving circuit SR thereon.
In some embodiments, the first active device T1 is located in the non-display area BA, for example, in the driving circuit SR. The material of the first channel CH1 of the first active device T1 in the non-display area BA includes polysilicon, which enables the display device to have the advantage of a narrow bezel. In some embodiments, the second active device T2 is located in the display area AA, and the control electrode E is a pixel electrode. The material of the second channel CH2 of the second active device T2 in the display area AA includes a metal oxide (e.g., indium gallium zinc oxide), which enables the display device to operate at a low frequency, thereby obtaining an advantage of low power consumption.
In the present embodiment, the first active device T1 and the second active device T2 are both top gate tfts, so the display device has the advantage of high aperture ratio.
In some embodiments, the first active device T1 and the second active device T may be both located in the display area AA or both located in the driving circuit SR of the non-display area BA. The control electrode E may be a connection electrode for connecting other electronic components.
Fig. 3 is a schematic partial circuit diagram of an electronic device according to an embodiment of the invention. It should be noted that the embodiment of fig. 3 follows the element numbers and partial contents of the embodiment of fig. 1A to 1E, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.
Referring to fig. 1E and fig. 3, in the present embodiment, the first gate G1 of the first active device T1 is electrically connected to the scan line SL, the first source S1 of the first active device T1 is electrically connected to the data line DL, the first drain D1 of the first active device T1 is electrically connected to the second gate G2 of the second active device T2, the second source S2 of the second active device T2 is electrically connected to the signal line CL, and the second source S2 of the second active device T2 is electrically connected to the control electrode E. In some embodiments, the second gate G2 of the second active device T2 and the second source S2 of the second active device T2 may be electrically connected to two ends of the capacitor, respectively, but the invention is not limited thereto.
Although the first drain D1 of the first active device T1 is electrically connected to the second gate G2 of the second active device T2 in the present embodiment, the invention is not limited thereto. The first active element T1 and the second active element T2 can also be separated from each other.
Fig. 4A-4C are schematic cross-sectional views of a treatment process according to an embodiment of the invention. It should be noted that the embodiment of fig. 4A to 4C uses the element numbers and part of the contents of the embodiment of fig. 1A to 1E, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.
Referring to fig. 4A, a shielding layer SH is formed on the source region SA, the channel region CH and the drain region DA, the shielding layer SH is, for example, a photoresist layer defined by a half tone mask (halftone mask), and a thickness t1 of the shielding layer SH on the channel region CH is greater than a thickness t2 of the shielding layer SH on the source region SA and the drain region DA.
Referring to fig. 4B, the patterned mask layer SH' is formed by performing an ashing process on the mask layer SH, such as an oxygen plasma, but the invention is not limited thereto. Since the thickness t1 of the shielding layer SH on the channel region CH is greater than the thickness t2 of the shielding layer SH on the source and drain regions SA and DA, the patterned shielding layer SH' covers the channel region CH and exposes the source and drain regions SA and DA.
Referring to fig. 4C, a processing process is performed by using the patterned shielding layer SH' as a mask to make the resistances of the source region SA and the drain region DA smaller than the channel region CH. In some embodiments, the patterned mask layer SH 'is removed after the treatment process, but the invention is not limited thereto, and the patterned mask layer SH' may be remained to be used as a passivation layer for the channel region CH.
In some embodiments, the material of the channel region CH, the source region SA and the drain region DA comprises a metal oxide (e.g., indium gallium zinc oxide), and the treatment process is a hydrogen treatment process or other suitable process, wherein the source of hydrogen may be hydrogen in a hydrogen plasma or other insulating layer.
In some embodiments, the material of the channel region CH, the source region SA and the drain region DA includes silicon (e.g., polysilicon), and the treatment process is a doping process, such as an ion implantation process or other suitable processes.
Fig. 5A-5C are schematic cross-sectional views of a treatment process according to an embodiment of the invention. It should be noted that the embodiment of fig. 5A to 5C follows the element numbers and part of the contents of the embodiment of fig. 4A to 4C, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.
Referring to fig. 5A, a shielding layer SH is formed on the source region SA, the channel region CH and the drain region DA, and the shielding layer SH is, for example, a photoresist layer defined by a mask. The thickness of the shielding layer SH becomes thinner as it goes away from the center of the shielding layer SH, which can also be said that the thickness of the shielding layer SH at the center corresponding to the mask opening is larger than the thickness of the shielding layer SH at the edge corresponding to the mask opening.
Referring to fig. 5B, the patterned mask layer SH' is formed by performing an ashing process on the mask layer SH, such as an oxygen plasma, but the invention is not limited thereto. Since the thickness of the shield layer SH becomes thinner as it goes away from the center of the shield layer SH, the patterned shield layer SH' covers the channel region CH and exposes the source and drain regions SA and DA.
Referring to fig. 5C, a processing process is performed by using the patterned shielding layer SH' as a mask to make the resistances of the source region SA and the drain region DA smaller than the channel region CH. In some embodiments, the patterned mask layer SH 'is removed after the treatment process, but the invention is not limited thereto, and the patterned mask layer SH' may be remained to be used as a passivation layer for the channel region CH.
Fig. 6 is a schematic cross-sectional view of an electronic device according to an embodiment of the invention. It should be noted that the embodiment of fig. 6 uses the element numbers and part of the contents of the embodiments of fig. 1A to 1E, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.
The main difference between the electronic device 20 of fig. 6 and the electronic device 10 of fig. 1E is that: the first source region SA1 and the first drain region DA1 of the electronic device 20 cover the first channel region CH1 in the direction y perpendicular to the substrate SB.
Referring to fig. 6, since the first source region SA1 and the first drain region DA1 cover the portion of the first channel region CH1 in the direction y perpendicular to the substrate SB, the contact area between the first source region SA1 and the first channel region CH1 and the contact area between the first drain region DA1 and the first channel region CH1 can be larger. In the embodiment, the first source region SA1 and the first channel region CH1 can be easily aligned, and the first drain region DA1 and the first channel region CH1 can also be easily aligned. There is relatively no disconnection due to misalignment between the first source region SA1 and the first channel region CH1 or between the first drain region DA1 and the first channel region CH 1.
Fig. 7A to 7F are schematic cross-sectional views of an electronic device according to an embodiment of the invention. It should be noted that the embodiment of fig. 7A to 7F follows the element numbers and partial contents of the embodiment of fig. 1A to 1E, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.
Referring to fig. 7A, a first channel region CH1, a first source region SA1, a first drain region DA1, a second source region SA2, and a second drain region DA2 are formed on a substrate SB. The first channel region CH1 is located between the first source region SA1 and the first drain region DA1, and the first source region SA1, the first channel region CH1 and the first drain region DA1 are sequentially connected.
In the present embodiment, the materials of the first channel region CH1, the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2 include silicon, such as amorphous silicon, polycrystalline silicon, microcrystalline silicon or monocrystalline silicon. For example, the material of the first channel region CH1, the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2 includes polysilicon, and the process of forming the first channel region CH1, the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2 includes a Low Temperature Polysilicon (LTPS) process.
Referring to fig. 7B, a second channel CH2 is formed on the substrate SB. The second channel region CH2 is located between the second source region SA2 and the second drain region DA 2. The second source region SA2, the second channel region CH2, and the second drain region DA2 are connected in sequence.
In the present embodiment, the first channel CH1, the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2 are formed on the substrate SB, and then the second channel CH2 is formed on the substrate SB. The material of the first channel region CH1 is different from that of the second channel region CH2, and the materials of the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2 are the same. The material of the second channel region CH2 includes a metal oxide. In this embodiment, the material of the second channel CH2 includes indium gallium zinc oxide.
In some embodiments, the method of forming the second channel CH2 includes, for example, forming a metal oxide layer, and then patterning the metal oxide layer by acid etching to form the second channel CH 2. The acid etching is, for example, using oxalic acid or other suitable etching solution.
Referring to fig. 7C, the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2 are processed such that the resistances of the first source region SA1 and the first drain region DA1 are smaller than the resistance of the first channel region CH1, and the resistances of the second source region SA2 and the second drain region DA2 are smaller than the resistance of the second channel region CH 2. In the present embodiment, the treatment process includes a doping process, such as an ion implantation process. In the embodiment, after the processing, the materials of the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2 comprise doped silicon. The first source region SA1 and the first drain region DA1 are a first type of doped silicon, and the second source region SA2 and the second drain region DA2 are a second type of doped silicon. For example, the first type of doped silicon and the second type of doped silicon are both N-type doped silicon. In other embodiments, the first type of doped silicon and the second type of doped silicon are different types of doped silicon.
In some embodiments, the process further includes forming a patterned mask layer on the first channel CH1 before the treatment process, so as to prevent the treatment process from directly affecting the resistance of the first channel CH 1. In some embodiments, the patterned shielding layer may also be formed on the second channel region CH 2.
Referring to fig. 7D, in the present embodiment, a light doping process may be selectively performed to form a light doped region M between the first source region SA1 and the first channel region CH1 and between the first drain region DA1 and the first channel region CH 1.
In some embodiments, the lightly doped region M may also be included between the second source region SA2 and the second channel region CH2 and between the second drain region DA2 and the second channel region CH2, but the invention is not limited thereto.
Referring to fig. 7E, a gate insulating layer GI is formed on the substrate SB. In the present embodiment, the gate insulating layer GI is formed on the first source region SA1, the first drain region DA1, the second source region SA2, the second drain region DA2, the first channel region CH1, the second channel region CH2, and the lightly doped region M.
A first gate G1 and a second gate G2 are formed on the substrate SB. In the present embodiment, the first gate G1 and the second gate G2 are formed on the gate insulating layer GI. The first gate G1 is disposed corresponding to the first channel CH1, and has a gate insulating layer GI sandwiched between the first channel CH1 and the gate G1. The second gate G2 is disposed corresponding to the second channel CH2, and has a gate insulating layer GI sandwiched between the second channel CH2 and the gate G2. The first gate G1 and the second gate G2 are located on the same plane or the same insulating layer and are formed of the same conductive material, for example, thereby reducing the number of masks required for the manufacturing process.
An insulating layer I1 is formed on the first gate G1 and the second gate G2. A first source S1, a first drain D1, a second source S2 and a second drain D2 are formed on the substrate SB, wherein the first source S1 and the first drain D1 respectively correspond to and are electrically connected to the first source region SA1 and the first drain region DA1, and the second source S2 and the second drain D2 respectively correspond to and are electrically connected to the second source region SA2 and the second drain region DA 2. For example, a first source S1, a first drain D1, a second source S2 and a second drain D2 are formed on the insulating layer I1, the first source S1 and the first drain D1 are respectively connected to the first source region SA1 and the first drain region DA1 through the openings H1 and H2, and the second source S2 and the second drain D2 are respectively connected to the second source region SA2 and the second drain region DA2 through the openings H3 and H4. The openings H1, H2, H3, and H4 at least penetrate through the insulating layer I1, and in the present embodiment, the openings H1, H2, H3, and H4 penetrate through the insulating layer I1 and the gate insulating layer GI. The first source S1, the first drain D1, the second source S2 and the second drain D2 are disposed on the same plane or on the same insulating layer and are formed of the same conductive material, for example, so that the number of masks required for the manufacturing process can be reduced.
Although the gate insulating layer GI, the first gate G1 and the second gate G2 are formed after the processing is performed in the embodiment, the invention is not limited thereto. In other embodiments, the gate insulating layer GI, the first gate G1 and the second gate G2 are formed first, and then the first gate G1 and the second gate G2 are used as a mask to perform a processing process. In some embodiments, a patterned conductive layer is formed on the gate insulating layer GI, and then a treatment process is performed using the patterned conductive layer as a mask, and then the patterned conductive layer is etched to form the first gate G1 and the second gate G2, and then a light doping process is performed using the first gate G1 and the second gate G2 as masks.
To this end, the first active device T1 and the second active device T2 are substantially completed. The first active device T1 and the second active device T2 are disposed on the substrate SB. The first active device T1 includes a first active layer SM1, a first gate G1, a first source S1 and a first drain D1. The first active layer SM1 includes a first source region SA1, a first drain region DA1, and a first channel region CH1 and a lightly doped region M between the first source region SA1 and the first drain region DA 1. The second active device T2 includes a second active layer SM2, a second gate G2, a second source S2 and a second drain D2. The second active layer SM2 includes a second source region SA2, a second drain region DA2, and a second channel region CH2 between the second source region SA2 and the second drain region DA 2.
In the present embodiment, the first channel CH1 is located between the substrate SB and the first gate G1, and the second channel CH2 is located between the substrate SB and the second gate G2, and the first active device T1 and the second active device T2 are top-gate thin film transistors, but the invention is not limited thereto. In other embodiments, the first active device T1 and the second active device T2 may be bottom gate thin film transistors or other types of thin film transistors.
Referring to fig. 7F, a passivation layer PL is formed on the first source S1, the first drain D1, the second source S2 and the second drain D2. In other words, the passivation layer PL is disposed on the first active device T1 and the second active device T2. The control electrode E is formed to be electrically connected to the second drain D2. In the present embodiment, the control electrode E is formed on the protection layer PL and electrically connected to the control electrode E through the opening O of the protection layer PL. To this end, the electronic device 30 is substantially completed.
Based on the above, since the materials of the first source region SA1, the first drain region DA1, the second source region SA2 and the second drain region DA2 are the same, the resistances of the first active layer SM1 and the second active layer SM2 can be adjusted by the same process, and the first active device T1 and the second active device T2 having different performances can be manufactured without performing other processes on the second active layer SM2 (for example, without performing a hydrogen plasma process on the metal oxide in the second active layer SM 2). Therefore, the use of the mask can be saved, and the electronic device 30 has the advantages of low manufacturing cost and easy manufacturing.
Fig. 8 is a schematic cross-sectional view of an electronic device according to an embodiment of the invention. It should be noted that the embodiment of fig. 8 follows the element numbers and partial contents of the embodiment of fig. 7A to 7F, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.
The main difference between the electronic device 40 of fig. 8 and the electronic device 30 of fig. 7F is that: the second channel region CH2 of the electronic device 40 covers a portion of the second source region SA2 and a portion of the second drain region DA2 in the direction y perpendicular to the substrate SB.
Referring to fig. 8, since the second channel region CH2 covers a portion of the second source region SA2 and a portion of the second drain region DA2 in the direction y perpendicular to the substrate SB, the contact area between the second source region SA2 and the second channel region CH2 and the contact area between the second drain region DA2 and the second channel region CH2 may be larger. In the embodiment, the second source region SA2 and the second channel region CH2 can be easily aligned, and the second drain region DA2 and the second channel region CH2 can also be easily aligned. There is relatively no disconnection due to misalignment between the second source region SA2 and the second channel region CH2 or between the second drain region DA2 and the second channel region CH 2.
In summary, since the materials of the first source region, the first drain region, the second source region and the second drain region are the same, the same process can be used to adjust the resistances of the first active layer and the second active layer, so as to manufacture the first active device and the second active device with different performances. Therefore, the use of the mask can be saved, and the electronic device has the advantages of low manufacturing cost and easy manufacturing.
Although the present invention has been described with reference to the above embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (18)

1. An electronic device, comprising:
a substrate;
a first active device on the substrate, comprising:
a first active layer including a first source region, a first drain region, and a first channel region between the first source region and the first drain region;
a first gate electrode disposed corresponding to the first channel region and having a gate insulating layer therebetween; and
a first source electrode and a first drain electrode, which are respectively corresponding to and electrically connected to the first source region and the first drain region;
a second active device on the substrate, comprising:
a second active layer including a second source region, a second drain region, and a second channel region between the second source region and the second drain region, wherein the material of the first channel region is different from the material of the second channel region, and the materials of the first source region, the first drain region, the second source region, and the second drain region are the same;
a second gate electrode disposed corresponding to the second channel region and having the gate insulating layer interposed therebetween; and
a second source and a second drain respectively corresponding to and electrically connected to the second source region and the second drain region;
a passivation layer on the first active device and the second active device;
and the control electrode is electrically connected with the second drain electrode.
2. The electronic device of claim 1, wherein the material of the first channel region comprises silicon.
3. The electronic device of claim 1, wherein the material of the second channel region comprises a metal oxide.
4. The electronic device of claim 1, wherein the first source region and the first drain region have a resistance less than a resistance of the first channel region, and the second source region and the second drain region have a resistance less than a resistance of the second channel region.
5. The electronic device of claim 1, wherein the first channel region is between the substrate and the first gate, and the second channel region is between the substrate and the second gate.
6. The electronic device of claim 1, wherein the first source region and the first drain region cover a portion of the first channel region in a direction perpendicular to the substrate.
7. The electronic device of claim 1, wherein the second channel region covers a portion of the second source region and a portion of the second drain region in a direction perpendicular to the substrate.
8. The electronic device of claim 1, wherein a material of the first source region, the first drain region, the second source region, and the second drain comprises doped silicon.
9. The electronic device of claim 1, wherein the first active device is in a non-display region, the second active device is in a display region, and the control electrode is a pixel electrode.
10. The electronic device of claim 1, wherein the first active device and the second active device are located in a display area.
11. A method of manufacturing an electronic device, comprising:
providing a substrate;
forming a first source region, a first channel region, a first drain region, a second source region and a second drain region on the substrate, and then forming a second channel on the substrate, wherein the material of the first channel region is different from that of the second channel region, and the materials of the first source region, the first drain region, the second source region and the second drain region are the same;
forming a gate insulating layer on the substrate;
forming a first grid and a second grid on the substrate;
forming a first source electrode, a first drain electrode, a second source electrode and a second drain electrode on the substrate, wherein the first source electrode and the first drain electrode correspond to and are electrically connected to the first source electrode region and the first drain electrode region respectively, and the second source electrode and the second drain electrode correspond to and are electrically connected to the second source electrode region and the second drain electrode region respectively;
forming a protective layer on the first source electrode, the first drain electrode, the second source electrode and the second drain electrode;
forming a control electrode to electrically connect the second drain.
12. The method of claim 11, wherein the gate insulating layer is formed on the first channel region and the second channel region, and the first gate and the second gate are formed on the gate insulating layer, wherein the first channel region is between the substrate and the first gate, and the second channel region is between the substrate and the second gate.
13. The method of claim 11, wherein the first channel region is between the first source region and the first drain region, and the second channel region is between the second source region and the second drain region.
14. The method of claim 11, wherein the first channel is formed on the substrate, and then the first source region, the first drain region, the second source region, the second channel region, and the second drain region are formed on the substrate.
15. The method of claim 11, further comprising processing the first source region, the first drain region, the second source region, and the second drain region such that the first source region and the first drain region have a resistance less than a resistance of the first channel region and the second source region and the second drain region have a resistance less than a resistance of the second channel region.
16. The method of claim 15, wherein the process comprises a plasma process, and the material of the first source region, the first drain region, the second source region, and the second drain region comprises a metal oxide.
17. The method of claim 15, further comprising forming a patterned mask layer over the second channel region prior to the treatment process.
18. The method of claim 15, wherein the process comprises a doping process, and wherein the material of the first source region, the first drain region, the second source region, and the second drain region comprises doped silicon after the process.
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