CN112951791A - Stacked package structure and packaging method - Google Patents
Stacked package structure and packaging method Download PDFInfo
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- CN112951791A CN112951791A CN201911264599.9A CN201911264599A CN112951791A CN 112951791 A CN112951791 A CN 112951791A CN 201911264599 A CN201911264599 A CN 201911264599A CN 112951791 A CN112951791 A CN 112951791A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 20
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- 229910000679 solder Inorganic materials 0.000 claims description 47
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- 229910052710 silicon Inorganic materials 0.000 description 4
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- 238000004544 sputter deposition Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
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- 238000005476 soldering Methods 0.000 description 2
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910008599 TiW Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The invention relates to a stacked packaging structure, which comprises a chip, wherein a first dielectric layer is arranged on the active surface of the chip; the rewiring layer is arranged on the first dielectric layer, a first metal layer opening is formed in the rewiring layer, and at least part of the first dielectric layer is exposed out of the first metal layer opening; the second dielectric layer is arranged on the rewiring layer; the surface of the first dielectric layer is also provided with a first groove, the first groove is communicated with the first metal layer opening, and the second dielectric layer is connected with the first dielectric layer through the first metal layer opening and the first groove. Through the arrangement, the problem that the junction of the three-layer stacked structure is easy to delaminate or crack due to different expansion or contraction degrees of the structural material between the rewiring layer and the two dielectric layers in the thermal cycle manufacturing process and the reliability process of the existing stacked packaging structure can be solved.
Description
Technical Field
The invention relates to the technical field of packaging, in particular to a stacked packaging structure and a packaging method.
Background
As a main way of high-density integration of packaging at present, stacked packaging is gaining more and more attention, stacking of chips is one of the main approaches to increase the density of electronic packaging, and the stacked packaging technology has been widely developed and applied in the industry.
In the package on package structure of the prior art, metal layers such as a redistribution layer are disposed between two organic dielectric passivation layers, that is, the redistribution layer covers the first dielectric layer, and the second dielectric layer covers the redistribution layer, thereby forming a three-layer package on package structure.
In the thermal cycle process and the reliability process, the redistribution layer and the two dielectric layers are easily subjected to thermal expansion and contraction when cooled after being influenced by temperature difference; the thermal expansion coefficients of the two structural materials of the dielectric layer and the redistribution layer are different, the expansion or contraction degrees of the two structural materials of the redistribution layer and the two dielectric layers are different, and the boundary of the two structural materials is pulled by stress, so that the boundary of the three-layer stacked packaging structure is easy to be layered or cracked, namely the boundary of the redistribution layer, the first dielectric layer and the second dielectric layer is easy to be layered or cracked.
Disclosure of Invention
The invention aims to provide a stacked packaging structure and a packaging method, which aim to solve the problem that the junction of a three-layer stacked structure is easy to delaminate or crack due to different expansion or contraction degrees of structural materials between a rewiring layer and two dielectric layers in the thermal cycle manufacturing process and the reliability process of the conventional stacked packaging structure.
In order to achieve one of the above objectives, an embodiment of the present invention provides a stacked package structure, including a chip, a first dielectric layer disposed on an active surface of the chip; the rewiring layer is arranged on the first dielectric layer, a first metal layer opening is formed in the rewiring layer, and at least part of the first dielectric layer is exposed out of the first metal layer opening; the second dielectric layer is arranged on the rewiring layer; the surface of the first dielectric layer is also provided with a first groove, the first groove is communicated with the first metal layer opening, and the second dielectric layer is connected with the first dielectric layer through the first metal layer opening and the first groove.
As a further improvement of the embodiment of the present invention, the width of the first groove is not less than the width of the opening of the first metal layer, and the depth of the first groove exceeds 0.3 um.
As a further improvement of an embodiment of the present invention, a width of the first groove is equal to a width of the first metal layer opening.
As a further improvement of the embodiment of the present invention, a second dielectric layer opening is further formed in the second dielectric layer, and at least a portion of the redistribution layer is exposed by the second dielectric layer opening; the packaging structure further comprises a solder ball, and the solder ball is electrically connected with the redistribution layer through the second dielectric layer opening.
As a further improvement of an embodiment of the present invention, the package structure further includes an under ball metal layer disposed between the solder ball and the redistribution layer, the under ball metal layer electrically connects the solder ball and the redistribution layer through the second dielectric layer opening, and a second metal layer opening is formed by surrounding a part of a side surface of the under ball metal layer and a surface of the redistribution layer; the surface of the second dielectric layer is also provided with a second groove.
As a further improvement of an embodiment of the present invention, a height difference between a bottom surface of the second groove and an upper side surface of the second metal layer opening is more than 0.3 um.
As a further improvement of an embodiment of the present invention, the second groove is in communication with or at least partially overlaps the second metal layer opening.
As a further improvement of an embodiment of the present invention, the package structure further includes a third dielectric layer disposed above the second dielectric layer, and the third dielectric layer encapsulates the ubm layer.
An embodiment of the present invention further provides a stack packaging method, including: arranging a first dielectric layer on the active surface of a wafer or a chip; arranging a rewiring layer on the first dielectric layer, and forming a first metal layer opening on the rewiring layer to expose at least part of the first dielectric layer; forming a first groove on the surface of the first dielectric layer, so that the first groove is communicated with the first metal layer opening; and arranging a second dielectric layer on the rewiring layer, so that the second dielectric layer is connected with the first dielectric layer through the first metal layer opening and the first groove.
As a further improvement of an embodiment of the present invention, the method further comprises: the width of the first groove is not less than the width of the opening of the first metal layer, and the depth of the first groove exceeds 0.3 um.
As a further improvement of an embodiment of the present invention, the method further comprises: forming a second dielectric layer opening on the second dielectric layer, so that the second dielectric layer opening exposes at least part of the rewiring layer; and implanting a solder ball into the opening of the second dielectric layer so that the solder ball is electrically connected with the redistribution layer.
As a further improvement of an embodiment of the present invention, the method further comprises: and arranging an under-ball metal layer between the solder ball and the redistribution layer, so that the solder ball is electrically connected with the redistribution layer through the second dielectric layer opening by the under-ball metal layer, and a second metal layer opening is formed by enclosing part of the side surface of the under-ball metal layer and the surface of the redistribution layer.
As a further improvement of an embodiment of the present invention, the method further comprises: and arranging a second groove on the surface of the second dielectric layer, so that the height difference between the bottom surface of the second groove and the upper side surface of the second metal layer opening is more than 0.3um, and the second groove is communicated with or at least partially overlapped with the second metal layer opening.
Compared with the prior art, the invention has the beneficial effects that: the groove is formed in the surface of the first dielectric layer, the second dielectric layer is embedded into the first dielectric layer, the contact area between the two dielectric layers is increased, and the adhesive force between the dielectric layers is increased, so that the stress between the dielectric layers and the heavy wiring layer is resisted, and the layering or the crack at the junction of the heavy wiring layer and the two dielectric layers is prevented.
Drawings
FIG. 1 is a schematic cross-sectional view of a package structure according to a first embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a package structure according to a second embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of a package structure according to a third embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of a package structure according to a fourth embodiment of the present invention;
FIG. 5 is a flow chart of a packaging method in a first embodiment of the present invention;
fig. 6 is a schematic structural diagram corresponding to each step in the first embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clear, the technical solutions of the present application will be clearly and completely described below with reference to the detailed description of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
As shown in fig. 1 to 3, an embodiment of the invention provides a stacked package structure, which includes a chip 9, where the chip 9 may be a silicon chip or a fan-out redistribution substrate, such as a heterogeneous chip composed of eWLB (embedded wafer level ball grid array) molding compound and silicon. The first dielectric layer 21 is arranged on the active surface 91 of the chip 9; the redistribution layer 4 is disposed on the first dielectric layer 21, the redistribution layer 4 is provided with a first metal layer opening 41, and at least a part of the first dielectric layer 21 is exposed from the first metal layer opening 41; a second dielectric layer 22 is provided on the rewiring layer 4; the surface of the first dielectric layer 21 is further formed with a first groove 211, the first groove 211 is communicated with the first metal layer opening 41, and the second dielectric layer 22 is connected to the first dielectric layer 21 through the first metal layer opening 41 and the first groove 211.
In the embodiment of the present invention, the stacked package structure is a chip-scale package, the package structure includes a chip 9 having an active surface 91, and the three-layer stacked structure is disposed on the active surface 91 of the chip 9 in a manner of stacking layer by layer, i.e., the first dielectric layer 21 is disposed above the active surface 91 of the chip 9, the redistribution layer 4 is disposed above the first dielectric layer 21, and the second dielectric layer 22 is disposed above the redistribution layer 4, thereby forming a three-layer structure.
The redistribution layer 4 is a metal layer, in order to implement line routing, the redistribution layer 4 is provided with a first metal layer opening 41, and the first metal layer opening 41 penetrates through the redistribution layer 4 along the material thickness direction to expose at least part of the surface of the first dielectric layer 21; the second dielectric layer 22 may be connected to the underlying first dielectric layer 21 through or past the first metal layer opening 41.
Because the thermal expansion coefficients of the two materials of the dielectric layer and the redistribution layer 4 are different, and the first dielectric layer 21 and the second dielectric layer 22 may be different materials, or the thicknesses and areas of the two dielectric layers are different, the three-layer structure is easily contracted when cooled by thermal expansion in the thermal cycle process, and the three-layer structure is easily layered or cracked at the boundary of the three-layer structure at the boundary of the first metal layer opening 41 under the action of stress. Therefore, a first groove 211 is formed on the surface of the first dielectric layer 21, and the second dielectric layer 22 can continue to pass through the first groove 211 after passing through the first metal layer opening 41, and is finally connected with the first dielectric layer 21; i.e. the second dielectric layer 22 at least partly enters or is embedded in the first dielectric layer 21. Therefore, the contact area between the two dielectric layers is increased, the adhesive force between the two dielectric layers is improved, and the stress action between the two dielectric layers and the heavy wiring layer 4 can be resisted, so that the delamination or the generation of cracks is prevented, and the reliability is improved.
Meanwhile, in order to realize functional system interconnection, a metal pad 95 and a protective layer 93 can be further arranged on the active surface 91 of the chip 9, and the metal pad 95 is exposed outside the protective layer 93; the first dielectric layer 21 further has an opening for exposing at least a portion of the metal pad 95; the redistribution layer 4 is electrically connected to the metal pad 95 through the opening, so that the redistribution layer 4 and the chip 9 are electrically connected to each other.
The first dielectric layer 21 may be disposed on the active surface 91 of the chip 9 by a coating process, and the material is not limited, and may be benzocyclobutene (BCB), Polyimide (PI), or other polymer dielectric materials, or polymer dielectric materials with fillers.
The redistribution layer 4 may be disposed above the first dielectric layer 21 by sputtering or electroplating, and the material of the redistribution layer 4 may be a single-layer or multi-layer structure of metal such as titanium, TiW, copper, nickel and gold, such as 200-1000A Ti and 2-30um Cu.
The second dielectric layer 22 may also be processed by coating or the like to be provided on the surface of the redistribution layer 4 and the exposed surface of the first dielectric layer 21.
The processing form of the first metal layer opening 41 and the first groove 211 is not limited, and a part of the redistribution layer 4 and a part of the first dielectric layer 21 can be removed by photolithography etching or laser etching, so as to obtain both the first metal layer opening 41 and the first groove 211; the processing forms of the two can be the same or different.
In addition, the stacked package structure is a wafer-level or board-level package, for example, the package structure includes a wafer, the wafer has an active surface 91, and the three-layer stacked structure is disposed on the active surface 91 of the wafer by laying the wafer layer by layer. The chip 9 may be a silicon chip, or a fan-out redistribution substrate, such as a heterogeneous chip composed of eWLB (embedded wafer level ball grid array) molding compound and silicon.
Further, the width of the first groove 211 is not less than the width of the first metal layer opening 41, and the depth of the first groove 211 exceeds 0.3 um.
Further, the width of the first groove 211 is equal to the width of the first metal layer opening 41.
Specifically, in order to increase the contact area of the two dielectric layers, the depth of the first groove 211 may be set to exceed 0.3um, so that the nesting portion between the first dielectric layer 21 and the second dielectric layer 22 is as large as possible. Wherein, verify through actual experiment, set up embedding depth to exceed 0.3um and can effectively avoid the layering phenomenon.
Meanwhile, the first groove 211 is widened in width so that the boundary of the first groove 211 may be aligned with the first metal layer opening 41, or the boundary of the first groove 211 is located below the rewiring layer 4; as shown in fig. 2, preferably, for ease of processing, the boundaries of the first recess 211 may be aligned with the first metal layer opening 41, both of which may be processed by laser or etching.
Therefore, the two dielectric layers are mutually nested, the contact area is greatly increased, the adhesive force is improved, the stress action between the dielectric layers and the heavy wiring layer 4 can be resisted, and delamination or cracks are prevented.
Further, a second dielectric layer opening 221 is further formed in the second dielectric layer 22, and at least a portion of the redistribution layer 4 is exposed by the second dielectric layer opening 221; the package structure further includes solder balls 8, and the solder balls 8 are electrically connected to the redistribution layer 4 through the second dielectric layer openings 221.
In order to electrically connect other external circuits, such as a circuit board (PCB), a chip 9 or other semiconductor packages, a solder ball 8 may be disposed on the second dielectric layer 22 to electrically connect the solder ball 8 with the redistribution layer 4.
Specifically, a second dielectric layer opening 221 is formed in the second dielectric layer 22, and the second dielectric layer opening 221 penetrates through the second dielectric layer 22 along the material thickness direction to expose at least a part of the surface of the redistribution layer 4; the solder balls 8 can pass through or penetrate the second dielectric layer openings 221 and then electrically connect with the underlying redistribution layer 4. The solder balls 8 may be implanted into the second dielectric layer openings 221 and directly contact the redistribution layer 4, or contact the redistribution layer 4 through the ubm layer 6.
Further, the package structure further includes an under ball metal layer 6 disposed between the solder ball 8 and the redistribution layer 4, the under ball metal layer 6 electrically connects the solder ball 8 and the redistribution layer 4 through the second dielectric layer opening 221, and a second metal layer opening 62 is formed by enclosing a part of the side surface of the under ball metal layer 6 and the surface of the redistribution layer 4; the surface of the second dielectric layer 22 is further formed with a second groove 222.
Further, the height difference between the bottom surface of the second groove 222 and the upper side surface of the second metal layer opening 62 exceeds 0.3 um.
Further, the second groove 222 is in communication with or at least partially overlaps the second metal layer opening 62.
As shown in fig. 3, to facilitate the soldering of the solder ball 8, an under ball metal layer 6 may be formed in the second dielectric layer opening 221, the under ball metal layer 6 is electrically connected to the redistribution layer 4 below after passing through or penetrating through the second dielectric layer opening 221, and then a solder ball 8, such as a solder ball 8, is formed above the under ball metal layer 6, so that the solder ball 8 is electrically connected to the under ball metal layer 6. Therefore, the exposed area of the metal circuit of the redistribution layer 4 is increased, the solder ball 8 is convenient to weld, and the electrical connection with the redistribution layer 4 is firm.
When the ubm layer 6 is disposed, the second dielectric layer 22 is located below the ubm layer 6 and embedded in the ubm layer 6, and a stress effect caused by thermal expansion and contraction exists between the ubm layer 6 and the second dielectric layer 22. To improve this, a second recess 222 may be formed on the surface of the second dielectric layer 22 to reduce the material content of the second dielectric layer 22.
Preferably, part of the second dielectric layer 22 is removed, and a second groove 222 with a depth exceeding 0.3um is formed on the surface thereof, so as to reduce the material amount of the second dielectric layer 22; meanwhile, the boundary of the second groove 222 may be flush with the boundary of the ubm layer 6 to facilitate processing; or the second groove 222 enters the position below the ubm layer 6, so that the hollowed area of the second groove 222 on the surface of the second dielectric layer 22 is as large as possible, and the contact area between the second dielectric layer 22 and the ubm layer 6 is as small as possible, thereby maximally relieving the stress action and changing the stress direction of different materials generated by thermal expansion and cold contraction, preventing delamination or cracks from being generated, and improving reliability.
Further, the package structure further includes a third dielectric layer 23 disposed above the second dielectric layer 22, and the third dielectric layer 23 encapsulates the ubm layer.
In order to further improve the reliability of the whole packaging structure, a third dielectric layer 23 is arranged to encapsulate the UBM metal layer 6, and the exposed UBM metal layer 6 is wrapped. The third dielectric layer 23 may be an island structure covering the UBM 6 and is opened along the side of the UBM 6, for example, the cross-sectional shape of the third dielectric layer 23 may be a ring or a square with a chamfer.
Therefore, the durability and the persistence of the whole packaging structure are improved, and the reliability is enhanced; the independent third dielectric layer 23 protects the single UBM metal layer 6, so that the deformation of the UBM metal layer 6 caused by thermal expansion and cold contraction can be reduced, and the warpage change of the wafer and the package body can be prevented.
For ease of understanding, examples are described in detail below:
example 1
As shown in fig. 1, the active surface 91 of the chip 9 has a three-layer stacked structure, a metal pad 95 and a passivation layer 93 are further disposed on the active surface 91, and the metal pad 95 is exposed outside the passivation layer 93.
The first dielectric layer 21 is disposed over the active surface 91 of the chip 9; the first dielectric layer 21 is further provided with an opening to expose at least a portion of the metal pad 95.
The rewiring layer 4 is disposed above the first dielectric layer 21; the redistribution layer 4 is electrically connected with the exposed part of the metal pad 95 through the opening formed in the first dielectric layer 21; the redistribution layer 4 is provided with a first metal layer opening 41, and the first metal layer opening 41 penetrates through the redistribution layer 4 along the material thickness direction to expose at least a part of the surface of the first dielectric layer 21.
The surface of the first dielectric layer 21 is further provided with a first groove 211, the first groove 211 is communicated with the first metal layer opening 41, and the width of the first groove 211 is greater than that of the first metal layer, that is, the boundary of the first groove 211 enters below the redistribution layer 4.
The second dielectric layer 22 is disposed above the redistribution layer 4; forming a second dielectric layer opening 221 in the second dielectric layer 22 to expose at least a portion of the surface of the redistribution layer 4; solder balls 8 are disposed at the positions of the openings 221 of the second dielectric layer, and the solder balls 8 are soldered and fixed to the redistribution layer 4 to achieve electrical connection.
Example 2
As shown in fig. 2, similarly, the active surface 91 of the chip 9 is provided with a three-layer stacked structure, a metal pad 95 and a passivation layer 93 are further provided on the active surface 91, and the metal pad 95 is exposed outside the passivation layer 93.
Different from the first embodiment, in this embodiment, the widths of the first groove 211 and the first metal layer are the same, that is, the boundary of the first groove 211 is flush with the boundary of the first metal layer, and both can be processed and formed by laser or etching, so that the processing is convenient and the process is simple.
Example 3
As shown in fig. 3, similarly, the active surface 91 of the chip 9 is provided with a three-layer stacked structure, a metal pad 95 and a passivation layer 93 are further provided on the active surface 91, and the metal pad 95 is exposed outside the passivation layer 93.
Unlike the first embodiment, in the present embodiment, the ubm layer 6 is formed in the second dielectric layer opening 221, and the ubm layer 6 is electrically connected to the redistribution layer 4 below after passing through or passing through the second dielectric layer opening 221.
A solder ball 8 or other metal solder ball is formed on the under-ball metal layer 6 by soldering, so that the solder ball 8 is electrically connected with the under-ball metal layer 6.
Example 4
As shown in fig. 4, similarly, the active surface 91 of the chip 9 is provided with a three-layer stacked structure, a metal pad 95 and a passivation layer 93 are further provided on the active surface 91, and the metal pad 95 is exposed outside the passivation layer 93.
Unlike the third embodiment, in the present embodiment, a third dielectric layer 23 encapsulating the UBM metal layer 6 is provided over the second dielectric layer 22, and the exposed UBM metal layer 6 is wrapped. The third dielectric layer 23 is an island structure covering the UBM 6, and is opened along the side of the UBM 6, for example, the cross-sectional shape of the third dielectric layer 23 is a ring or a square with a chamfer.
As shown in fig. 5, an embodiment of the present invention further provides a package on package method, which includes the following steps:
s2 disposing the first dielectric layer 21 on the active surface 91 of the wafer or chip 9;
s4 disposing a redistribution layer 4 on the first dielectric layer 21, and opening a first metal layer opening 41 on the redistribution layer 4, so that at least a portion of the first dielectric layer 21 is exposed by the first metal layer opening 41;
s6 forming a first recess 211 in the surface of the first dielectric layer 21, such that the first recess 211 and the first metal layer opening 41 are in communication with each other;
s8 disposing the second dielectric layer 22 on the redistribution layer 4 such that the second dielectric layer 22 is connected with the first dielectric layer 21 via the first metal layer opening 41 and the first recess 211.
In the embodiment of the present invention, the package structure is a wafer level package or a chip level package, and the wafer or the chip 9 has an active surface 91.
First, the first dielectric layer 21 is disposed over the active surface 91 of the chip 9 by a coating process or the like. Then, the redistribution layer 4 is disposed above the first dielectric layer 21 by sputtering or electroplating; forming a first metal layer opening 41 in the redistribution layer 4, wherein the first metal layer opening 41 penetrates through the redistribution layer 4 along the material thickness direction to expose at least part of the surface of the first dielectric layer 21; meanwhile, a first groove 211 is also formed in the surface of the first dielectric layer 21, and the first groove 211 and the first metal layer opening 41 may be processed together by photolithography etching or laser etching; then, a second dielectric layer 22 is disposed above the redistribution layer 4 by a coating process or the like; the second dielectric layer 22 can pass through both the first metal layer opening 41 and the first recess 211 and then enter the first dielectric layer 21 below, i.e. the first dielectric layer 21 and the second dielectric layer 22 are nested and connected with each other. The first dielectric layer 21 and the second dielectric layer 22 may be different materials, or the thicknesses and areas of the two dielectric layers may be different.
Further, for step S6, the method specifically includes:
the width of the first groove 211 is not less than the width of the first metal layer opening 41, and the depth of the first groove 211 exceeds 0.3 um.
To increase the contact area of the two dielectric layers, the depth of the first groove 211 is set to exceed 0.3um, and the width of the first groove 211 is widened such that the boundary of the first groove 211 is aligned with the first metal layer opening 41, or the boundary of the first groove 211 is located below the rewiring layer 4.
Further, after step S8, the method further includes:
s91 opening a second dielectric layer opening 221 in the second dielectric layer 22, so that the second dielectric layer opening 221 exposes at least a portion of the redistribution layer 4;
s93 implanting solder balls 8 into the second dielectric layer openings 221, such that the solder balls 8 are electrically connected to the redistribution layer 4.
Further, for step S93, the method specifically includes:
s931 places the ubm layer 6 between the solder ball 8 and the redistribution layer 4, so that the ubm layer 6 electrically connects the solder ball 8 and the redistribution layer 4 through the second dielectric layer opening 221, and a portion of the side surface of the ubm layer 6 and the surface of the redistribution layer 4 surround to form a second metal layer opening 62.
Further, for step S931, the method specifically includes:
a second groove 222 is formed in the surface of the second dielectric layer 22, such that the height difference between the bottom surface of the second groove 222 and the upper side surface of the second metal layer opening 62 exceeds 0.3um, and the second groove 222 is communicated with or at least partially overlapped with the second metal layer opening 62.
After the ubm layer 6 is disposed, a second metal layer opening 62 is formed by surrounding a part of the side surface of the ubm layer 6 and the surface of the redistribution layer 4, and a stress effect caused by thermal expansion and contraction exists between the ubm layer 6 and the second dielectric layer 22.
In order to improve the situation, a second groove 222 may be further formed on the surface of the second dielectric layer 22, the depth of the second groove 222 exceeds 0.3um, and the boundary may be flush with the boundary of the ubm layer 6, or the second groove 222 enters below the ubm layer 6, so that the contact area between the second dielectric layer 22 and the ubm layer 6 is as small as possible, thereby maximally relieving the stress effect of different materials generated by thermal expansion and contraction.
The package-on-package method is generally described as follows:
in the embodiment of the present invention, as shown in fig. 6, the package structure is a wafer level package or a chip level package, and the wafer or the chip 9 has an active surface 91. The active surface 91 is further provided with a metal pad 95 and a passivation layer 93, and the metal pad 95 is exposed outside the passivation layer 93.
First, the first dielectric layer 21 is disposed above the active surface 91 and the metal pad 95 by a coating process, and the first dielectric layer 21 further has an opening exposing at least a portion of the metal pad 95.
Then, the redistribution layer 4 is disposed above the first dielectric layer 21 by means of sputtering or electroplating; the redistribution layer 4 is electrically connected to the exposed portion of the metal pad 95 through the opening of the first dielectric layer 21, so as to be electrically connected to the chip 9.
Removing part of the redistribution layer 4 and part of the first dielectric layer 21 by photolithography etching or laser etching to form a first metal layer opening 41 penetrating through the redistribution layer 4 and a first groove 211 on the surface of the first dielectric layer 21;
then, the second dielectric layer 22 is disposed above the redistribution layer 4 by a coating process and the like; forming a second dielectric layer opening 221 in the second dielectric layer 22 to expose at least a part of the surface of the redistribution layer 4; solder balls 8 are implanted at the positions of the second dielectric layer openings 221, so that the solder balls 8 are electrically connected with the redistribution layer 4.
In summary, in the stacked package structure provided by the present invention, a three-layer stacked structure of the first dielectric layer 21, the redistribution layer 4 and the second dielectric layer 22 is sequentially disposed above the active surface 91 of the chip 9, the first groove 211 is additionally formed on the surface of the first dielectric layer 21, so that the first dielectric layer 21 can enter the second dielectric layer 22, the contact area between the two nested dielectric layers is increased, the adhesive force between the two dielectric layers is improved, the stress between the two dielectric layers and the redistribution layer 4 can be resisted, and thus delamination or crack generation is prevented, and reliability is improved.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention and is not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention are included in the scope of the present invention.
Claims (13)
1. A stacked package structure comprises a chip, a first dielectric layer arranged on the active surface of the chip; the rewiring layer is arranged on the first dielectric layer, a first metal layer opening is formed in the rewiring layer, and at least part of the first dielectric layer is exposed out of the first metal layer opening; the second dielectric layer is arranged on the rewiring layer; it is characterized in that the preparation method is characterized in that,
the surface of the first dielectric layer is also provided with a first groove, the first groove is communicated with the first metal layer opening, and the second dielectric layer is connected with the first dielectric layer through the first metal layer opening and the first groove.
2. The package on package structure of claim 1, wherein the width of the first recess is not less than the width of the first metal layer opening, and the depth of the first recess exceeds 0.3 um.
3. The package on package structure of claim 2, wherein a width of the first recess is equal to a width of the first metal layer opening.
4. The package on package structure of claim 1, wherein the second dielectric layer further defines a second dielectric layer opening, the second dielectric layer opening exposing at least a portion of the redistribution layer; the packaging structure further comprises a solder ball, and the solder ball is electrically connected with the redistribution layer through the second dielectric layer opening.
5. The package-on-package structure of claim 4, further comprising an under-ball metal layer disposed between the solder balls and the redistribution layer, the under-ball metal layer electrically connecting the solder balls and the redistribution layer through the second dielectric layer openings, a portion of the side surfaces of the under-ball metal layer and the surface of the redistribution layer enclosing the second metal layer openings; the surface of the second dielectric layer is also provided with a second groove.
6. The package on package structure of claim 5, wherein the height of the bottom surface of the second recess differs by more than 0.3um from the height of the upper side of the second metal layer opening.
7. The package on package structure of claim 5, wherein the second recess is in communication with or at least partially overlaps the second metal layer opening.
8. The package-on-package structure of claim 5, further comprising a third dielectric layer disposed over the second dielectric layer, the third dielectric layer encapsulating the UBM layer.
9. A method of packaging on a package, the method comprising:
arranging a first dielectric layer on the active surface of a wafer or a chip;
arranging a rewiring layer on the first dielectric layer, and forming a first metal layer opening on the rewiring layer to expose at least part of the first dielectric layer;
forming a first groove on the surface of the first dielectric layer, so that the first groove is communicated with the first metal layer opening;
and arranging a second dielectric layer on the rewiring layer, so that the second dielectric layer is connected with the first dielectric layer through the first metal layer opening and the first groove.
10. The package-on-package method according to claim 9, wherein the step of forming the first recess in the surface of the first dielectric layer specifically comprises:
the width of the first groove is not less than the width of the opening of the first metal layer, and the depth of the first groove exceeds 0.3 um.
11. The package-on-package method according to claim 9, wherein after the step of "disposing a second dielectric layer on the redistribution layer", the method further comprises:
forming a second dielectric layer opening on the second dielectric layer, so that the second dielectric layer opening exposes at least part of the rewiring layer;
and implanting a solder ball into the opening of the second dielectric layer so that the solder ball is electrically connected with the redistribution layer.
12. The package-on-package method of claim 11, wherein the step of implanting solder balls in the openings of the second dielectric layer so that the solder balls are electrically connected to the redistribution layer comprises:
and arranging an under-ball metal layer between the solder ball and the redistribution layer, so that the solder ball is electrically connected with the redistribution layer through the second dielectric layer opening by the under-ball metal layer, and a second metal layer opening is formed by enclosing part of the side surface of the under-ball metal layer and the surface of the redistribution layer.
13. The package-on-package method according to claim 12, wherein after the step of providing an under-ball metal layer between the solder ball and the redistribution layer, the method further comprises:
and arranging a second groove on the surface of the second dielectric layer, so that the height difference between the bottom surface of the second groove and the upper side surface of the second metal layer opening is more than 0.3um, and the second groove is communicated with or at least partially overlapped with the second metal layer opening.
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| CN201911264599.9A CN112951791A (en) | 2019-12-11 | 2019-12-11 | Stacked package structure and packaging method |
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| CN201911264599.9A CN112951791A (en) | 2019-12-11 | 2019-12-11 | Stacked package structure and packaging method |
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| WO2023051565A1 (en) * | 2021-09-30 | 2023-04-06 | 华为技术有限公司 | Power semiconductor device, preparation method therefor, and electronic apparatus |
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