CN107768343A - High reliability RDL stacks open-celled structure - Google Patents

High reliability RDL stacks open-celled structure Download PDF

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Publication number
CN107768343A
CN107768343A CN201710907481.8A CN201710907481A CN107768343A CN 107768343 A CN107768343 A CN 107768343A CN 201710907481 A CN201710907481 A CN 201710907481A CN 107768343 A CN107768343 A CN 107768343A
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CN
China
Prior art keywords
layer
metal wiring
dielectric layer
polymer dielectric
wiring layer
Prior art date
Application number
CN201710907481.8A
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Chinese (zh)
Inventor
林耀剑
Original Assignee
江苏长电科技股份有限公司
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Publication date
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Priority to CN201710907481.8A priority Critical patent/CN107768343A/en
Publication of CN107768343A publication Critical patent/CN107768343A/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Abstract

The present invention relates to a kind of high reliability RDL to stack open-celled structure, and it includes silicon substrate(1), chip pad(2)And passivation layer(3), the passivation layer(3)And chip pad(2)It is coated with the first polymer dielectric layer(4), first polymer dielectric layer(4)On be provided with the first metal wiring layer(6), first metal wiring layer(6)It is coated with the second polymer dielectric layer(7), second polymer dielectric layer(7)On be provided with the second metal wiring layer(9), second metal wiring layer(9)It is coated with the 3rd polymer dielectric layer(10), the 3rd polymer dielectric layer(10)On be provided with tin ball(11).A kind of high reliability RDL of the present invention stacks open-celled structure, its second polymer dielectric layer under the second metal wiring layer opens stress buffer groove, dispersive stress is concentrated, to reduce the interfacial stress in chip pad and the first metal wiring layer, so as to improve the reliability of device.

Description

High reliability RDL stacks open-celled structure

Technical field

The present invention relates to a kind of high reliability RDL to stack open-celled structure, belongs to technical field of semiconductor encapsulation.

Background technology

In order to meet the certain stacking open-celled structure design of current power requirement wafer-level packaging needs.It is as shown in Figure 1 The solder bumps structure of high power wafer-level packaging, chip pad 2 is formed by metallic aluminium on silicon substrate 1;Form passivation layer SiO2/Si3N4 or PI(polymer insulation)To expose the part of each chip pad 2 on silicon substrate 1, simultaneously Protect the remainder of silicon substrate 1;In passivation layer SiO2/Si3N4 or PI(polymer insulation)Top forms first Polymer dielectric layer 4, the first heavy cloth is then formed above the chip pad 2 of the part of the first polymer dielectric layer 4 and exposure Line(RDL)Pattern 6(It is redistributed from the electric signal for combining weld pad to tin ball), second is formed on the first RDL patterns 6 of part Polymer dielectric layer 7, while leave the first RDL patterns 6 of exposed part;In the part of the second polymer dielectric layer 7 and cruelly Second is formed on first RDL patterns 6 of dew to reroute(RDL)Pattern 9, tin ball 11 is finally formed above the 2nd RDL patterns, its The 3rd polymer dielectric layer 10 is formed on remaining expose portion.

But this is stacked at open-celled structure metal line aggregation one, due to rerouting the hot swollen of metal level and polymer dielectric layer Swollen coefficient is different, and chip pad can be made to reroute the interface of pattern with first and produce larger stress, especially to smaller perforate Design is such as<The design of=25 micron diameters, interface can produce separation or crackle and cause reliability failures.

The content of the invention

The technical problems to be solved by the invention are to provide a kind of high reliability RDL for above-mentioned prior art to stack perforate Structure, its second polymer dielectric layer under the second metal wiring layer are opened stress buffer groove or hole, dispersive stress, existed with reducing Chip pad and the interfacial stress of the first metal wiring layer, so as to improve the reliability of device.

Technical scheme is used by the present invention solves the above problems:A kind of high reliability RDL stacks open-celled structure, and it is wrapped Silicon substrate is included, chip pad and passivation layer are provided with the silicon substrate, the passivation layer is arranged at around chip pad, described Passivation layer and chip pad are coated with the first polymer dielectric layer, and first polymer dielectric layer is set in chip pad position It is equipped with the first perforate, is provided with the first metal wiring layer on first polymer dielectric layer and in the first perforate, described first Metal wiring layer is electrically connected with chip pad, and first metal wiring layer is coated with the second polymer dielectric layer, described Second polymer dielectric layer is provided with the second perforate in the first metal wiring layer position, and second polymer dielectric layer is first Metal wiring layer peripheral position is provided with the first dashpot, on second polymer dielectric layer, slow with first in the second perforate It is provided with the second metal wiring layer in jet-bedding, second metal wiring layer and the first metal wiring layer are electrically connected with, and described the Two metal wiring layers are coated with the 3rd polymer dielectric layer, and the 3rd polymer dielectric layer is in the second metal wiring layer position The 3rd perforate is offered, the 3rd tapping is provided with tin ball.

First dashpot is a complete annular groove or incomplete annular groove.

First dashpot is substituted using the multiple cushion holes arranged in a ring.

First polymer dielectric layer is provided with the 3rd dashpot below the first metal wiring layer.

The first dashpot is provided with above first metal wiring layer, the is provided with below first metal wiring layer Three dashpots.

A kind of high reliability RDL stacks open-celled structure, and it includes silicon substrate, chip pad and passivation are provided with the silicon substrate Layer, the passivation layer are arranged at around chip pad, and the passivation layer and chip pad are coated with the first polymer dielectric layer, First polymer dielectric layer is provided with the first perforate in chip pad position, on first polymer dielectric layer and first The first metal wiring layer is provided with perforate, first metal wiring layer is electrically connected with chip pad, first metal Wiring layer is coated with the second polymer dielectric layer, and second polymer dielectric layer is provided with the first metal wiring layer position Second perforate, second polymer dielectric layer are provided with the first dashpot in the first metal wiring layer peripheral position, and described The second metal wiring layer, second hardware cloth are provided with two polymer dielectric layers, in the second perforate and in the first dashpot Line layer and the first metal wiring layer are electrically connected with, and second metal wiring layer is coated with the 3rd polymer dielectric layer, described The second dashpot is provided with the outside of the 3rd polymer dielectric layer above first perforate, on the 3rd polymer dielectric layer and the Ball lower metal layer is provided with two dashpots, tin ball is provided with the ball lower metal layer.

The passivation layer uses SiN, SiO or SOG.

The material of first polymer dielectric layer, the second polymer dielectric layer and the 3rd polymer dielectric layer using BCB, Polyimide, PBO, other polymer insulation films or polymer composite thin film.

The material of first metal wiring layer and the second metal wiring layer uses Cu, Al, Cr, NiV, Ti or TiW.

Compared with prior art, the advantage of the invention is that:

1st, second in the first polymer dielectric layer of the present invention under the first metal wiring layer or under the second metal wiring layer is high Stress buffer groove or hole are set in molecular dielectric layer, and dispersive stress is concentrated, to reduce in chip pad and the first metal wiring layer Interfacial stress, so as to improve the reliability of device;

2nd, the present invention is having UMB(Ball lower metal layer)Design under, below UMB, directly over the first polymer dielectric layer perforate The polymer dielectric layer of member-retaining portion the 3rd, cumulative stress can be reduced using the flexibility of high polymer material.

Brief description of the drawings

Fig. 1 is the schematic diagram of the solder bumps structure of existing high power wafer-level packaging.

Fig. 2 is the schematic diagram that a kind of high reliability RDL of the present invention stacks open-celled structure embodiment 1.

Metal wiring layer and the top view of several embodiments of dashpot in Fig. 3 ~ Fig. 6.

Fig. 7 is the schematic diagram that a kind of high reliability RDL of the present invention stacks open-celled structure embodiment 2.

Fig. 8 ~ Figure 12 is the process flow diagram that a kind of high reliability RDL of the present invention stacks open-celled structure embodiment 2

Figure 13 is the schematic diagram that a kind of high reliability RDL of the present invention stacks open-celled structure embodiment 3.

Figure 14 is the schematic diagram that a kind of high reliability RDL of the present invention stacks open-celled structure embodiment 4.

Wherein:

Silicon substrate 1

Chip pad 2

Passivation layer 3

First polymer dielectric layer 4

First perforate 5

First metal wiring layer 6

Second polymer dielectric layer 7

Second perforate 8

Second metal wiring layer 9

3rd polymer dielectric layer 10

Tin ball 11

First dashpot 12

3rd perforate 13

Ball lower metal layer 14

Second dashpot 15

3rd dashpot 16.

Embodiment

The present invention is described in further detail below in conjunction with accompanying drawing embodiment.

Embodiment 1:

As shown in Fig. 2 a kind of high reliability RDL in the present embodiment stacks open-celled structure, it includes silicon substrate 1, the silicon lining Chip pad 2 and passivation layer 3 are provided with bottom 1, the passivation layer 3 is arranged at around chip pad 2, the passivation layer 3 and core Piece weld pad 2 is coated with the first polymer dielectric layer 4, and first polymer dielectric layer 4 is provided with the position of chip pad 2 One perforate 5, the first metal wiring layer 6, first gold medal are provided with first polymer dielectric layer 4 and in the first perforate 5 Category wiring layer 6 is electrically connected with chip pad 2, and first metal wiring layer 6 is coated with the second polymer dielectric layer 7, institute State the second polymer dielectric layer 7 and the second perforate 8, second polymer dielectric layer 7 are provided with the position of the first metal wiring layer 6 The peripheral position of first metal wiring layer 6 is provided with the first dashpot 12, on second polymer dielectric layer 7, the second perforate 8 The second metal wiring layer 9, the metal wiring layer 6 of the second metal wiring layer 9 and first are provided with interior and the first dashpot 12 It is electrically connected with, second metal wiring layer 9 is coated with the 3rd polymer dielectric layer 10, the 3rd polymer dielectric layer 10 The 3rd perforate 13 is offered in the position of the second metal wiring layer 9, tin ball 11 is provided with the 3rd perforate 13;

As shown in Fig. 3 ~ Fig. 5, first dashpot 12 can be a complete annular groove or incomplete annular Groove;

As shown in fig. 6, first dashpot 12 can also use the multiple cushion holes arranged in a ring to substitute.

Embodiment 2:

Referring to Fig. 7, a kind of high reliability RDL in the present embodiment stacks open-celled structure, and it includes silicon substrate 1, the silicon substrate 1 On be provided with chip pad 2 and passivation layer 3, the passivation layer 3 is arranged at around chip pad 2, the passivation layer 3 and chip weldering Pad 2 is coated with the first polymer dielectric layer 4, and first polymer dielectric layer 4 is provided with first in the position of chip pad 2 and opened Hole 5, the first metal wiring layer 6, first hardware cloth are provided with first polymer dielectric layer 4 and in the first perforate 5 Line layer 6 is electrically connected with chip pad 2, and first metal wiring layer 6 is coated with the second polymer dielectric layer 7, and described Two polymer dielectric layers 7 are provided with the second perforate 8 in the position of the first metal wiring layer 6, and second polymer dielectric layer 7 is The peripheral position of one metal wiring layer 6 is provided with the first dashpot 12, on second polymer dielectric layer 7, in the second perforate 8 and The second metal wiring layer 9 is provided with first dashpot 12, second metal wiring layer 9 and the first metal wiring layer 6 are electrical Connection, second metal wiring layer 9 are coated with the 3rd polymer dielectric layer 10, and the 3rd of the top of the first perforate 5 is high The outside of molecular dielectric layer 10 is provided with the second dashpot 15, is set on the 3rd polymer dielectric layer 10 and in the second dashpot 15 Ball lower metal layer 14 is equipped with, tin ball 11 is provided with the ball lower metal layer 14;

Its processing step is as follows:

Step 1: referring to Fig. 8, passivation layer and chip pad are formed on wafer or silicon substrate, on passivation layer and chip pad The first polymer dielectric layer is prepared, is welded by exposure imaging to remove the polymer dielectric layer of part first with expose portion chip Pad, the first metal wiring layer is formed by mask deposition metal, the first metal wiring layer is electrically connected with chip pad;

Passivation layer can be made up of any dielectric material as known in the art, such as silicon nitride(SiN), silica(SiO)Or SOG, PI(polymer insulation)Deng insulating polymeric material;

Chip pad can be made of an electrically conducting material, such as metal and metal alloy;

First polymer dielectric layer is made up of dielectric polymer material, such as BCB, polyimides(PI)Or epoxy molding compounds Composite(EMC);

Step 2: referring to Fig. 9, the second polymer dielectric layer is prepared on the first polymer dielectric layer and the first metal wiring layer, The polymer dielectric layer of part second is removed with the metal wiring layer of expose portion first and the high score of part first by exposure imaging Sub- dielectric layer;

Step 3: referring to Figure 10, the second wiring metal is formed by covering deposited metal layer on the second polymer dielectric layer Layer, the part that the second interconnection metal layer does not need metal level is generally then removed by mask and etching;

Second interconnection metal layer can use any conductive material, such as metal and metal alloy, including Cu, Al, Cr, NiV and Ti;

Step 4: referring to Figure 11, prepare the 3rd polymer dielectric layer and cover the second metal wiring layer, then carry out photoetching and solidification The follow-up part for needing to plant ball of exposure, retains portion of the 3rd polymer dielectric layer directly over the first polymer dielectric layer perforate Point;

Step 5: referring to Figure 12, mask deposition forms UBM on the 3rd polymer dielectric layer(Ball lower metal layer), and in UBM Upper implantation tin ball;

The material of ball lower metal layer can be Al/NiV/Cu, Ti/NiV/Cu, Ti/Cu, TiW/Cu or Ti/Cu/Ni etc..

Embodiment 3:

Referring to Figure 13, a kind of high reliability RDL in the present embodiment stacks open-celled structure, and it includes silicon substrate 1, the silicon substrate Chip pad 2 and passivation layer 3 are provided with 1, the passivation layer 3 is arranged at around chip pad 2, the passivation layer 3 and chip Weld pad 2 is coated with the first polymer dielectric layer 4, and first polymer dielectric layer 4 is provided with first in the position of chip pad 2 Perforate 5, first polymer dielectric layer 4 are provided with the 3rd dashpot 16 in the position of passivation layer 3.First polymer dielectric Be provided with the first metal wiring layer 6 on layer 4, in the first perforate 5 and in the 3rd dashpot 16, first metal wiring layer 6 with Chip pad 2 is electrically connected with, and first metal wiring layer 6 is coated with the second polymer dielectric layer 7, second macromolecule Dielectric layer 7 is provided with the second perforate 8 in the position of the first metal wiring layer 6, on second polymer dielectric layer 7 and the second perforate The second metal wiring layer 9 is provided with 8, second metal wiring layer 9 is electrically connected with the first metal wiring layer 6, and described Two metal wiring layers 9 are coated with the 3rd polymer dielectric layer 10.3rd polymer dielectric layer 10 is in the second metal line 9 position of layer offer the 3rd perforate 13, and tin ball 11 is provided with the 3rd perforate 13;

As shown in figure 13, the dashpot 16 of the first perforate 5 and the 3rd is under the same conductive gasket of the first metal wiring layer 6, The shape of the conductive gasket can be circular, square or other irregular shapes, and the 3rd dashpot 16 and the first perforate 5 exist Symmetrically and evenly arranged under same conductive gasket, the 3rd dashpot 16 can be cylinder, cuboid, cone or other not advise Then shape.

Embodiment 4:

Referring to Figure 14, a kind of high reliability RDL in the present embodiment stacks open-celled structure, and it includes silicon substrate 1, the silicon substrate Chip pad 2 and passivation layer 3 are provided with 1, the passivation layer 3 is arranged at around chip pad 2, the passivation layer 3 and chip Weld pad 2 is coated with the first polymer dielectric layer 4, and first polymer dielectric layer 4 is provided with first in the position of chip pad 2 Perforate 5, first polymer dielectric layer 4 are provided with the 3rd dashpot 16 in the position of passivation layer 3.First polymer dielectric Be provided with the first metal wiring layer 6 on layer 4, in the first perforate 5 and in the 3rd dashpot 16, first metal wiring layer 6 with Chip pad 2 is electrically connected with, and first metal wiring layer 6 is coated with the second polymer dielectric layer 7, second macromolecule Dielectric layer 7 is provided with the second perforate 8 and the first dashpot 12, second polymer dielectric in the position of the first metal wiring layer 6 Be provided with the second metal wiring layer 9 on layer 7, in the second perforate 8 and in the first dashpot 12, second metal wiring layer 9 with First metal wiring layer 6 is electrically connected with, and second metal wiring layer 9 is coated with the 3rd polymer dielectric layer 10.Described Three polymer dielectric layers 10 offer the 3rd perforate 13 in the position of the second metal wiring layer 9, are provided with the 3rd perforate 13 Tin ball 11.

In addition to the implementation, present invention additionally comprises have other embodiment, all use equivalent transformation or equivalent replacement modes The technical scheme of formation, it all should fall within the scope of the hereto appended claims.

Claims (10)

1. a kind of high reliability RDL stacks open-celled structure, it is characterised in that:It includes silicon substrate(1), the silicon substrate(1)On It is provided with chip pad(2)And passivation layer(3), the passivation layer(3)It is arranged at chip pad(2)Around, the passivation layer(3) And chip pad(2)It is coated with the first polymer dielectric layer(4), first polymer dielectric layer(4)In chip pad(2) Position is provided with the first perforate(5), first polymer dielectric layer(4)Upper and the first perforate(5)Inside it is provided with the first metal Wiring layer(6), first metal wiring layer(6)With chip pad(2)It is electrically connected with, first metal wiring layer(6)Outside It is coated with the second polymer dielectric layer(7), second polymer dielectric layer(7)In the first metal wiring layer(6)Position is set There is the second perforate(8), second polymer dielectric layer(7)In the first metal wiring layer(6)It is slow that peripheral position is provided with first Jet-bedding(12), second polymer dielectric layer(7)Upper, the second perforate(8)Interior and the first dashpot(12)Inside it is provided with second Metal wiring layer(9), second metal wiring layer(9)With the first metal wiring layer(6)It is electrically connected with, second hardware cloth Line layer(9)It is coated with the 3rd polymer dielectric layer(10), the 3rd polymer dielectric layer(10)In the second metal wiring layer (9)Position offers the 3rd perforate(13), the 3rd perforate(13)Place is provided with tin ball(11).
2. a kind of high reliability RDL according to claim 1 stacks open-celled structure, it is characterised in that:First buffering Groove(12)It is a complete annular groove or incomplete annular groove.
3. a kind of high reliability RDL according to claim 1 stacks open-celled structure, it is characterised in that:First buffering Groove(12)Substituted using the multiple cushion holes arranged in a ring.
4. a kind of high reliability RDL according to claim 1 stacks open-celled structure, it is characterised in that:First high score Sub- dielectric layer(4)In the first metal wiring layer(6)Lower section is provided with the 3rd dashpot(16).
5. a kind of high reliability RDL according to claim 1 stacks open-celled structure, it is characterised in that:First metal Wiring layer(6)Top is provided with the first dashpot(12), lower section is provided with the 3rd dashpot(16).
6. a kind of high reliability RDL according to claim 4 stacks open-celled structure, it is characterised in that:First perforate (5)With the 3rd dashpot(16)In the first metal wiring layer(6)Lower section symmetry arrangement.
7. a kind of high reliability RDL stacks open-celled structure, it is characterised in that:It includes silicon substrate(1), the silicon substrate(1)On It is provided with chip pad(2)And passivation layer(3), the passivation layer(3)It is arranged at chip pad(2)Around, the passivation layer(3) And chip pad(2)It is coated with the first polymer dielectric layer(4), first polymer dielectric layer(4)In chip pad(2) Position is provided with the first perforate(5), first polymer dielectric layer(4)Upper and the first perforate(5)Inside it is provided with the first metal Wiring layer(6), first metal wiring layer(6)With chip pad(2)It is electrically connected with, first metal wiring layer(6)Outside It is coated with the second polymer dielectric layer(7), second polymer dielectric layer(7)In the first metal wiring layer(6)Position is set There is the second perforate(8), second polymer dielectric layer(7)In the first metal wiring layer(6)It is slow that peripheral position is provided with first Jet-bedding(12), second polymer dielectric layer(7)Upper, the second perforate(8)Interior and the first dashpot(12)Inside it is provided with second Metal wiring layer(9), second metal wiring layer(9)With the first metal wiring layer(6)It is electrically connected with, second hardware cloth Line layer(9)It is coated with the 3rd polymer dielectric layer(10), first perforate(5)3rd polymer dielectric layer of top(10) Outside is provided with the second dashpot(15), the 3rd polymer dielectric layer(10)Upper and the second dashpot(15)Inside it is provided with ball Lower metal layer(14), the ball lower metal layer(14)On be provided with tin ball(11).
8. a kind of high reliability RDL according to claim 1 or 7 stacks open-celled structure, it is characterised in that:The passivation layer (3)Using SiN, SiO, SiON, SOG or insulating polymeric material.
9. a kind of high reliability RDL according to claim 1 or 7 stacks open-celled structure, it is characterised in that:Described first is high Molecular dielectric layer(4), the second polymer dielectric layer(7)With the 3rd polymer dielectric layer(10)Material using BCB, Polyimide, PBO, polymer insulation film or polymer composite thin film.
10. a kind of high reliability RDL according to claim 1 or 7 stacks open-celled structure, it is characterised in that:First metal Wiring layer(6)With the second metal wiring layer(9)Material use Cu, Al, Cr, NiV, Ti or TiW.
CN201710907481.8A 2017-09-29 2017-09-29 High reliability RDL stacks open-celled structure CN107768343A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070001301A1 (en) * 2005-06-08 2007-01-04 Yongqian Wang Under bump metallization design to reduce dielectric layer delamination
US20070075423A1 (en) * 2005-09-30 2007-04-05 Siliconware Precision Industries Co., Ltd. Semiconductor element with conductive bumps and fabrication method thereof
CN101882608A (en) * 2009-05-08 2010-11-10 台湾积体电路制造股份有限公司 Bump pad structure and method for manufacturing the same
CN103681611A (en) * 2012-09-14 2014-03-26 台湾积体电路制造股份有限公司 Post passivation interconnect structure and method for forming the same
US20170162540A1 (en) * 2015-12-03 2017-06-08 Mediatek Inc. Wafer-level chip-scale package with redistribution layer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070001301A1 (en) * 2005-06-08 2007-01-04 Yongqian Wang Under bump metallization design to reduce dielectric layer delamination
US20070075423A1 (en) * 2005-09-30 2007-04-05 Siliconware Precision Industries Co., Ltd. Semiconductor element with conductive bumps and fabrication method thereof
CN101882608A (en) * 2009-05-08 2010-11-10 台湾积体电路制造股份有限公司 Bump pad structure and method for manufacturing the same
CN103681611A (en) * 2012-09-14 2014-03-26 台湾积体电路制造股份有限公司 Post passivation interconnect structure and method for forming the same
US20170162540A1 (en) * 2015-12-03 2017-06-08 Mediatek Inc. Wafer-level chip-scale package with redistribution layer

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