CN112951771A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112951771A CN112951771A CN201911255015.1A CN201911255015A CN112951771A CN 112951771 A CN112951771 A CN 112951771A CN 201911255015 A CN201911255015 A CN 201911255015A CN 112951771 A CN112951771 A CN 112951771A
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- trench
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
Abstract
The application discloses a semiconductor structure and a forming method thereof, the semiconductor structure comprises a semiconductor substrate, a first groove structure and a second groove structure, wherein the first groove structure is formed in the semiconductor substrate and used for forming a groove type capacitor, and the second groove structure is formed in the semiconductor substrate and arranged around the first groove structure. The second trench structure is used for preventing the first trench structure from being mechanically damaged when the semiconductor substrate is cut. The first trench structure and the second trench structure are formed in the same etching process without adding additional process steps. The semiconductor structure and the forming method thereof can prevent the substrate from being mechanically damaged in the chip cutting process under the condition of not increasing additional process steps.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In order to prevent moisture or dust from entering the chip during semiconductor manufacturing, a sealing ring is typically provided on the substrate around the chip. Grounding the seal ring can also be an off-chip electrostatic disturbance.
However, since the seal ring is usually disposed above the substrate, it cannot prevent external stress from acting on the substrate during the chip dicing process, so as to cause mechanical damage to the semiconductor structure located in the substrate.
Therefore, a semiconductor structure and a method for forming the same capable of preventing a substrate from being mechanically damaged during a chip dicing process are needed.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present application aims to provide a semiconductor structure and a method for forming the same, which can prevent a substrate from being mechanically damaged during a chip cutting process without adding additional process steps.
One aspect of the present application provides a semiconductor structure including a semiconductor substrate, a first trench structure formed in the semiconductor substrate for forming a trench capacitor, and a second trench structure formed in the semiconductor substrate and disposed around the first trench structure.
In some embodiments, the second trench structure comprises one or more trenches, the plurality of trenches are disposed around each other, and at least one of the plurality of trenches is continuous.
In some embodiments, the second groove structure comprises one or more structurally discontinuous grooves, the plurality of grooves being disposed around each other.
In some embodiments, the plurality of structurally discontinuous grooves each comprise indentations that are arranged in an alternating manner with respect to each other.
In some embodiments, among the plurality of structurally discontinuous trenches, a pitch of adjacent trenches is 2 μm to 5 μm.
In some embodiments, each trench in the second trench structure has a depth of 25 μm to 35 μm.
In some embodiments, each trench in the second trench structure has a width of 0.8 μm to 1.2 μm.
In some embodiments, the second trench structure is spaced apart from the first trench structure by 8 μm to 12 μm.
In some embodiments, the semiconductor structure further includes a scribe line formed in the semiconductor substrate and surrounding the second trench structure, and the second trench structure is spaced apart from the scribe line by 8 μm to 12 μm.
One aspect of the present application provides a method of forming a semiconductor structure, comprising: providing a semiconductor substrate; and etching the semiconductor substrate, and simultaneously forming a first groove structure and a second groove structure, wherein the first groove structure is used for forming a groove type capacitor, and the second groove structure is arranged around the first groove structure.
In some embodiments, the second trench structure comprises one or more trenches, the plurality of trenches are disposed around each other, and at least one of the plurality of trenches is continuous.
In some embodiments, the second groove structure comprises one or more structurally discontinuous grooves, the plurality of grooves being disposed around each other.
In some embodiments, the plurality of structurally discontinuous grooves each comprise indentations that are arranged in an alternating manner with respect to each other.
In some embodiments, among the plurality of structurally discontinuous trenches, a pitch of adjacent trenches is 2 μm to 5 μm.
In some embodiments, the second trench structure is spaced apart from the first trench structure by 8 μm to 12 μm.
In some embodiments, each trench in the second trench structure has a depth of 25 μm to 35 μm.
In some embodiments, each trench in the second trench structure has a width of 0.8 μm to 1.2 μm.
In some embodiments, the method for forming a semiconductor structure further includes: and etching the semiconductor substrate to form a cutting channel, wherein the cutting channel is arranged around the second groove structure, and the distance between the second groove structure and the cutting channel is 8-12 μm.
The semiconductor structure and the forming method thereof realize the technical effect of preventing the substrate from being mechanically damaged during chip cutting at the minimum cost (namely, without adding any new process step) by forming the groove for blocking external mechanical damage at the same time of forming the groove for arranging the capacitor.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present disclosure, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
FIG. 1 is a schematic diagram of a semiconductor structure;
FIG. 2 is a flow chart of a method of forming a semiconductor structure according to an embodiment of the present application;
fig. 3 to 6 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present disclosure;
FIG. 7a is a schematic view of a trench structure of a semiconductor structure according to an embodiment of the present application;
FIG. 7b is a cross-sectional view taken along line A-A of FIG. 7a of an embodiment of the present application;
FIG. 7c is a cross-sectional view taken along line A-A of FIG. 7a according to another embodiment of the present application;
FIG. 8a is a schematic view of a trench structure of a semiconductor structure according to an embodiment of the present application;
FIG. 8B is a cross-sectional view taken along line B-B of FIG. 8a according to an embodiment of the present application;
FIG. 8c is a cross-sectional view taken along line B-B of FIG. 8a according to another embodiment of the present application.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various local modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Thus, the present disclosure is not to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
Unless otherwise indicated, or as may be apparent from the context of use, any terms, abbreviations, acronyms, or scientific symbols and notations used herein are to be given their ordinary meaning in the technical disciplines to which the invention most closely pertains. The following terms, abbreviations and acronyms may be used throughout the description presented herein and shall generally be given the following meanings unless otherwise contradicted or elaborated upon by the description set forth herein.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
As shown in fig. 1, a semiconductor structure includes a semiconductor substrate 10, a trench 20 formed in the semiconductor substrate 10, a capacitor 30 formed in the trench 20, a contact layer 50 connecting the capacitor, a metal interconnect layer 60 connecting the contact layer 50, a seal ring 40 located over the semiconductor substrate 10.
In such a semiconductor structure, although the seal ring 40 is provided to ensure that the devices above the substrate are not externally disturbed by moisture, dust, static electricity, etc., the seal ring 40 cannot prevent external stress from being applied into the substrate during the chip dicing process. For example, cracks 70 due to external stress may extend into the substrate, thereby causing damage to the capacitor 30 located within the substrate.
In order to solve the above problem, an embodiment of the present invention provides a method for forming a semiconductor structure, as shown in fig. 2, including the following steps:
step S102: providing a semiconductor substrate;
step S104: and etching the semiconductor substrate, and simultaneously forming a first groove structure and a second groove structure, wherein the first groove structure is used for forming a groove type capacitor, and the second groove structure is arranged around the first groove structure.
The above steps will be described in detail with reference to fig. 3 to 6. It should be noted that methods that perform the above and below steps in other orders also fall within the scope of the present disclosure.
As shown in fig. 3, a semiconductor substrate 100 is provided.
The material of the semiconductor substrate 100 may be silicon (Si), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other materials, such as a III-V compound such as gallium arsenide. The material of the semiconductor substrate 100 may be one of single crystal silicon, polycrystalline silicon, and amorphous silicon. The material of the semiconductor substrate 100 may be a silicon germanium compound. The semiconductor substrate 100 may also be a silicon-on-insulator structure or a silicon-on-epitaxial layer structure. In the semiconductor substrate 100, a semiconductor device (not shown), such as a metal oxide semiconductor device having a gate, a source, and a drain, may be formed.
As shown in fig. 4, the semiconductor substrate 100 is etched while forming the first trench structure 210 and the second trench structure 220.
The first trench structure 210 may include a plurality of trenches, each of the plurality of trenches having a depth of 25 μm to 35 μm and a width of 0.8 μm to 2.0 μm, e.g., 1.0 μm, 1.2 μm, 1.5 μm, 1.8 μm, etc. The second trench structure 220 includes one or more trenches, each of the one or more trenches having a depth D of 25 μm to 35 μm and a width W of 0.8 μm to 1.2 μm. The first trench structure 210 and the second trench structure 220 have a distance of 8 μm to 12 μm. The second trench structure 220 is configured to protect the first trench structure 210 from mechanical damage caused by external stress when the semiconductor substrate 100 is cut. Specifically, when the semiconductor chip is cut along the scribe line, the cutting force may cause cracks to occur in the semiconductor substrate 100 (as shown in fig. 1), and the presence of the second trench structure 220 can prevent the cracks from extending further to the first trench structure 210, thereby ensuring the security of the devices in the semiconductor substrate 100.
In the present embodiment, the first trench structure 210 and the second trench structure 220 are formed by the same etching process (e.g., dry etching or wet etching), so that the technical effect of protecting the semiconductor substrate can be achieved with minimal cost (i.e., without adding any new process step).
As shown in fig. 5, in some embodiments, the method for forming a semiconductor structure of the present application may further include: a trench capacitor 300 is formed in the first trench structure 210.
The trench capacitor 300 includes a lower electrode 320, an inter-electrode layer 330, and an upper electrode 340.
The specific steps for forming the trench capacitor 300 in the first trench structure 210 are as follows.
First, the lower electrode 320 is formed on the bottom wall and the sidewall of each trench in the first trench structure 210 and the semiconductor substrate 100. The lower electrode 320 may include a first metal nitride layer, a metal layer and a second metal nitride layer, which are sequentially stacked, wherein the first metal nitride layer may be titanium nitride or tantalum nitride, the metal layer may be metal aluminum or metal copper, and the second metal nitride layer may be titanium nitride or tantalum nitride. Subsequently, an inter-electrode layer 330 is formed on the lower electrode 320. The material of the interlayer 330 may be silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric materials. Finally, an upper electrode 340 is formed on the inter-electrode layer 330. The material of the upper electrode 340 may be the same as or similar to the lower electrode 320. The lower electrode 320, the inter-electrode layer 330, and the upper electrode 340 may all be deposited by Atomic Layer Deposition (ALD) techniques.
In some embodiments, the multilayer trench capacitor 300 may be stacked in the same manner in each trench in the first trench structure 210.
As shown in fig. 6, in some embodiments, the method for forming a semiconductor structure of the present application may further include: forming a contact layer 500 over the trench capacitor 300; forming a metal interconnection layer 600 on the contact layer 500; and a seal ring 400 is formed on the second trench structure 220.
In some embodiments, the method for forming a semiconductor structure of the present application may further include: the semiconductor substrate 100 is etched to form a cutting street (not shown), wherein the cutting street surrounds the second trench structure 220, and the second trench structure 220 and the cutting street are spaced apart by 8 μm to 12 μm.
Fig. 7a is a schematic view of a trench structure of a semiconductor structure according to an embodiment of the present application, and fig. 7b is a cross-sectional view taken along line a-a in fig. 7a according to an embodiment of the present application.
In the embodiment shown in fig. 7a and 7b, the second trench structure 220 comprises only one trench, which is structurally continuous, i.e. has a continuous ring-shaped structure (viewed in a direction perpendicular to the semiconductor substrate 100). In this application, a structure continuous refers to a structure without any break or gap. When the structure of the trench is continuous, it is able to provide all-directional protection for the first trench structure 210 located in the semiconductor substrate 100. In some embodiments, the second trench structure 220 may include a plurality of trenches, at least one structure of which is continuous. In some embodiments, a plurality of grooves may be disposed to surround each other to obtain a better depth protection effect. In some embodiments, the protective effect may also be improved by increasing the width and/or depth of the trench.
FIG. 7c is a cross-sectional view taken along line A-A in FIG. 7a according to another embodiment of the present application.
In the embodiment shown in fig. 7c, the second trench structure 220 comprises only one trench, the structure of which is discontinuous. As shown, a break or gap 225 is present in the annular cross-section of the groove. In this application, structural discontinuity refers to a structure in which one or more discontinuities or gaps exist. When the density of the first trench structures 210 is not large, it can provide sufficient mechanical damage resistance to the first trench structures 210 located in the semiconductor substrate 100 even if the trenches of the second trench structure 220 form a discontinuous ring shape. In some embodiments, the second trench structure 220 may comprise one or more structurally discontinuous trenches. In some embodiments, the second trench structure 220 may include both structurally continuous trenches and structurally discontinuous trenches. Although the structurally discontinuous grooves in fig. 7c are formed from four rectangular sections, it should be noted that one or more sections of the structurally discontinuous grooves may be square, rectangular, circular, oval, diamond, triangular, trapezoidal, wavy, pentagonal, hexagonal, other polygonal shapes, and/or combinations thereof.
Fig. 8a is a schematic view of a trench structure of a semiconductor structure according to an embodiment of the present application, and fig. 8B is a cross-sectional view taken along line B-B in fig. 8a according to an embodiment of the present application.
In the embodiment shown in fig. 8a and 8b, the second trench structure 220 comprises two first trenches 221 and a second trench 222 arranged around the first trenches 221. The first trench 221 and the second trench 222 are structurally continuous, so that dual protection can be provided for the first trench structure 210. In some embodiments, the second trench structure 220 may include three or more structurally continuous trenches, thereby providing multiple protections to the first trench structure 210. In some embodiments, the second trench structure 220 may include two structurally continuous trenches and one structurally discontinuous trench. In some embodiments, the second trench structure 220 may include two structurally discontinuous trenches and one structurally continuous trench. In the present embodiment, the pitch Y of adjacent trenches (e.g., the first trench 221 and the second trench 222) may be 2 μm to 5 μm. In some embodiments, the protective effect may also be improved by increasing the spacing Y of adjacent trenches, the width of the trenches, and/or the depth of the trenches.
FIG. 8c is a cross-sectional view taken along line B-B of FIG. 8a according to another embodiment of the present application.
In the embodiment shown in fig. 8c, the second trench structure 220 comprises two first trenches 221 and a second trench 222 arranged around the first trenches 221. The first groove 221 and the second groove 222 are each structurally discontinuous. The notches 227 and 226 of the first and second trenches 221 and 222 are disposed in a staggered manner, so that the external crack can be effectively prevented from extending to the first trench structure 210. Specifically, even if an extraneous crack extends through the notch 226, thereby breaking through the line of defense formed by the second trench 222, it is blocked by the first trench 221. In some embodiments, to make the layout more compact, the protection trench may be provided in only one direction (e.g., a direction in which the semiconductor structures are dense). In some embodiments, the second trench structure 220 may include three or more structurally discontinuous trenches.
Although the structurally discontinuous grooves in fig. 8c are formed from a plurality of rectangular sections, it should be noted that one or more sections of the discontinuous annular grooves may be square, rectangular, circular, oval, diamond, triangular, trapezoidal, wavy, pentagonal, hexagonal, other polygonal shapes, and/or combinations thereof.
In conclusion, upon reading the present detailed disclosure, those skilled in the art will appreciate that the foregoing detailed disclosure can be presented by way of example only, and not limitation. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, improvements, and modifications are intended to be suggested by this disclosure, and are within the spirit and scope of the exemplary embodiments of this disclosure.
Claims (18)
1. A semiconductor structure, comprising:
a semiconductor substrate;
a first trench structure formed in the semiconductor substrate for forming a trench capacitor; and
and the second groove structure is formed in the semiconductor substrate and arranged around the first groove structure.
2. The semiconductor structure of claim 1, wherein the second trench structure comprises one or more trenches, the plurality of trenches are disposed around each other, and at least one of the plurality of trenches is continuous.
3. The semiconductor structure of claim 1, wherein the second trench structure comprises one or more structurally discontinuous trenches disposed around each other.
4. The semiconductor structure of claim 3, wherein the plurality of structurally discontinuous trenches each comprise indentations, the indentations being disposed in an alternating manner.
5. The semiconductor structure of claim 4, wherein a pitch of adjacent trenches in the plurality of structurally discontinuous trenches is 2 μm to 5 μm.
6. The semiconductor structure of claim 1, wherein a depth of each trench in the second trench structure is 25 μ ι η to 35 μ ι η.
7. The semiconductor structure of claim 1, wherein a width of each trench in the second trench structure is 0.8 μ ι η to 1.2 μ ι η.
8. The semiconductor structure of claim 1, wherein the second trench structure is spaced 8 μ ι η to 12 μ ι η from the first trench structure.
9. The semiconductor structure of claim 1, further comprising:
a scribe line formed in the semiconductor substrate and disposed around the second trench structure,
wherein the distance between the second groove structure and the cutting track is 8-12 μm.
10. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate; and
etching the semiconductor substrate to simultaneously form a first trench structure and a second trench structure,
the first trench structure is used for forming a trench capacitor, and the second trench structure is arranged around the first trench structure.
11. The method of claim 10, wherein the second trench structure comprises one or more trenches, wherein the plurality of trenches are disposed around each other, and wherein at least one of the plurality of trenches is continuous.
12. The method of forming a semiconductor structure of claim 10, wherein the second trench structure comprises one or more structurally discontinuous trenches disposed around each other.
13. The method of claim 12, wherein the plurality of structurally discontinuous trenches each include indentations, the indentations being disposed in an alternating manner.
14. The method of claim 13, wherein a pitch of adjacent trenches in the plurality of structurally discontinuous trenches is between 2 μm and 5 μm.
15. The method of forming a semiconductor structure of claim 10, wherein a pitch of the second trench structure to the first trench structure is 8 μ ι η to 12 μ ι η.
16. The method of forming a semiconductor structure of claim 10, wherein each trench in the second trench structure has a depth of 25 μ ι η to 35 μ ι η.
17. The method of forming a semiconductor structure of claim 10, wherein a width of each trench in the second trench structure is 0.8 μ ι η to 1.2 μ ι η.
18. The method of forming a semiconductor structure of claim 10, further comprising:
etching the semiconductor substrate to form a cutting path,
the cutting channel is arranged around the second groove structure, and the distance between the second groove structure and the cutting channel is 8-12 μm.
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| CN201911255015.1A CN112951771A (en) | 2019-12-10 | 2019-12-10 | Semiconductor structure and forming method thereof |
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