CN112929587A - Analog division reading circuit applied to CMOS-TOF image sensor - Google Patents
Analog division reading circuit applied to CMOS-TOF image sensor Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
Abstract
The invention relates to the field of analog integrated circuits, in order to replace the mode of carrying out analog-to-digital conversion and then carrying out division operation by a digital circuit in the prior art, the analog-to-digital conversion digital-to-digital conversion analog-to-digital conversion circuit has the advantages of simple structure, high speed, small area, low power consumption and the like, and is applied to an analog division reading circuit of a CMOS; the output of subtractor 1 and the output of subtractor 2 are then connected to inputs 1 and 2, respectively, of an analog division circuit, which divides the two differences by the phase offset of the reflected light relative to the emitted light
Is turning toAnd (5) cutting. The invention is mainly applied to the integrated circuit design and manufacture occasions.
Description
Technical Field
The invention relates to the field of analog integrated circuit design, in particular to the field of design of a CMOS-TOF image sensor reading circuit. In particular to an analog division readout circuit applied to a CMOS-TOF image sensor.
Background
The image sensor may convert image information into electrical signals that are convenient to store, transmit, and process. There are two types of image sensors, namely, a Charge Coupled Device (CCD) image sensor and a Complementary Metal Oxide Semiconductor (CMOS) image sensor, which are limited by the process level in the early years, and the performance of the CMOS image sensor is low, and the CCD image sensor occupies the mainstream of the image sensor.
With the development of image sensing technology and the improvement of image quality requirements of people, the three-dimensional imaging technology is more and more widely concerned, and the three-dimensional image sensor can acquire depth information of a scene and has wide application prospects in various fields such as industry, consumer electronics, military, automotive electronics, medical treatment and the like. The current three-dimensional imaging methods mainly include a stereoscopic vision method, a triangulation method, a diffraction method, a Time of Flight (TOF) method, and the like. The TOF measures real-time information of a target, and the working principle of the TOF is as follows: the light source of the TOF camera projects modulated light towards the target, the modulated light is reflected at the surface of the target, the reflected light is received by the receiver of the TOF camera, and the distance to the target can be calculated from the propagation time of the modulated light between the camera and the target. Compared with other three-dimensional imaging methods, TOF three-dimensional imaging has the advantages of high precision, low cost, low system complexity, long distance measurement, strong real-time property, simple data processing and the like. TOF stereo imaging can be classified into three types according to the working mode: pulse type, continuous wave type and time dependent single photon counting. The pulse type TOF directly acquires distance information of a target object by using propagation time of an optical pulse signal between the target object and a camera; the continuous wave TOF indirectly acquires distance information of a target object by using a phase difference between emitted light and reflected light; the time-correlated single photon counting TOF is used for acquiring distance information of a target object by utilizing current generated by avalanche breakdown when a photodiode is excited by photons in a Geiger mode. The continuous mode TOF has advantages of low requirements for bandwidth and light source power, high signal-to-noise ratio, and strong configurability, and thus has been widely used.
Sine wave is a common light source of a continuous wave type TOF image sensor, and a light source signal is assumed to be
S(t)＝A sin(ωt) (1)
Where A is the amplitude and ω is the angular frequency of the light source signal. The received optical signal is
Ar is the amplitude of the reflected light received by the sensor, which is attenuated compared to the light source signal,. phi.is the phase shift of the reflected light relative to the incident light, and B is the background light in the environment. The working principle of the TOF image sensor based on sine waves is shown in fig. 1, the distance information of the target object needs to be acquired by sampling signals with four phases and pi/2 intervals in pairs, and the sampling results of the four phases are respectively as follows:
the phase shift can be obtained from equations (3) to (6)
The distance of the target object can be obtained by phase shift
In the prior art, a reading circuit of a TOF image sensor needs to perform analog-to-digital conversion on difference values a0-a2 and a1-A3 of reflected light of different phases received by the sensor, and then a digital circuit is used for division operation. Therefore, if the division operations for a0-a2 and a1-A3 can be realized by analog circuits, the defects of complex data processing, large circuit area and the like of digital circuits can be solved.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a method for dividing the difference values A0-A2 and A1-A3 of two-phase output signals of a pixel by an analog circuit, which replaces the mode of firstly carrying out analog-to-digital conversion and then carrying out division operation by a digital circuit in the prior art. Therefore, the technical scheme adopted by the invention is that the analog division reading circuit applied to the CMOS-TOF image sensor has the following structure: outputs 1 and 3 of four pixels with different phases of the TOF pixel are respectively connected to an input 1 and an input 2 of a subtracter 1, and an output 2 and an output 4 of the TOF pixel are respectively connected to an input 1 and an input 2 of the subtracter 2, so that the difference value of output signals with different phases of the TOF pixel is obtained; the output of subtractor 1 and the output of subtractor 2 are then connected to inputs 1 and 2, respectively, of an analog division circuit, which divides the two differences by the phase offset of the reflected light relative to the emitted light
The tangent value of (c); then the output of the analog division circuit is connected to the input of the analog-to-digital conversion circuit to obtain the phase offset
A digital code of tangent value, which is inverse-tangent converted by digital circuit to obtain the phase shift of received light
According to phase shift
And obtaining the depth information of the detection target.
The pixel adopts a 4-tap structure, four output signals with different phases are obtained simultaneously by one-time exposure, the analog division operation is realized by analog logarithm operation, subtraction operation and inverse logarithm operation, wherein the analog logarithm operation and the inverse logarithm operation both utilize the exponential volt-ampere characteristic when the diode is conducted in the forward direction, and the current of the diode is
Where Is the reverse saturation current of the diode, q Is the electronic charge, UD Is the diode terminal voltage, k Is the boltzmann constant, and T Is the absolute temperature.
Basic logarithm operation circuit structure: the base electrode of a bipolar transistor BJT (bipolar Junction transistor) is grounded, the emitter electrode is connected with the output end of the operational amplifier 1, the collector electrode is connected with the inverting input end of the operational amplifier 1, one end of the resistor 1 is grounded, the other end of the resistor 1 is connected with the non-inverting input end of the operational amplifier 1, one end of the resistor 2 is connected with the input signal ui, the other end of the resistor 2 is connected with the inverting input end of the operational amplifier 1, the virtual ground characteristic of the operational amplifier 1 is utilized, the base electrode voltage and the collector electrode voltage of the bipolar transistor are both 0V, the emitter electrode voltage is equal to the output voltage uo of the operational amplifier 1, and the collector:
so that the relationship between the input voltage ui and the output voltage uo of the operational amplifier 1 is
Is temperature dependent, and a temperature compensation circuit Is used to eliminate the temperature influence of Is.
The logarithm arithmetic circuit structure added with temperature compensation comprises the following steps: one end of the resistor 21 is grounded, the other end of the resistor 21 is connected with the non-inverting input end of the operational amplifier 21, one end of the resistor 22 is connected with an input signal ui2, the other end of the resistor is connected with the inverting input end of the operational amplifier 21, the base electrode of the bipolar transistor 21 is grounded, the collector electrode of the bipolar transistor 21 is connected with the inverting input end of the operational amplifier 21, the emitter electrode of the resistor 22 is connected with the output end of the operational amplifier 21 through a capacitor, one end of the resistor 24 is grounded, the other end of the resistor 23 is connected with the emitter electrode of the transistor 21, the other end of the resistor 25 is connected with the output end of the operational amplifier 22, the base electrode of the bipolar transistor 22 is connected with the contact point of the resistor 23 and the resistor 24R2The other end of the resistor 27 is connected with the non-inverting input end of the operational amplifier 22, one end of the resistor 27 is connected with the non-inverting input end of the operational amplifier 22, the other end of the resistor is grounded, and the output signal uo of the logarithmic circuit is output at the output end of the operational amplifier 21. The bipolar transistors 21 and 22 are pair transistors having the same characteristics, and have collector currents of
Thereby obtaining
The base voltage of the bipolar transistor 22 is shown as
The base voltage of the bipolar transistor 22 is alternatively expressed as:
thereby obtaining a function expression of the output voltage and the input voltage of the operational amplifier
The IS Is eliminated by the above formula, and errors caused by the influence of temperature on the IS are avoided.
Adding a temperature-compensated anti-log operation circuit structure: one end of the resistor 31 is grounded, the other end is connected with the non-inverting input end of the operational amplifier 31, and one end of the resistor 32 is connected with the reference voltage UR3The other end of the bipolar transistor is connected with the inverting input end of the operational amplifier 31, the base of the transistor 31 is connected with an input signal ui3 through a resistor 33, the collector of the transistor is connected with the inverting input end of the operational amplifier 31, the emitter of the transistor is connected with the output end of the operational amplifier 31 through a resistor 34, one end of a capacitor is connected with the inverting input end of the operational amplifier 31, the other end of the capacitor is connected with the output end of the operational amplifier 31, the base of the bipolar collector 32 is grounded, and the collector of the bipolar collector isThe emitter is connected to the emitter of the bipolar transistor 31, one end of the resistor 35 is connected to ground, the other end is connected to the non-inverting input terminal of the operational amplifier 32, one end of the resistor 36 is connected to the inverting input terminal of the operational amplifier 32, the other end is connected to the output terminal of the operational amplifier 32, and the output signal uo3 of the anti-logarithm circuit is output at the output terminal of the operational amplifier 32.
The subtraction circuit structure: one end of the resistor 41 is connected with the input signal ui41, the other end is connected with the inverting input end of the operational amplifier 4, one end of the resistor 42 is connected with the input signal ui42, the other end is connected with the non-inverting input end of the operational amplifier 4, one end of the resistor 43 is grounded, the other end is connected with the non-inverting input end of the operational amplifier 4, one end of the resistor 44 is connected with the inverting input end of the operational amplifier 4, the other end is connected with the output end of the operational amplifier 4, and the relation between the output voltage uo4 of the subtraction circuit and the input voltages ui41 and ui42
If R41 ═ R42 ═ R43 ═ R44, then
uo4＝-ui41+ui42 (21)
The overall structure of the analog division circuit is that the input of the logarithmic circuit 1 is the difference value A20-A22 of two different phase output signals of pixels, and the output of the logarithmic circuit 1
Input 1 of the subtraction circuit is connected, where K is a constant related to a circuit parameter, input of the logarithm circuit 2 is a difference A21-A23 of two other phase output signals of the pixel, output of the logarithm circuit 2
Connected to the input 2 of the subtraction circuit, the output of the subtraction circuit being, according to a mathematical algorithm of subtraction of two logarithms
Output connection object of subtraction circuitThe input of the digital circuit and the output of the anti-digital circuit are
Wherein C and D are constants related to temperature, BJT characteristic parameters and the like, and C and D are both equal to 1 by reasonably designing circuit parameters, thereby obtaining the result of analog division operation
The invention has the characteristics and beneficial effects that:
the analog division circuit provided by the invention is suitable for the TOF image sensor with a 4-tap pixel structure, can solve the problems of complex structure, large number of registers, large power consumption, large area and the like of a digital division circuit, improves the working speed of a reading circuit of the TOF image sensor, reduces the power consumption and saves the chip area.
Description of the drawings:
fig. 1 is based on the sine wave TOF image sensor working principle.
Fig. 2 is a schematic diagram of a 4-tap pixel structure.
Fig. 3 is a block diagram of a TOF reading circuit employing an analog division circuit.
Fig. 4 is a schematic diagram of a basic logarithmic circuit configuration.
Fig. 5 is a schematic diagram of a logarithmic circuit structure incorporating a temperature compensation circuit.
FIG. 6 is a schematic diagram of an anti-log circuit incorporating a temperature compensation circuit.
Fig. 7 is a schematic diagram of a subtraction circuit configuration.
Fig. 8 is a schematic diagram of the overall structure of the analog division circuit described in the present invention.
Detailed Description
Since the TOF image sensor reading circuit using the analog division circuit processes the output signals of four pixels with different phases at the same time, the pixels are required to output the analog signals of four different phases at the same time, and thus a 4-tap pixel structure is adopted. The schematic diagram of the 4-tap pixel structure is shown in fig. 2, and pixel signals of four floating diffusion nodes can be controlled to be read out simultaneously through timing.
When the output signals of the pixels are processed, the mode that the difference value of the output signals of the pixels is firstly subjected to analog-to-digital conversion and then division operation is realized by a digital circuit is changed into the mode that an analog circuit is used for analog voltage division operation. The structure block diagram of the TOF reading circuit adopting the analog division circuit is shown in the attached figure 3, and the working principle is as follows: firstly, respectively connecting outputs 1 and 3 of four pixels with different phases of TOF pixels to an input 1 and an input 2 of a subtracter 1, respectively connecting an output 2 and an output 4 of the pixels to an input 1 and an input 2 of the subtracter 2, respectively, and thus obtaining difference values of output signals with different phases of the pixels; the output of subtractor 1 and the output of subtractor 2 are then connected to inputs 1 and 2, respectively, of an analog division circuit, which divides the two differences by the phase offset of the reflected light relative to the emitted light
The tangent value of (c); then the output of the analog division circuit is connected to the input of the analog-to-digital conversion circuit to obtain the phase offset
A digital code of tangent value, which is inverse-tangent converted by digital circuit to obtain the phase shift of received light
For phase shift
The depth information of the detection target can be obtained through further processing.
In order to more intuitively express the implementation conditions, advantages, and the like of the present invention, embodiments of the present invention are described below with reference to examples. The pixels adopt a 4-tap structure, four output signals with different phases can be obtained simultaneously through one-time exposure, and the analog division operation is realized through analog logarithm operation, subtraction operation and inverse logarithm operation, wherein the analog logarithm operation and the inverse logarithm operation both utilize exponential volt-ampere characteristics when the diodes are conducted in the forward direction. When the diode is in forward conduction, the current is
Wherein Is the reverse saturation current of the diode, q Is the electron charge, UDIs the diode terminal voltage, k is the boltzmann constant, and T is the absolute temperature.
The basic logarithmic computation circuit is schematically shown in fig. 4, wherein a Bipolar Junction Transistor (BJT) has a base grounded, an emitter connected to an output terminal of the operational amplifier 1, a collector connected to an inverting input terminal of the operational amplifier 1, one end of the resistor 1 is grounded, the other end is connected to an non-inverting input terminal of the operational amplifier 1, one end of the resistor 2 is connected to the input signal ui, the other end is connected to an inverting input terminal of the operational amplifier 1, and by using the virtual ground characteristic of the operational amplifier 1, the base voltage and the collector voltage of the Bipolar Transistor are both 0V, the emitter voltage is equal to the output voltage uo of the operational amplifier 1, and the collector current of the Bipolar Transistor is equal to
So that the relationship between the input voltage ui and the output voltage uo of the operational amplifier 1 is
Is temperature dependent, and a temperature compensation circuit Is used to eliminate the temperature influence of Is. The structure of the logarithmic operation circuit with temperature compensation is shown in figure 5, one end of a resistor 21 is grounded, the other end of the resistor is connected with the non-inverting input end of an operational amplifier 21, one end of a resistor 22 is connected with an input signal ui, the other end of the resistor 22 is connected with the inverting input end of the operational amplifier 21, and the bipolar circuit is bipolarThe base of the transistor 21 is grounded, the collector is connected with the inverted input end of the operational amplifier 21, the emitter is connected with the output end of the operational amplifier 21 through a capacitor, one end of a resistor 24 is grounded, the other end of the resistor 24 is connected with the output end of the operational amplifier 21 through a resistor 23, one end of a resistor 25 is connected with the emitter of the transistor 1, the other end of the resistor 25 is connected with the output end of the operational amplifier 22, the base of the bipolar transistor 22 is connected with the contact point of the resistor 23 and the resistor 24, the emitter is connected with the emitter of the bipolar transistor 21, the collector is connected with the inverted input endR2And the other end of the resistor 27 is connected with the inverting input end of the operational amplifier 22, one end of the resistor 27 is connected with the non-inverting input end of the operational amplifier 22, the other end of the resistor is grounded, and the logarithmic circuit output signal uo2 is output at the output end of the operational amplifier 21. The bipolar transistors 21 and 22 are pair transistors having the same characteristics, and have collector currents of
Thereby obtaining
The base voltage of the bipolar transistor 22 may be expressed as
The base voltage of the bipolar transistor 22 can also be expressed as
Thereby obtaining a function expression of the output voltage and the input voltage of the operational amplifier
The IS Is eliminated by the above formula, and errors caused by the influence of temperature on the IS are avoided.
The structure of an anti-log operation circuit with temperature compensation is shown in figure 6, one end of a resistor 31 is grounded, the other end of the resistor 31 is connected with the non-inverting input end of an operational amplifier 31, one end of a resistor 32 is connected with a reference voltage UR3The other end of the inverting input terminal of the operational amplifier 31 is connected with the inverting input terminal of the operational amplifier 31, the base of the transistor 31 is connected with the input signal ui3 through the resistor 33, the collector is connected with the inverting input terminal of the operational amplifier 31, the emitter is connected with the output terminal of the operational amplifier 31 through the resistor 34, one end of the capacitor is connected with the inverting input terminal of the operational amplifier 31, the other end of the capacitor is connected with the output terminal of the operational amplifier 31, the base of the bipolar collector 32 is grounded, the collector is connected with the inverting input terminal of the operational amplifier 32, the emitter is connected with the emitter of the bipolar transistor 31, one end of the resistor 35 is grounded, the other end of the resistor is connected with the non-inverting input terminal of the operational amplifier 32, the other end of the resistor 36 is connected with the output terminal of the operational amplifier 32, the output signal uo3 of.
The structure of the subtraction circuit is shown in fig. 7, one end of a resistor 41 is connected with an input signal ui41, the other end is connected with the inverting input end of the operational amplifier 4, one end of the resistor 42 is connected with the input signal ui42, the other end is connected with the non-inverting input end of the operational amplifier 4, one end of a resistor 43 is grounded, the other end is connected with the non-inverting input end of the operational amplifier 4, one end of a resistor 44 is connected with the inverting input end of the operational amplifier 4, the other end is connected with the output end of the operational amplifier 4, and the relation between the output voltage uo4 of the subtraction circuit and the input voltages ui 36
If R is41＝R42＝R43＝R44Then, then
uo4＝-ui41+ui42 (21)
The overall structure of the analog division circuit is shown in fig. 8, the input of the logarithmic circuit 1 is the difference value A20-A22 of two different phase output signals of the pixel, and the output of the logarithmic circuit 1
Input 1 of the subtraction circuit is connected, where K is a constant related to a circuit parameter, input of the logarithm circuit 2 is a difference A21-A23 of two other phase output signals of the pixel, output of the logarithm circuit 2
Connected to the input 2 of the subtraction circuit, the output of the subtraction circuit being, according to a mathematical algorithm of subtraction of two logarithms
The output of the subtraction circuit is connected to the input of the anti-log circuit, the output of the anti-log circuit is
Wherein C and D are constants related to temperature, BJT characteristic parameters and the like, and C and D are both equal to 1 by reasonably designing circuit parameters, thereby obtaining the result of analog division operation
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (6)
1. Analog division reading applied to CMOS-TOF image sensorThe output circuit is characterized by comprising the following structures: outputs 1 and 3 of four pixels with different phases of the TOF pixel are respectively connected to an input 1 and an input 2 of a subtracter 1, and an output 2 and an output 4 of the TOF pixel are respectively connected to an input 1 and an input 2 of the subtracter 2, so that the difference value of output signals with different phases of the TOF pixel is obtained; the output of subtractor 1 and the output of subtractor 2 are then connected to inputs 1 and 2, respectively, of an analog division circuit, which divides the two differences by the phase offset of the reflected light relative to the emitted light
The tangent value of (c); then the output of the analog division circuit is connected to the input of the analog-to-digital conversion circuit to obtain the phase offset
A digital code of tangent value, which is inverse-tangent converted by digital circuit to obtain the phase shift of received light
According to phase shift
And obtaining the depth information of the detection target.
2. The analog division readout circuit applied to the CMOS-TOF image sensor according to claim 1, wherein the pixel adopts a 4-tap structure, four output signals with different phases are obtained simultaneously by one exposure, and the analog division operation is realized by analog logarithm operation, subtraction operation and inverse logarithm operation, wherein the analog logarithm operation and the inverse logarithm operation both utilize the exponential volt-ampere characteristic when the diode is in forward conduction, and the current when the diode is in forward conduction is:
where Is the reverse saturation current of the diode, q Is the electronic charge, UD Is the diode terminal voltage, k Is the boltzmann constant, and T Is the absolute temperature.
3. The analog division readout circuit applied to a CMOS-TOF image sensor according to claim 1, wherein the basic logarithmic operation circuit structure: the base electrode of a bipolar transistor BJT (bipolar Junction transistor) is grounded, the emitter electrode is connected with the output end of the operational amplifier 1, the collector electrode is connected with the inverting input end of the operational amplifier 1, one end of the resistor 1 is grounded, the other end of the resistor 1 is connected with the non-inverting input end of the operational amplifier 1, one end of the resistor 2 is connected with the input signal ui, the other end of the resistor 2 is connected with the inverting input end of the operational amplifier 1, the virtual ground characteristic of the operational amplifier 1 is utilized, the base electrode voltage and the collector electrode voltage of the bipolar transistor are both 0V, the emitter electrode voltage is equal to the output voltage uo of the operational amplifier 1, and the collector:
so that the relationship between the input voltage ui and the output voltage uo of the operational amplifier 1 is
Is temperature dependent, and a temperature compensation circuit Is used to eliminate the temperature influence of Is.
4. The analog division readout circuit applied to a CMOS-TOF image sensor according to claim 1 wherein the temperature compensated logarithmic operation circuit structure is added: one end of the resistor 21 is grounded, the other end is connected with the non-inverting input end of the operational amplifier 21, one end of the resistor 22 is connected with the input signal ui2 and the other endThe end is connected with the inverted input end of the operational amplifier 21, the base of the bipolar transistor 21 is grounded, the collector is connected with the inverted input end of the operational amplifier 21, the emitter is connected with the output end of the operational amplifier 21 through a capacitor, one end of the resistor 24 is grounded, the other end is connected with the output end of the operational amplifier 21 through a resistor 23, one end of the resistor 25 is connected with the emitter of the transistor 21, the other end is connected with the output end of the operational amplifier 22, the base of the bipolar transistor 22 is connected with the contact point of the resistor 23 and the resistor 24, the emitter is connected with the emitter of the bipolar transistor 21, the collector is connected with the inverted input end ofR2The other end of the resistor 27 is connected with the non-inverting input end of the operational amplifier 22, one end of the resistor 27 is connected with the non-inverting input end of the operational amplifier 22, the other end of the resistor is grounded, and the output signal uo of the logarithmic circuit is output at the output end of the operational amplifier 21. The bipolar transistors 21 and 22 are pair transistors having the same characteristics, and have collector currents of
Thereby obtaining
The base voltage of the bipolar transistor 22 is shown as
The base voltage of the bipolar transistor 22 is alternatively expressed as:
thereby obtaining a function expression of the output voltage and the input voltage of the operational amplifier
The IS Is eliminated by the above formula, and errors caused by the influence of temperature on the IS are avoided.
5. The analog division readout circuit applied to a CMOS-TOF image sensor according to claim 1, wherein a temperature compensated anti-log operation circuit structure is added: one end of the resistor 31 is grounded, the other end is connected with the non-inverting input end of the operational amplifier 31, and one end of the resistor 32 is connected with the reference voltage UR3The other end of the resistor is connected with the inverting input end of the operational amplifier 31, the base of the transistor 31 is connected with an input signal ui3 through a resistor 33, the collector of the transistor is connected with the inverting input end of the operational amplifier 31, the emitter of the transistor is connected with the output end of the operational amplifier 31 through a resistor 34, one end of a capacitor is connected with the inverting input end of the operational amplifier 31, the other end of the capacitor is connected with the output end of the operational amplifier 31, the base of the bipolar collector 32 is grounded, the collector of the capacitor is connected with the inverting input end of the operational amplifier 32, the emitter of the bipolar transistor 31 is connected, one end of the resistor 35 is grounded, the other end of the resistor is connected with the non-inverting input end of the operational amplifier 32, the other end of the resistor 36 is connected with the output.
6. The analog division readout circuit applied to a CMOS-TOF image sensor according to claim 1, wherein the subtraction circuit structure: one end of the resistor 41 is connected with the input signal ui41, the other end is connected with the inverting input end of the operational amplifier 4, one end of the resistor 42 is connected with the input signal ui42, the other end is connected with the non-inverting input end of the operational amplifier 4, one end of the resistor 43 is grounded, the other end is connected with the non-inverting input end of the operational amplifier 4, one end of the resistor 44 is connected with the inverting input end of the operational amplifier 4, the other end is connected with the output end of the operational amplifier 4, and the output voltage uo4 of the subtraction circuit and the input voltages ui41 and ui42 have the relationship:
if R41 ═ R42 ═ R43 ═ R44, then
uo4＝-ui41+ui42 (21)
The overall structure of the analog division circuit is that the input of the logarithmic circuit 1 is the difference value A20-A22 of two different phase output signals of pixels, and the output of the logarithmic circuit 1
Input 1 of the subtraction circuit is connected, where K is a constant related to a circuit parameter, input of the logarithm circuit 2 is a difference A21-A23 of two other phase output signals of the pixel, output of the logarithm circuit 2
Connected to the input 2 of the subtraction circuit, the output of the subtraction circuit being, according to a mathematical algorithm of subtraction of two logarithms
The output of the subtraction circuit is connected to the input of the anti-log circuit, the output of the anti-log circuit is
Wherein C and D are constants related to temperature, BJT characteristic parameters and the like, and C and D are both equal to 1 by reasonably designing circuit parameters, thereby obtaining the result of analog division operation
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