CN112929512B - Control circuit and control method thereof - Google Patents
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- CN112929512B CN112929512B CN201911374373.4A CN201911374373A CN112929512B CN 112929512 B CN112929512 B CN 112929512B CN 201911374373 A CN201911374373 A CN 201911374373A CN 112929512 B CN112929512 B CN 112929512B
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Abstract
The invention provides a control circuit and a control method thereof, wherein the control circuit is coupled between an image acquisition device and a display device. The image acquisition device outputs a plurality of image data according to an operating frequency. The control circuit comprises a first transmission interface, a storage circuit, a processing circuit and a second transmission interface. The first transmission interface is coupled to the image acquisition device for receiving the image data. The storage circuit is coupled to the first transmission interface for receiving and storing the image data. The processing circuit acquires the image data stored in the storage circuit, is used for generating a plurality of display data, and generates the working frequency according to the quantity of the data stored in the storage circuit. The second transmission interface is coupled to the processing circuit and used for outputting display data to the display device.
Description
Technical Field
The present invention relates to a control circuit, and more particularly, to a control circuit coupled between an image capturing device and a display device.
Background
In the current image processing process, a microprocessor unit (MPU) is generally utilized. However, today's micro-controller units (MCUs) are increasingly powerful and are increasingly capable of image processing. However, the internal memory space of the micro controller unit is limited, and a large amount of image data cannot be stored.
Disclosure of Invention
The invention provides a control circuit which is coupled between an image acquisition device and a display device. The image acquisition device outputs a plurality of image data according to an operating frequency. The control circuit comprises a first transmission interface, a storage circuit, a processing circuit and a second transmission interface. The first transmission interface is coupled to the image acquisition device for receiving the image data. The storage circuit is coupled to the first transmission interface for receiving and storing the image data. The processing circuit acquires the image data stored in the storage circuit, is used for generating a plurality of display data, and generates the working frequency according to the quantity of the data stored in the storage circuit. The second transmission interface is coupled to the processing circuit and used for outputting display data to the display device.
The invention also provides a control method, which is suitable for a control circuit and comprises the steps of receiving a plurality of image data, wherein the plurality of image data are provided by an image acquisition device; storing the plurality of image data in a memory circuit; acquiring the plurality of image data stored by the storage circuit to generate a plurality of display data; outputting the plurality of display data to a display device; and adjusting an operating frequency of the image acquisition device according to the amount of the data stored by the storage circuit.
The control method of the present invention may be implemented by the control circuit of the present invention, which is hardware or firmware capable of executing specific functions, or may be embodied in a recording medium by means of program codes and implemented in combination with specific hardware. When the program code is loaded into and executed by an electronic device, processor, computer, or machine, the electronic device, processor, computer, or machine becomes a control circuit or operating system for practicing the present invention.
Drawings
FIG. 1 is a schematic diagram of an operating system of the present invention.
Fig. 2 is a schematic diagram of a control circuit according to one embodiment of the present invention.
Fig. 3 is a schematic diagram of a memory circuit.
FIG. 4 is a schematic diagram of a control method according to one embodiment of the present invention.
Fig. 5 is a schematic diagram of another possible flow of the control method of the present invention.
Reference numerals:
100: an operating system; 110: an image acquisition device;
120: a control circuit; 130: a display device;
125: an integrated circuit bus; 210. 230: a transmission interface;
220: a processing circuit; 240: a memory circuit;
250: a counting circuit; 400. 500: a control method;
MCLK: an operating frequency; VA: a count value;
DTI: image data; PCLK: a pixel frequency;
DTD: displaying the data; hsync: a horizontal synchronization signal;
vsync). A vertical synchronization signal; BK0 to BK11: a block;
IND: an index; DATCAP/2: a target value;
DATHTH, DATLTH: a critical value;
DATCAP: memory space
DATFULLF, DATEPTF: boundary values;
s411 to S419, S511 to S521: and (3) step (c).
Detailed Description
The present invention will be described in more detail with reference to the drawings, wherein the invention is not limited to the embodiments. The present description provides various examples to illustrate the features of various embodiments of the present invention. The arrangement of the elements in the embodiments is for illustration, and is not intended to limit the invention. In addition, the repetition of the reference numerals in the embodiments is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments.
FIG. 1 is a schematic diagram of an operating system of the present invention. As shown, the operating system 100 includes an image acquisition device 110, a control circuit 120, and a display device 130. The image acquisition device 110 senses external light according to an operating frequency MCLK and generates image data DT according to the sensing result I . In one possible embodiment, the image acquisition device 110 converts the operating frequency MCLK to generate a pixel frequency PCLK and outputs the image data DT according to the pixel frequency PCLK I . In the present embodiment, the image acquisition device 110 outputs the image data DT in a serial manner (serial communication) I But are not intended to limit the invention. In other embodiments, the image acquisition device 110 outputs the image data DT in a parallel manner (parallel communication) I . In addition, the present invention is not limited to the circuit architecture of the image capturing device 110. In one possible embodiment, the image acquisition device 110 includes a photosensitive coupling element (Charge Coupled Device; CCD) or a Complementary metal oxide semiconductor (CMOS Me)tal-Oxide Semiconductor; CMOS) sensing element.
The control circuit 120 is coupled between the image acquisition device 110 and the display device 130, and receives and stores the image data DT I . In the present embodiment, when the control circuit 120 stores the image data DT I When the number of (a) reaches a target value, the control circuit 120 generates a target value based on the image data DT stored in itself I Generating display data DT D And to the display device 130. In one possible embodiment, the control circuit 120 directly converts the image data DT I As display data DT D Output to the display device 130. In this example, each time the control circuit 120 outputs a display data DT D When the control circuit 120 deletes the corresponding image data DT I . For convenience of description, it is assumed that the control circuit 120 directly converts the image data DT I As display data DT D But are not intended to limit the invention. In other embodiments, the control circuit 120 processes (e.g., converts) the image data DT I For generating display data DT D 。
The control circuit 120 outputs display data DT D While the control circuit 120 is still continuously receiving and storing the image data DT I . When the control circuit 120 stores the image data DT I When the number of (2) is greater than a first threshold, the control circuit 120 decreases the operating frequency MCLK for slowing down the image data DT outputted from the image capturing device 110 I Is a function of the speed of the machine. However, when the control circuit 120 stores the image data DT I When the number of (2) is smaller than a second threshold, the control circuit 120 increases the operating frequency MCLK to accelerate the image data DT output by the image capturing device 110 I Is a function of the speed of the machine. In the present embodiment, the control circuit 120 outputs the display data DT in a serial manner D But are not intended to limit the invention. In other embodiments, the control circuit 120 outputs the display data DT in a parallel manner D . The invention is not limited to the architecture of the control circuit 120. In one possible embodiment, the control circuit 120 is a Micro Control Unit (MCU).
In other embodiments, the control circuit 120 receives the image data DT according to the pixel frequency PCLK I . And in accordance with the inventionThe relationship between the operating frequency MCLK and the pixel frequency PCLK is not limited. In one possible embodiment, when the control circuit 120 decreases the operating frequency MCLK, the pixel frequency PCLK also decreases. Thus, the control circuit 120 receives the image data DT I Is slowed down. In this example, when the control circuit 120 increases the operating frequency MCLK, the pixel frequency PCLK also increases. Thus, the control circuit 120 receives the image data DT I The speed of (c) becomes faster.
The present invention does not limit how the control circuit 120 determines the image data DT stored in itself I Whether the number of (c) reaches a target value. In one possible embodiment, each time the image acquisition device 110 outputs an image data DT I After that, the image capturing device 110 enables a horizontal synchronizing signal Hsync. Therefore, the control circuit 120 can know the image data DT according to the enabled times of the horizontal synchronizing signal Hsync I Whether the number of (c) reaches a target value. In another possible embodiment, the control circuit 120 is based on the internal imaged data DT I The number of filled memory blocks to obtain the image data DT I Whether the number of (c) reaches a target value.
The present invention does not limit the image data DT I Is a format of (c). In one possible embodiment, each image data DT I Is a column of image data. In this example, when the control circuit 120 is based on an image data DT I Output a display data DT D At this time, one column of pixels of the display device 130 is based on the display data DT D And a picture is presented. The present invention is not limited to the control circuit 120 receiving the image data DT I Is of the speed of (and) output display data DT D Is a function of the speed of the machine. The control circuit 120 receives the image data DT I May be the same or different from the output display data DT D Is a function of the speed of the machine.
In one possible embodiment, each time the control circuit 120 receives an image data DT I When this occurs, the control circuit 120 increments a count value. Every time the control circuit 120 outputs a display data DT D When this count value is reduced, the control circuit 120. In this example, the count value represents the image data DT stored by the control circuit 120 I Is a number of (3). In other embodimentsIn one example, the control circuit 120 reads the count value every fixed time, and adjusts the operating frequency MCLK according to the count value.
When the count value is greater than a high threshold (or first threshold), the image data DT stored in the control circuit 120 is indicated I Is a relatively large number. Therefore, the control circuit 120 decreases the operating frequency MCLK for slowing down the image data DT output by the image capturing device 110 I Is a function of the speed of the machine. However, when the count value is smaller than a low threshold (or second threshold), the image data DT stored in the control circuit 120 is indicated I Is less numerous. Therefore, the control circuit 120 increases the operating frequency MCLK for accelerating the output of the image data DT from the image capturing device 110 I Is a function of the speed of the machine.
In other embodiments, each time the image data DT output by the image capturing device 110 I When the number reaches a predetermined value, the image capturing device 110 enables a vertical synchronization signal Vsync. For example, when the image acquisition device 110 outputs 240 strokes of image data DT I After that, the image capturing device 110 enables the vertical synchronization signal Vsync. In this example, each time the image acquisition device 110 outputs one image data DT I At this time, the image acquisition device 110 enables the horizontal synchronization signal Hsync.
In some embodiments, the control circuit 120 is implemented via an integrated circuit bus (Inter-Integrated Circuit; I) 2 C) 125 are in communication with the image acquisition device 110. In this case, the control circuit 120 may set the image capturing device 110 to output color or black image data or set the number of images output by the image capturing device 110 per second, such as 60, 30 or 1 images, according to the preset value stored in advance. In one possible embodiment, each 1 frame is composed of a plurality of pens (e.g. 240 pens) of image data DT I Is composed of the components. In some embodiments, the control circuit 120 sets the image data DT through the integrated circuit bus 125 I Is a high resolution. For example, the control circuit 120 may require the image capturing device 110 to output image data with a resolution of 320X240 or 640X480 to meet the resolution of the display device 130.
Display device130 according to the display data DT D And presenting the picture. In one possible embodiment, the display device 130 has an i80 interface (not shown) or a serial peripheral interface (serial peripheral interface) for receiving the display data DT D . The present invention is not limited to the type of display device 130. In one possible embodiment, the display device 130 is a non-self-luminous display (LCD display). In other embodiments, the display device 130 is a self-luminous display (such as an organic light emitting diode display (Organic Light Emitting Diode Display; OLED display).
Fig. 2 is a schematic diagram of a control circuit according to one embodiment of the present invention. As shown, the control circuit 120 includes transmission interfaces 210, 230, a processing circuit 220, and a memory circuit 240. The transmission interface 210 is coupled to the image acquisition device 110 for transmitting the image data DT I The operating frequency MCLK, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the pixel frequency PCLK. In addition, the transport interface 210 has an integrated circuit bus 125.
The processing circuit 220 receives the image data DT via the transmission interface 210 I And image data DT I Written to the memory circuit 240. In the present embodiment, when the image data DT stored by the storage circuit 240 I When the number of (a) reaches a target value, the processing circuit 220 starts to sequentially read and output the image data stored in the storage circuit 240.
The transmission interface 230 transmits the display data DT D And to the display device 130. In the present embodiment, the transmission interface 230 receives the display data DT in a serial manner D And outputs display data DT in serial mode D The display device 130 is not intended to limit the present invention. In other embodiments, the transmission interface 230 may receive the display data DT generated by the processing circuit 220 in a parallel manner D 。
The storage circuit 240 is coupled to the processing circuit 220 for storing the image data DT I . In the present embodiment, the storage circuit 240 indirectly receives the image data DT through the processing circuit 220 I But are not intended to limit the invention. In other embodimentsIn one embodiment, the memory circuit 240 is directly coupled to the transmission interface 210 for directly receiving the image data DT I . The present invention is not limited to the type of memory circuit 240. In one possible embodiment, the memory circuit 240 is a Static Random Access Memory (SRAM).
Fig. 3 is a schematic diagram of a memory circuit 240. As shown, the memory circuit 240 has blocks BK 0-BK 11 for storing a plurality of image data DT I . In other embodiments, the memory circuit 240 has other blocks for storing other information. In this embodiment, each of the blocks BK 0-BK 11 is used to store one line of image data. In this example, the image data stored by each of the blocks BK 0-BK 11 is the data required for a column of pixels of the display device 130. In other embodiments, image data stored in each tile may be available for use with multiple columns of pixels, or image data stored in multiple tiles may be available for use with a single column of pixels.
In the present embodiment, it is assumed that the storage circuit 240 stores nine image data DT I And each image data DT I A block may be filled. Accordingly, the blocks BK0 to BK8 are in the filled state, and the blocks BK9 to BK11 are in the unfilled state. Since the blocks BK 0-BK 8 are full, the index IND points to the block BK8. In this example, when the index IND points to the block BK5, the image data DT is represented I Has reached the target value DATCAP/2. Thus, the processing circuit 220 starts reading and outputting the image data DT stored in the storage circuit 240 I 。
For example, the processing circuit 220 may first read the image data stored in the block BK0 and use the image data stored in the block BK0 as the first display data DT D Output to the display device 130. The first column of pixels in the display device 130 is based on the display data DT of the first pen D And presenting the picture. At this time, the index value IND may move downward. However, since the processing circuit 220 continues to write the image data DT I To the memory circuit 240, the index value IND may gradually move up to the block BK8.
When the index value IND points to the block BK8, it represents the image data DT stored by the storage circuit 240 I The number of (2) has reached the high threshold DATHTH. Therefore, the processing circuit 220 decreases the operating frequency MCLK for commanding the image capturing device 110 to slow down the output image data DT I Is a function of the speed of the machine. However, when the index value IND points to the block BK1, it represents the image data DT stored by the storage circuit 240 I The number of (a) has been lower than the low threshold datath. Therefore, the processing circuit 220 increases the operating frequency MCLK for commanding the image capturing device 110 to increase the output image data DT I Is a function of the speed of the machine. When the index IND is between the high threshold datath and the low threshold datath, the processing circuit 220 does not adjust the operating frequency MCLK. In one possible embodiment, the target value DATCAP/2 is half of the memory space DATCAP used by the memory circuit 240 to store the column image data.
Since the processing circuit 220 starts to read the image data stored in the storage circuit 240 after the number of the image data in the storage circuit 240 reaches a target value, it is used to provide the display data DT D In the display device 130, the memory space of the memory circuit 240 is not required to be too large. Furthermore, since the processing circuit 220 dynamically adjusts the operating frequency MCLK, the amount of column image data stored by the memory circuit 240 can be properly controlled without losing the image data DT I 。
In some embodiments, when processing circuit 220 detects that an exception condition has occurred, processing circuit 220 performs a particular action. For example, when the index IND is greater than a threshold value datfullff (i.e., a third threshold value), it indicates that the image acquisition device 110 outputs the image data DT I Is too fast, the memory circuit 240 does not store the image data DT as much I . Therefore, the processing circuit 220 may suspend the supply of the display data DT after outputting the column image data stored in the BK0 to BK11 D Until the vertical synchronization signal Vsync is enabled, in the display device 130. In this example, since the processing circuit 220 pauses refreshing the picture of the display device 130, some columns of pixels of the display device 130 may exhibit the previous picture. However, after the vertical synchronization signal Vsync is enabled, the processing circuit 220 starts outputting the display data DT D In the display device 130, the user cannot easily observe that the display device 130 presents an incorrect picture. In other embodimentsIn an embodiment, when the storage circuit 240 is not storing the image data DT I When the display device 130 is in the black state, the processing circuit 220 may output specific display data to the display device 130 for displaying black images on some rows of pixels of the display device 130.
Similarly, when the index IND is lower than another boundary value DATEPTF (e.g., fourth threshold value), it indicates that the image acquisition device 110 outputs the image data DT I Is too slow, the storage circuit 240 does not store the complete image data DT I . Therefore, the processing circuit 220 cannot provide the correct display data DT D And to the display device 130. At this time, the processing circuit 220 may suspend acquiring the blocks BK0 to BK11 and suspend refreshing the screen of the display device 130. In this example, the display device 130 may present the previous frame. In other embodiments, the processing circuit 220 may provide a predetermined image to the display device 130, so that the display device 130 temporarily displays a black image. At this time, the processing circuit 220 may increase the operating frequency MCLK to speed up the image data DT output from the image capturing device 110 I Is a function of the speed of the machine. Due to the image data DT I The number of (2) reaches the target value DATCAP/2, so that the processing circuit 220 can immediately generate the display data DT D At display 130. Due to the effect of persistence of vision, and the processing circuit 220 provides the display data DT on-the-fly D Therefore, the user cannot easily observe that the display device 130 presents an incorrect picture.
Referring to fig. 2, the control circuit 120 includes a counting circuit 250. The counting circuit 250 has a count value VA. The count value VA corresponds to the index IND of fig. 3. In this example, the processing circuit 220 is configured to store the image data DT according to the image data DT stored in the storage circuit 240 I The count value VA is adjusted, and the operating frequency MCLK is adjusted according to the count value VA. In another possible embodiment, the count value VA relates to the number of times the horizontal synchronizing signal Hsync is enabled. In this example, the processing circuit 220 increments the count value VA each time the image capturing apparatus 110 enables the horizontal synchronization signal Hsync. Each time the processing circuit 220 generates a display data DT D In this case, the processing circuit 220 decrements the count value VA.
The present invention does not limit when the processing circuit 220 adjusts the operating frequency MCLK. In one possible embodiment, the processing circuit 220 adjusts the operating frequency MCLK according to the count value VA every time the horizontal synchronizing signal Hsync is enabled. In other embodiments, when the number of times the horizontal synchronizing signal Hsync is enabled reaches a predetermined value, the processing circuit 220 reads the count value VA.
FIG. 4 is a schematic diagram of a control method according to one embodiment of the present invention. The control method 400 of the present invention is suitable for a control circuit (e.g., the control circuit 200 of fig. 2) for adjusting the speed at which an image capturing device outputs image data. In this case, the control circuit does not need to provide a large-capacity memory to store image data. Therefore, the usable space of the control circuit can be increased, the cost of the element can be reduced, and the memory is more expensive as the capacity is larger.
First, an initialization setting is performed (step S411). In one possible embodiment, step S411 initializes a plurality of flags inside the control circuit. The flags are used to provide different default values, such as DATFULLF, DATHTH, DATCAP/2, DATLTH and DATEPTF of FIG. 3. In addition, the control circuit may set an external image acquisition device according to the plurality of flags. In one possible embodiment, the number of the plurality of flags may be burned in the control circuit in advance, so step S411 may be omitted.
A plurality of image data is received and stored (step S412). In one possible embodiment, the plurality of image data is provided by an image acquisition device (e.g., 110 shown in FIG. 1). The image acquisition device may comprise a CCD or CMOS sensor element. In some embodiments, each image data is a column of image data for a column of pixels of the display device. In one possible embodiment, step S412 is to store the plurality of image data in a memory circuit. The memory circuit may be a volatile memory.
It is determined whether the number of stored image data reaches a target value (step S413). In one possible embodiment, the target value is the value of a flag initialized in step S411, such as the target value DATCAP/2 of FIG. 3. The present invention does not limit how to determine whether the number of stored image data reaches a target value in step S413. In one possible embodiment, a count value is incremented each time the image capture device enables a horizontal synchronization signal. Therefore, by the count value, it is known whether the number of stored image data reaches a target value. In other embodiments, step S413 is to determine whether the number of stored image data reaches a target value according to the number of memory blocks filled with the image data.
When the number of stored image data does not reach the target value, the process returns to step S412, and the image data continues to be received and stored. When the number of stored image data reaches the target value, a display data is outputted to a display device (step S414). In one possible embodiment, step S414 outputs the image data stored in the storage circuit as display data to the display device. In this example, the count value is decremented each time a display data is output in step S414. However, the count value is increased whenever image data is stored.
The speed at which the image data is output by the image acquisition device is adjusted according to the number of stored image data (step S415). In one possible embodiment, step S415 is triggered when the image capturing device enables a horizontal synchronization signal. For example, after step S414, if the horizontal synchronization signal is not triggered, step S415 is not performed. In other embodiments, step S415 is performed only when the number of times the horizontal synchronization signal is enabled reaches a predetermined value.
In the present embodiment, step S415 includes steps S416 to S419. First, it is determined whether the number of stored image data is greater than a first threshold (step S416). If the number of stored image data is greater than the first threshold value, the speed at which the image data is output by the image acquisition device is slowed down (step S417). In one possible embodiment, step S417 is to reduce the operating frequency of the image capturing device. In this case, the image acquisition device reduces the pixel frequency according to the reduced operating frequency. However, returning to step S414, the stored image data is continuously read and converted.
If the number of stored image data is not greater than the first threshold, it is determined whether the number of stored image data is less than a second threshold (step S418). In this embodiment, the second threshold is smaller than the first threshold. When the number of stored image data is smaller than the second critical value, the speed of outputting the image data by the image acquisition device is increased (step S419). In one possible embodiment, step S419 is to speed up the operating frequency of the image capturing device. In this case, the image acquisition device may increase the pixel frequency according to the accelerated operating frequency. However, returning to step S414, the stored image data is continuously read and converted.
In the present embodiment, after the reception of the image data is started (step S412), the reception of the image data is continued. Therefore, the number of image data stored in the memory circuit can be maintained within a preset range.
Fig. 5 is another flow chart of the control method of the present invention. Fig. 5 is similar to fig. 4, except that the control method 500 of fig. 5 has more steps S520 and 521. Since steps S511 to S519 are similar to steps S411 to S419, the description thereof will not be repeated. In this embodiment. Step S520 is to determine whether an abnormal situation occurs. When an abnormal situation occurs, a specific action is performed (step S521), and then the process returns to step S512, where the image data is continuously received and stored. When the abnormal situation does not occur, step S515 is performed.
In one possible embodiment, the abnormal condition is that the amount of data stored in the memory circuit is greater than a third threshold or less than a fourth threshold, wherein the third threshold is greater than the first threshold and the fourth threshold is less than the second threshold. For example, when the number of image data stored in the storage circuit is greater than the third threshold value, it means that the image data is output by the image acquisition apparatus too fast, and the storage circuit is not as fast as the image data. In other embodiments, when the amount of image data stored in the memory circuit is less than the fourth threshold, it is indicative that the image data is output by the image capture device too slowly, and the image data in the memory circuit is insufficient to drive the display device.
When the abnormal situation occurs, a specific action is executed, such as outputting a preset data to the display device. In this case, the pixels of the display device may exhibit black images (corresponding to the preset data). The user does not perceive a black picture due to the persistence of vision. In other embodiments, certain actions may suspend refreshing the display device, i.e., not outputting any signals to the display device. Thus, the display device presents the previous picture. Since the control circuit of the present invention will properly adjust (accelerate or decelerate) the speed of the image data output from the image capturing device, the display device can be refreshed in real time to avoid data overload (over run) or underrun (underrun).
The control method of the present invention, or a specific form or part thereof, may exist in the form of program code. The program code may be stored on a tangible medium, such as a floppy diskettes, CD-ROMs, hard drives, or any other machine-readable (e.g., computer-readable) storage medium, or may be a computer program product in an external form, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. Program code may also be transmitted over some transmission medium, such as electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine, such as a computer, the machine becomes an area of control for the participation of the machine in the invention. When implemented in a general-purpose processing unit, the program code combines with the processing unit to provide a unique apparatus that operates analogously to specific logic circuits.
Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Furthermore, unless explicitly indicated otherwise, the definition of a word in a general dictionary should be construed as meaning in its articles of related art and should not be interpreted as an ideal state or an excessively formal state.
Although the invention has been described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. For example, the system, apparatus or method according to the embodiments of the present invention may be implemented in hardware, software or a combination of hardware and software. The scope of the invention is therefore defined by the appended claims.
Claims (8)
1. A control circuit coupled between an image capturing device and a display device, the image capturing device outputting a plurality of image data according to an operating frequency, the control circuit comprising:
the first transmission interface is coupled with the image acquisition device and used for receiving the plurality of image data;
the storage circuit is coupled with the first transmission interface and used for receiving and storing the plurality of image data;
the processing circuit is used for acquiring the plurality of image data stored in the storage circuit to generate a plurality of display data and generating the working frequency according to the quantity of the data stored in the storage circuit; and
a second transmission interface coupled to the processing circuit for outputting the plurality of display data to the display device:
when the amount of data stored in the storage circuit is larger than a first critical value, the processing circuit reduces the working frequency to slow down the speed of the image acquisition device outputting the image data, and when the amount of data stored in the storage circuit is smaller than a second critical value, the processing circuit increases the working frequency to speed up the speed of the image acquisition device outputting the image data, wherein the first critical value is larger than the second critical value.
2. The control circuit of claim 1, wherein the image capture device converts the operating frequency to generate a pixel frequency and provides the pixel frequency to the processing circuit, and the processing circuit receives the plurality of image data according to the pixel frequency and writes the plurality of image data to the memory circuit.
3. The control circuit of claim 2 wherein the image acquisition device decreases the pixel frequency when the processing circuit decreases the operating frequency and increases the pixel frequency when the processing circuit increases the operating frequency.
4. The control circuit of claim 1, wherein the processing circuit suspends acquiring the plurality of image data stored in the memory circuit when the amount of data stored in the memory circuit is greater than a third threshold or less than a fourth threshold, the third threshold being greater than the first threshold and the fourth threshold being less than the second threshold.
5. The control circuit of claim 4, wherein the processing circuit outputs a predetermined data to the display device through the second transmission interface when the amount of data stored in the storage circuit is greater than the third threshold or less than the fourth threshold.
6. The control circuit of claim 1, further comprising:
the counting circuit is provided with a counting value, wherein the processing circuit adjusts the counting value according to the quantity of the data stored by the storage circuit and adjusts the working frequency according to the counting value.
7. A control method is characterized by being suitable for a control circuit and comprising
Receiving a plurality of image data, wherein the plurality of image data is provided by an image acquisition device;
storing the plurality of image data in a memory circuit;
acquiring the plurality of image data stored by the storage circuit to generate a plurality of display data;
outputting the plurality of display data to a display device; and
adjusting an operating frequency of the image acquisition device according to the quantity of the data stored by the storage circuit;
when the amount of data stored in the storage circuit is larger than a first critical value, the processing circuit reduces the working frequency to slow down the speed of the image acquisition device outputting the image data, and when the amount of data stored in the storage circuit is smaller than a second critical value, the processing circuit increases the working frequency to speed up the speed of the image acquisition device outputting the image data, wherein the first critical value is larger than the second critical value.
8. The control method of claim 7, further comprising:
receiving a pixel frequency; and
receiving the plurality of image data according to the pixel frequency;
wherein the pixel frequency is a third value when the operating frequency is decreased, and a fourth value when the operating frequency is increased, the third value being smaller than the fourth value.
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| CN102595193A (en) * | 2011-01-05 | 2012-07-18 | 联发科技股份有限公司 | Video processing apparatus and method |
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| US7248387B2 (en) * | 2001-07-31 | 2007-07-24 | Umax Data Systems, Inc. | Scanning speed control device and method |
| TWI336201B (en) * | 2007-06-15 | 2011-01-11 | Holtek Semiconductor Inc | Circuit and method for regulating image clock |
| CN101431643B (en) * | 2007-11-06 | 2010-12-01 | 瑞昱半导体股份有限公司 | Apparatus and method for reducing video data output speed |
| JP4974930B2 (en) * | 2008-02-27 | 2012-07-11 | 株式会社リコー | Timing signal generator and image reading apparatus having the same |
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| JPS63201783A (en) * | 1987-02-18 | 1988-08-19 | Canon Inc | Picture processing device |
| CN102595193A (en) * | 2011-01-05 | 2012-07-18 | 联发科技股份有限公司 | Video processing apparatus and method |
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