CN112929127B

CN112929127B - Method and device for 5G NR parallel de-interleaving and de-rate matching

Info

Publication number: CN112929127B
Application number: CN202110100413.7A
Authority: CN
Inventors: 赵旭莹; 张达; 张丽雅; 石晶林
Original assignee: Institute of Computing Technology of CAS
Current assignee: Institute of Computing Technology of CAS
Priority date: 2021-01-26
Filing date: 2021-01-26
Publication date: 2022-05-24
Anticipated expiration: 2041-01-26
Also published as: CN112929127A

Abstract

The invention provides a parallel de-interleaving and de-rate matching method for a 5G NR LDPC code, which is used for storing received data packets into a ring buffer, wherein the ring buffer is divided into Q storage areas, Q is a modulation order, and the Q storage areas are regarded as Q rows of a virtual matrix storage, and the method comprises the following steps: step 100: determining the starting addresses of Q storage areas in the ring buffer according to the retransmission version number, the received rate matching length E, the modulation order Q, the filling bit length fill _ num and the starting address fill _ start; step 200: and sequentially storing the ith data in each Q bits of data into the ith storage area from the first bit of the received data packet until all the data of the data packet are stored into the ring buffer, wherein i is 0 … and Q-1. Based on the embodiment of the invention, the processing time delay can be reduced, the size of the internal memory can be reduced, and the problem of transmission efficiency caused by interaction with a bus can be avoided.

Description

Method and device for 5G NR parallel de-interleaving and de-rate matching

Technical Field

The present invention relates to wireless communication systems, and more particularly, to methods of deinterleaving and de-rate matching.

Background

LDPC rate matching in 5G NR comprises two processes: bit selection and bit interleaving. Bit interleaving is to rearrange the bit sequence of transmission by using interleaving coding technique, which will cause burst error of digital signal transmission, thus it can disperse and correct the concentrated burst error and improve the transmission characteristic of mobile communication. Bit selection is generally a method of increasing or decreasing the amount of data transmitted by encoded data for rate matching after encoding.

Currently, the conventional practice for deinterleaving and de-rate matching is a serial implementation. First deinterleaving is performed and then rate de-matching is performed. There are two ways to de-interleave. The first method is to store the received soft information in the chip according to rows, and perform rate de-matching on each row of data output after all data are received, see fig. 1. The second approach is to provide a memory external to the chip for rank mapping. The first method of deinterleaving needs to set a relatively large memory inside, and has relatively high power consumption, area and cost. The second method adopts an external memory, which can solve the problem of the oversize internal memory, but the bus access efficiency problem is accompanied, and the real-time requirement is difficult to meet.

Disclosure of Invention

The present invention is directed to the above-mentioned problem, and according to a first aspect of the present invention, a method for parallel deinterleaving and de-rate matching of a 5G NR LDPC code for storing received data packets in a circular buffer, wherein the circular buffer is divided into Q storage areas, Q being a modulation order, the Q storage areas being treated as Q rows of a virtual matrix storage, the method comprising:

step 100: determining the starting addresses of Q storage areas in the ring buffer according to the retransmission version number, the received rate matching length E, the modulation order Q, the filling bit length fill _ num and the starting address fill _ start;

step 200: and sequentially storing the ith data in each Q bits of data into the ith storage area from the first bit of the received data packet until all the data of the data packet are stored into the ring buffer, wherein i =0 … and Q-1.

In one embodiment of the present invention, wherein the circular buffer comprises a line counter k, one memory Pointer k for each of the Q memory regions, k = 0.

Step 210: initializing a line counter k to be 0, and respectively initializing a storage Pointer _ k of each line in the Q lines to be the initial address of the line;

step 220: storing the first data bit in the data packet into the storage position indicated by a storage Pointer _ k in the kth storage area indicated by the current line counter k;

step 230: incrementing a storage Pointer _ k to indicate a next storable position in the kth storage area;

if Pointer _ k is larger than the end address of the ring buffer, setting the Pointer _ k as the start address of the ring buffer;

step 231: incrementing the line counter k by 1, determining whether the line counter k is equal to Q,

if the line counter k is equal to Q, it is set to 0;

step 240: storing the next data bit to be processed into the storage position indicated by the storage Pointer Pointer _ k in the storage area indicated by the line counter k;

step 250: step 230 and step 240 are repeated until the reception of the data packet is completed.

In one embodiment of the present invention, the step 100 comprises:

calculating the length of each line L, L = E/Q,

calculating the starting address of the nth line, wherein n =0,1, … Q-1, and the calculating step is as follows:

when n =0, the starting address of the nth row is k0, where k0 is the corresponding starting address of the retransmission version,

when n >0, the nth row starting address Sn is:

if L > a, Sn = k0+ nL + fill _ num,

if L.ltoreq.a, Sn = k0+ nL,

where a = fill _ start-k0, fill _ start being the start address of the fill bits, and fill _ num being the length of the fill bits.

In one embodiment of the present invention, step 100 further comprises: if the calculated start address Sn is larger than the ring buffer length Ncb, recalculating the start address thereof, comprising the steps of:

calculate b = Sn% Ncb;

sn = b if b < = fill _ start;

if b > fill _ start, and b < = fill _ start + fill _ num, Sn = fill _ start + fill _ num;

sn = b + fill _ num if b > fill _ start + fill _ num.

In one embodiment of the present invention, when the padding bit length fill _ num is 0, the method for calculating the n-th line start address with the length L of each line is k0+ nL.

In one embodiment of the present invention, where the rate matching length E is greater than the circular buffer length Ncb, the repeatedly transmitted portions are combined in the circular buffer at the receiving end.

In an embodiment of the present invention, the method further includes: when rate matching is performed by puncturing or truncation, 0 bits are padded in the puncturing positions when data is received.

According to a second aspect of the present invention, there is provided a computer readable storage medium in which one or more computer programs are stored which, when executed by a processor, are for implementing the method for parallel deinterleaving and rate matching for a 5G NR LDPC code of the present invention.

According to a third aspect of the invention there is provided a computing system comprising: a storage device, and one or more processors; wherein the storage means is for storing one or more computer programs which when executed by the processor are for implementing the method for parallel de-interleaving and de-rate matching of 5G NR LDPC codes of the present invention.

Compared with the prior art, the invention has the advantages that the parallel operation of de-interleaving and de-rate matching is realized, the processing time delay can be reduced, the size of an internal memory is reduced, and the problem of transmission efficiency caused by interaction with a bus is avoided.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

FIG. 1 illustrates a serial implementation of deinterleaving and de-rate matching;

FIG. 2 illustrates bit selection in a circular buffer;

FIG. 3 shows a row list bit interleaving;

figure 4 shows a parallel de-interleaving and de-rate matching process.

Fig. 5 shows a general flow diagram of parallel deinterleaving and de-rate matching.

Fig. 6 shows a detailed flowchart of parallel deinterleaving and de-rate matching.

Detailed Description

In view of the problems in the background art, the inventors have studied and proposed a method for parallel deinterleaving and de-rate allocation.

The purpose of bit selection is to match the number of coded bits with the space-time resources, assuming that the length of the coded bits is N, the length of the data after bit selection is E, and the length of E is determined by the resources allocated by the higher layer. When the length of E is smaller than N, rate matching is usually performed by adopting a puncturing or truncation mode; when E is greater than N, rate matching is typically performed in a repeated manner, and fig. 2 shows versions of the circular buffer and the selected bits of length E are sent from the start address corresponding to version Rv 0.

Bit interleaving is to rearrange the data after bit selection in sequence so as to improve the anti-interference capability of the system. Bit interleaving in 5G NR is to divide E bits after bit selection into Q rows on average for storage, where the length of each row of data L = E/Q, where the number of rows Q of the matrix is equal to a modulation order, and the modulation orders supported in the current 5G NR protocol are 1,2,4,6, and 8. The process of bit interleaving is to output the data in the Q x L matrix in rows. Taking fig. 3 as an example, E =96, and the modulation order Q =4, the number of rows of the matrix memory is 4, and the length L =24 of each row. The sequence before bit interleaving is { A0, A1, A2, … A95}, and the sequence after bit interleaving is { A0, A24, A48, A72, A1, A25, A49, A73, …, A22, A46, A70, A94, A23, A47, A71, A95 }. Deinterleaving and de-rate matching are the inverse of bit selection and bit interleaving. And the order is opposite, bit selection is carried out firstly at the transmitting end, then bit interleaving is carried out, and bit interleaving is carried out firstly at the receiving end, and then bit selection is carried out. At the receiving end, after digital demodulation, each bit corresponds to a log-likelihood ratio, which is called soft information. The de-interleaving process is to write the received soft information with the length of E into the matrix memory according to columns and read the data according to rows so as to perform de-interleaving. Taking fig. 3 as an example, the received interleaved sequences { a0, a24, a48, a72, a1, a25, a49, a73, …, a22, a46, a70, a94, a23, a47, a71, and a95} are deinterleaved to { a0, a1, a2, … a95 }. And D, storing the de-interleaved sequence with the length of E into a circular buffer by de-rate matching. Taking fig. 3 as an example, the deinterleaved { a0, a1, a2, … a95} sequence is stored in the ring buffer. The data length before rate de-matching is E, the maximum number of allocated resource blocks is 275 due to the large transmission bandwidth in the 5G NR, the length of E is in direct proportion to the number of allocated resource blocks, and in extreme cases, the length of E reaches millions of orders. In addition, the received soft information is generally quantized with 6 bits, and if the received soft information is stored internally and then subjected to row-column matrix transformation, the storage cost is very high. Therefore, the present invention does not instantiate a real matrix memory for de-interleaving, but directly calculates the address of each received bit in the circular buffer and stores the address in the circular buffer directly. But in the calculation process the virtual matrix memory related concepts are used, such as row, column, length of the row etc. Taking fig. 3 as an example, the storage addresses of the received { a0, a24, a48, a72, a1, a25, a49, a73, …, a22, a46, a70, a94, a23, a47, a71, and a95} in the ring buffer are directly calculated.

Assuming that the modulation order Q =4, the number of rows of the matrix memory is 4, and the length L = E/Q of each row. The soft information sequence received by the matrix is { a0, b0, c0, d0, a1, b1, c1, d1, a2, b2, c2, d2, a3, b3, c3, d3. }, and the length of the soft information sequence is E, as shown in (r) of FIG. 4.

The encoded data is stored in a ring buffer of length Ncb and rate matching length E. The starting address of the bit selection changes with different retransmission version numbers, and the retransmission version numbers have four types: and the information with the length of E is sent by the Rv0, the Rv1, the Rv2 and the Rv3 according to the starting address determined by the retransmission version number. When the length of E is larger than Ncb, the data in the loop buffer is repeatedly transmitted. The corresponding start addresses k0 of different retransmission version numbers are shown in the following table, wherein Zc represents the extension factor of the LDPC code basic matrix.

Assuming that the retransmission version number is Rv0 and the start address is k0=0, the data storage form after the conventional de-interleaving is as shown in fig. 4, where S0 denotes the start address of the 0 th row of data in the matrix memory, S1 denotes the start address of the 1 st row of data, S2 denotes the start address of the 2 nd row of data, and S3 denotes the start address of the 3 rd row of data. The calculation formula of the starting addresses of different lines is as follows:

S0 = k0;

S1 = S0+L;

S2 = S0+2L;

S3 = S0+3L;

for example, in the data in fig. 3, the data received by the receiving end is { a0, a24, and a24 }, in (i) and (ii) of fig. 4, a24, b 24, c 24, and d 24 may correspond to a24, and a24, respectively, of fig. 3, and a24, b 24, c 24, and d 24 may correspond to a24, and a24 of fig. 3, respectively, while a24, b 24, c 24, and d 24 may correspond to a24, and a24, b 24, c 24, and d 24, respectively, and d 24 of fig. 3, may correspond to a24, and d 24, respectively, and a24 of fig. 3, respectively. So the columns of fig. 4 that achieve de-interleaving are presented. The final deinterleave is { A0, A1, A2, … A95 }. To facilitate de-interleaving in a column-out fashion, the starting address of each row at which a column in the circular buffer is to be dequeued is calculated. In e.g. fig. 4, the actual address storage space is not a matrix, but consecutive addresses (numbers), such as starting addresses k0=0x0000200, S1=0x0000218 (18 in hexadecimal is 24, which is the length of one row), S2=0x0000230 (30 in hexadecimal is 48, which is the length of two rows).

The circular buffer length is Ncb, and according to an embodiment of the present invention, the circular buffer may contain padding bits, such as the gray area in the third part of fig. 4, since the code block length in the protocol is calculated, and in fact, the length of the segmented code block may not reach the length calculated by the protocol, and is padded with NULL bits. The length of the padding bit is fill _ num, and the start address of the padding bit is fill _ start. When the rate is de-matched, the filling bit area is encountered, and the area needs to be skipped for storage. As shown in fig. 4, after the filling bit region is skipped, the start addresses corresponding to different rows of the matrix memory need to be adjusted, and the calculation method is explained in detail below. For the sake of distinction from the previous example, S0, S1, S2, S3 are no longer used to indicate the line data start address, but S4 is used to indicate the line 0 start address, S5 is used to indicate the line 1 start address, S6 is used to indicate the line 2 start address, and S7 is used to indicate the line 3 start address. The calculation formula of the starting addresses of different lines is as follows:

S4 = k0;

S5:

a=fill_start-k0

if L > a, S5 = S0+ L + fill _ num;

otherwise, S5 = S0+ L;

S6：

if 2L > a, S6 = S0+2L + fill _ num;

otherwise, S6 = S0+2L;

S7：

if 3L > a, S7 = S0+3L + fill _ num;

otherwise, S7 = S0+3L;

according to an embodiment of the present invention, since the ring buffer length is Ncb, if the calculated row start address S4, S5, S6, S7 is greater than Ncb, it needs to be further converted into a value less than Ncb, and then the start addresses of 0 th, 1 st, 2 nd, and 3 rd rows are respectively represented by S8, S9, S10, and S11, where S11 is calculated as follows using S7 as an example in S11:

if S7> Ncb, b = S7% Ncb

If b < = fill _ start, S11= b;

if b > fill _ start, and b < = fill _ start + fill _ num, S11= fill _ start + fill _ num;

if b > fill _ start + fill _ num, S11= b + fill _ num;

if S4, S5 and S6 are also larger than Ncb, the conversion relationships of S8/S4, S9/S5 and S10/S6 are the same as those of S11/S7.

When the retransmission version numbers are Rv1, Rv2, Rv3, the line start address calculation process is the same as Rv0, except that the value of k0 is different.

At this point, we have the row start address for parallel de-interleaving and de-rate matching.

In order to map the received data packets to the circular buffer, the present invention divides the circular buffer into Q memory areas, Q being the modulation order, said Q memory areas being treated as Q rows of the virtual matrix memory, which Q memory areas may overlap. The present invention needs to set a line counter k, k = 0.,. Q-1, and set a storage Pointer for each line, where the storage Pointer of the kth line is denoted as Pointer _ k, for example, the storage Pointer of the 3 rd line is denoted as Pointer _3, k denotes a line in which the currently received data bit should be stored, and Pointer _ k denotes a specific storage location of the currently received data bit in the line. Before receiving data, the line counter k is set to 0 and the memory pointer for each line is initialized to the starting address of the line calculated in the manner described above. The first data bit in the packet will be stored at the start address of row 0 as indicated by k =0 and Pointer _ 0.

To implement a column out, each time a data bit is received, the value of the current row counter k indicates the row in the matrix storage to which the data bit should be mapped, then the row counter is incremented by 1 for the next received bit, and if the value of the row counter incremented by 1 equals Q, the row counter is set to 0. That is, the i-th data in each Q-th data is stored in the i-th storage area from the first bit of the received data packet until all the data of the data packet is stored in the ring buffer, wherein i =0 … and Q-1. A general flow chart of parallel deinterleaving and de-rate matching is shown in fig. 5.

After determining the row for the received data bit, the specific memory location is indicated by the memory Pointer k of the row, and after processing the received data bit, the address for the next received data bit mapped to the row is calculated. If no padding area is encountered, add 1 to Pointer _ k, if a padding area is encountered, need to skip the padding area, add file _ num to Pointer _ k. If Pointer _ k is greater than the ending address of the ring buffer, point _ k is set to the starting address of the ring buffer, e.g., when Pointer _2 of the second row indicated by S6 is greater than the ending address of the ring buffer in fig. 4, point _2 is set to the starting address of the ring buffer. According to the method, the data bits in the received data packet are processed sequentially until all the data bits in the data packet are processed.

For example, when Q =4, the received 1 st bit is mapped to the start address of the 0 th row, the received 2 nd, 3 th and 4 th bits are mapped to the start addresses of the 1 st, 2 nd and 3 th rows, respectively, the received 5 th bit is mapped to the start address of the 0 th row plus 1, the received 6 th bit is mapped to the start address of the 1 st row plus 1, the received 10 th bit is mapped to the start address of the 1 st row plus 2, and if the start address of the 1 st row plus 2 is a padding area and the length of the padding area is 1, the received 10 th bit should not be mapped to the start address of the 1 st row plus 2 but should be mapped to the start address of the 1 st row plus 3. A detailed flow diagram of parallel deinterleaving and de-rate matching is shown in fig. 6.

If the length of the circular buffer is 100 bits, 10-19 bits are filled with a filling area (the filling area is 10 bits long in total), if E is 120, when the circular buffer is full, only 90 bits are stored, the remaining 30 bits (120-90 = 30) have a merging problem, of the remaining 30 bits, 91-100 bits after the column is extracted are merged with the 0-9 bits of the circular buffer respectively, and of the remaining 30 bits, 101-120 bits after the column is extracted need to skip the filling area and then are merged with the 20-39 bits of the circular buffer respectively.

The combining method is the same as the combining method after receiving a plurality of version data in the HARQ process, and the combining operation in the mapping process solves the self-combining problem when the rate matching length E is larger than the length Ncb of the circular buffer. When all the received data are written into the circular buffer, the parallel de-interleaving and de-rate matching process is finished.

When the rate matching is performed by adopting a punching or truncation mode, 0 bit is filled in a punching position when data is received, and the same method as the method is used for sequentially mapping according to the row addresses, namely, the 0 th row of data is mapped firstly, and then the 1 st row of data, the 2 nd row of data and the 3 rd row of data are mapped. Since the length of E is not greater than Ncb, data in the circular buffer is not repeatedly transmitted, and the receiving end does not need to merge the repeatedly transmitted data.

The previous description is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Moreover, all or a portion of any aspect and/or embodiment may be utilized with all or a portion of any other aspect and/or embodiment, unless stated otherwise. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for parallel de-interleaving and de-rate matching of a 5G NR LDPC code for storing received packets into a circular buffer, wherein the circular buffer is divided into Q memory regions, Q being a modulation order, the Q memory regions being treated as Q rows of a virtual matrix memory, the circular buffer comprising a row counter k, each of the Q memory regions having a memory Pointer pointerk, k = 0.

step 200: sequentially storing the ith data in each Q bits of data to the ith storage area from the first bit of the received data packet until all data of the data packet is stored in the ring buffer, wherein i =0 …, Q-1, and the step 200 comprises:

if the line counter k is equal to Q, it is set to 0;

2. The method of claim 1, the step 100 comprising:

calculating the length of each line L, L = E/Q,

calculating an nth row start address, wherein n =0,1, … Q-1, the step of calculating the nth row start address being:

when n =0, the starting address of the nth row is k0, where k0 is the starting address corresponding to the retransmission version, and when n >0, the starting address Sn of the nth row is:

if L > a, Sn = k0+ nL + fill _ num,

if L.ltoreq.a, Sn = k0+ nL,

3. The method of claim 2, step 100 further comprising: if the calculated start address Sn is larger than the ring buffer length Ncb, recalculating the start address thereof, comprising the steps of:

calculate b = Sn% Ncb;

sn = b if b < = fill _ start;

sn = b + fill _ num if b > fill _ start + fill _ num.

4. The method of claim 2, wherein the method of calculating the start address of the nth row with length L of each row is k0+ nL when the padding bit length fill _ num is 0.

5. The method of claim 1, wherein the repeatedly transmitted parts are combined in a circular buffer at a receiving end when a rate matching length E is greater than a circular buffer length Ncb.

6. The method of claim 1, further comprising: when rate matching is performed by puncturing or truncation, 0 bits are padded in the puncturing positions when data is received.

7. A computer-readable storage medium, in which one or more computer programs are stored which, when being executed by a processor, are adapted to carry out the method of any one of claims 1-6.

8. A computing system, comprising:

a storage device, and one or more processors;

wherein the storage means is for storing one or more computer programs which, when executed by the processor, are for implementing the method of any one of claims 1-6.