CN112929001A - Differential amplifier circuit - Google Patents
Differential amplifier circuit Download PDFInfo
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- CN112929001A CN112929001A CN202110143642.7A CN202110143642A CN112929001A CN 112929001 A CN112929001 A CN 112929001A CN 202110143642 A CN202110143642 A CN 202110143642A CN 112929001 A CN112929001 A CN 112929001A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
Abstract
The divisional application discloses a differential amplification circuit, including: forming a first transistor and a second transistor of a differential pair structure; a third transistor, wherein the grid-drain parasitic capacitance of the third transistor is connected with the grid-drain parasitic capacitance of the first transistor in parallel and has opposite polarity; a fourth transistor, the grid-drain parasitic capacitance of which is connected in parallel with the grid-drain parasitic capacitance of the second transistor and the polarities of which are opposite; the first end of the primary coil of the second transformer is coupled to the first end of the secondary coil of the first transformer and the control end of the first transistor through the third transistor, and the second end of the primary coil of the second transformer is coupled to the second end of the secondary coil of the first transformer and the control end of the second transistor through the fourth transistor.
Description
The application is a divisional application, the application number of the original application is 201710743761.X, the application date is 2017, 08 and 25, and the name of the invention is 'differential amplification circuit'.
Technical Field
The present invention relates to the field of electronic circuit technology, and more particularly, to a differential amplifier circuit.
Background
A Complementary Metal Oxide Semiconductor (CMOS) transistor has an increased parasitic effect at high frequencies, and the main reason for this is that the influence of the gate-drain parasitic capacitance Cgd of the MOS transistor becomes large, and the reverse isolation performance of the transistor becomes poor. For example, in the millimeter wave amplifier, the gate-drain parasitic capacitance of the transistor may reduce the stability and the maximum obtainable gain of the millimeter wave amplifier, and therefore, how to reduce the reverse coupling caused by the gate-drain parasitic capacitance Cgd and how to ensure the stability of the millimeter wave amplifier become a core difficulty in the design process of the millimeter wave amplifier.
The millimeter-wave amplifier generally adopts a differential architecture. In order to improve the stability and gain of the millimeter wave amplifier, some prior arts adopt a cross-coupling capacitance neutralization method. Fig. 1 shows a circuit schematic of a prior art millimeter wave amplifier. As shown in fig. 1, in the prior art, by utilizing the characteristics of a differential structure, neutralization capacitors Cx1 and Cx2 are added to a millimeter wave amplifier, a first terminal of the capacitor Cx1 receives a first input signal Vin1, a second terminal of the capacitor Cx1 receives a second output signal Vout2, a first terminal of the capacitor Cx2 receives a second input signal Vin2, and a second terminal of the capacitor Cx2 receives a first output signal Vout 1. The first input signal Vin1 and the second input signal Vin2 are provided by the input transformer U01, the first output signal Vout1 and the second output signal Vout2 are provided to the output transformer U02, when the first input signal Vin1 and the second input signal Vin2 are differential signals with opposite polarities to each other, and the first output signal Vout1 and the second output signal Vout2 are differential signals with opposite polarities to each other, the gate-drain parasitic capacitance of the capacitance Cx1 with respect to the first amplification tube M01 (labeled as the capacitance Cgd01 in fig. 1) may be equivalent to a capacitance with a negative capacitance value, and the gate-drain parasitic capacitance of the capacitance Cx2 with respect to the gate-drain parasitic capacitance of the second amplification tube M02 (labeled as the capacitance Cgd 8 in fig. 1) may be equivalent to a capacitance with a negative capacitance value, so that the gate-drain parasitic capacitances of the first amplification tube M01 and the second amplification tube M02 may be cancelled by setting the capacitance Cx1 and the capacitance Cx2, thereby reducing reverse gate-drain parasitic capacitance, and improving stability.
In the prior art, the capacitors Cx1 and Cx2 are usually implemented by Metal-oxide-Metal (MOM) capacitors, and the capacitors of this type have a large area, which results in a long connection line with a transistor, and therefore, a large parasitic inductance is generated, and accurate modeling in a millimeter wave frequency band is difficult. In addition, since the MOM capacitance varies greatly with the process and the variation tendency is not consistent with the variation tendency of the gate-drain parasitic capacitance Cgd of the transistor, it is difficult to ensure the effect that the gate-drain parasitic capacitance Cgd of the transistor in the millimeter-wave amplifier is cancelled in the process of mass production.
Meanwhile, in the prior art, the method for neutralizing the practical cross-coupling capacitance has side effects. The neutralization capacitances Cx1 and Cx2 can cancel the gate-drain parasitic capacitances in the first amplifier tube M01 and the second amplifier tube M02 only when the millimeter wave amplifier operates in the differential mode, that is, when the polarities of the first input signal and the second input signal of the millimeter wave amplifier are opposite. However, when the millimeter wave amplifier operates in the common mode, that is, the polarities of the first input signal and the second input signal of the millimeter wave amplifier are the same, the neutralization capacitances Cx1 and Cx2 are in the same polarity direction as the gate-drain parasitic capacitances of the first amplifying tube M01 and the second amplifying tube M02, and not only the gate-drain parasitic capacitances of the first amplifying tube M01 and the second amplifying tube M02 are not cancelled, but also the gate charge amounts of the first amplifying tube M02 and the second amplifying tube M02 are increased, thereby conversely causing the reverse coupling phenomenon of the millimeter wave amplifier to be enhanced. Additional measures are therefore required to ensure the stability of the millimeter-wave amplifier in the common mode.
Disclosure of Invention
In order to solve the problems in the prior art, the present invention provides a differential amplifier circuit, which can neutralize or even cancel the gate-drain parasitic capacitance of the differential pair transistors in the signal environment of the differential mode and the common mode, thereby reducing the reverse coupling effect, improving the stable gain of the differential amplifier, improving the stability of the differential amplifier, and being more beneficial to the realization of mass production.
The present disclosure provides a differential amplification circuit, comprising: a first transistor and a second transistor forming a differential pair structure, a control terminal of the first transistor being a first input node to receive a first input signal, a control terminal of the second transistor being a second input node to receive a second input signal, a first path terminal of the first transistor being a second output node to provide a second output signal, a first path terminal of the second transistor being a first output node to provide a first output signal; a third transistor having a control terminal and a first path terminal, a parasitic capacitance being formed between the control terminal and the first path terminal of the third transistor, the parasitic capacitance being connected in parallel to a parasitic capacitance formed between the control terminal and the first path terminal of the third transistor; a fourth transistor having a control terminal connected to the first path terminal to form a parasitic capacitance therebetween, the parasitic capacitance being connected in parallel to a parasitic capacitance formed between the control terminal of the second transistor and the first path terminal; a first transformer having a primary winding receiving an input voltage, a secondary winding having a first end for providing the first input signal, and a second end for providing the second input signal; a second transformer having a primary winding with a first end for receiving the first output signal, a primary winding with a second end for receiving the second output signal, and a secondary winding for providing an output signal. Wherein a first terminal of the primary winding of the second transformer is directly coupled to the first terminal of the secondary winding of the first transformer and the control terminal of the first transistor via the third transistor, and a second terminal of the primary winding of the second transformer is directly coupled to the second terminal of the secondary winding of the first transformer and the control terminal of the second transistor via the fourth transistor.
In some alternative embodiments, the first pass terminal and the second pass terminal of the third transistor are coupled to be coupled to one of the first input node and the first output node, and the control terminal of the third transistor is coupled to the other of the first input node and the first output node; a first path terminal and a second path terminal of the fourth transistor are connected to be connected to one of the second input node and the second output node, and a control terminal of the fourth transistor is connected to the other of the second input node and the second output node.
In some optional embodiments, the channel length and width dimensions of the first transistor and the second transistor are the same, the channel length and width dimensions of the third transistor and the fourth transistor are the same, and a capacitance value formed by the third transistor between the control terminal and the first pass terminal thereof is equal to a capacitance value formed by the first transistor between the control terminal and the first pass terminal thereof.
In some optional embodiments, a channel width-to-length ratio of the third transistor is approximately equal to two to three times a channel width-to-length ratio of the first transistor, and a channel width-to-length ratio of the fourth transistor is approximately equal to two to three times a channel width-to-length ratio of the second transistor.
In some alternative embodiments, the channel lengths or the channel widths of the first to fourth transistors are the same.
In some optional embodiments, the first to fourth transistors are respectively formed by a plurality of MOSFETs, the first transistor includes n MOSFETs connected in parallel, the second transistor includes n MOSFETs connected in parallel, the third transistor includes m MOSFETs connected in parallel, and the fourth transistor includes m MOSFETs each having the same channel width, where n and m are natural numbers equal to or greater than 1, and n is approximately two to three times as large as m.
In some alternative embodiments, the first transistor is disposed adjacent to the third transistor, the first transistor and each of the MOSFETs in the third transistor are arranged in a row with the first side and the second side of the row facing each other, channels of the MOSFETs are parallel to each other, a gate of each of the MOSFETs in the first transistor is connected to a gate of each of the MOSFETs in the third transistor at the first side of the row, a source of each of the MOSFETs in the first transistor is connected at the first side of the row, a drain of each of the MOSFETs in the first transistor is connected at the second side of the row, and a source and a drain of each of the MOSFETs in the third transistor are connected at the second side of the row.
In some optional embodiments, the second transistor is disposed adjacent to the fourth transistor, the second transistor and each of the MOSFETs in the fourth transistor are arranged in a row with the first side and the second side of the row opposite to each other, channels of the respective MOSFETs are parallel to each other, a gate of each of the MOSFETs in the second transistor is connected to a gate of each of the MOSFETs in the fourth transistor at the first side of the row, a source of each of the MOSFETs in the second transistor is connected at the first side of the row, a drain of each of the MOSFETs in the fourth transistor is connected at the second side of the row, and a source and a drain of each of the MOSFETs in the fourth transistor are connected at the second side of the row.
In some alternative embodiments, each MOSFET is of an N-channel type, and the second path terminal of the first transistor and the second path terminal of the second transistor are connected to ground.
In some optional embodiments, a first path terminal of the third transistor is grounded through a second resistor, a second path terminal of the third transistor is connected to the first output node, and a control terminal of the third transistor is connected to the control terminal of the first transistor; and a first path end of the fourth transistor is grounded through a third resistor, a second path end of the fourth transistor is connected with the second output node, and a control end of the fourth transistor is connected with a control end of the second transistor.
In some optional embodiments, the first input signal and the second input signal are common mode signals with the same polarity, and the differential amplifying circuit further includes: the first end of the first capacitor is connected with the reference ground, the second end of the first capacitor is connected with the first end of the first resistor and receives bias voltage, and the second end of the first resistor is connected with a center tap of a secondary coil of the first transformer; and a second resistor and a second capacitor connected in series between a center tap of the primary coil of the second transformer and a reference ground, the center tap of the primary coil of the second transformer receiving a supply voltage.
In some alternative embodiments, the first transistor and the third transistor are arranged adjacently, and the control end of the first transistor and the control end of the third transistor are connected by a first connection (G1), and the extension direction of the first connection is perpendicular to the extension direction of the channel lengths of the first transistor and the third transistor; the second transistor and the fourth transistor are adjacently arranged, the control end of the second transistor and the control end of the fourth transistor are connected through a second connecting line (G2), and the extending direction of the second connecting line is perpendicular to the extending direction of the channel lengths of the second transistor and the fourth transistor.
According to the differential amplification circuit provided by the embodiment of the invention, the transistors are arranged between the input end and the output end of the differential pair transistor in a crossed manner, and the gate-drain parasitic capacitance of the differential pair transistor can be neutralized or even counteracted under the signal environment of a differential mode and a common mode, so that the reverse coupling effect of the differential pair transistor is reduced, and the stable gain and the stability of the differential amplifier are improved. Compared with the prior art, the differential amplification circuit provided by the embodiment of the invention has smaller dependence on the process, so that the matching between the transistor for decoupling and the gate-drain parasitic capacitance of the differential pair transistor can be ensured in the process of mass production, thereby being beneficial to weakening the parasitic effect and improving the product quality. In some preferred embodiments, parasitic inductance caused by additional connection traces can be avoided by compactly arranging the active regions of the transistors in the differential amplifier.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a circuit schematic of a prior art millimeter wave amplifier.
Fig. 2 shows a circuit schematic of a differential amplifier circuit according to a first embodiment of the present invention.
Fig. 3 shows a circuit schematic of a differential amplifier circuit according to a second embodiment of the present invention.
Fig. 4a and 4b are schematic diagrams showing partial structures of differential amplifier circuits according to first and second embodiments of the present invention.
Fig. 5 shows a partial circuit schematic diagram of an alternative embodiment of the differential amplifying circuit of the first and second embodiments of the present invention.
Fig. 6 shows a partial circuit schematic diagram of another alternative embodiment of the differential amplifying circuit of the first and second embodiments of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The following detailed description refers to the accompanying drawings.
Fig. 2 shows a circuit schematic of a differential amplifier circuit according to a first embodiment of the present invention.
As shown in fig. 2, the differential amplifying circuit according to the first embodiment of the present invention includes first to fourth transistors M10 to M40, and a first transformer U10 and a second transformer U20. In this embodiment, the first Transistor M10 to the fourth Transistor M40 are N-channel Metal-Oxide-Semiconductor Field-Effect transistors (MOSFETs).
The primary winding of the first transformer U10 receives an externally provided input voltage Vin, and both ends of the secondary winding of the first transformer U10 provide a first input signal Vin1 and a second input signal Vin2, respectively. The first input signal Vin1 has a common-mode component Vcm1 and a differential-mode component vi1, the second input signal Vin2 also has a common-mode component Vcm2 and a differential-mode component vi2, the common-mode component Vcm1 of the first input signal Vin1 is equal to the common-mode component Vcm2 of the second input signal Vin2, and the differential-mode component vi1 of the first input signal Vin1 is opposite in phase to the differential-mode component vi2 of the second input signal. In this embodiment, the first input signal Vin1 and the second input signal Vin2 are differential signals with different polarities, and the differential amplifier operates in a differential mode.
The primary winding of the second transformer U20 receives the first output signal Vout1 and the second output signal Vout2 at its two ends, respectively, and the secondary winding of the second transformer U20 provides the output signal Vout to the load.
The first transistor M10 and the second transistor M20 form a differential pair structure, a control terminal (gate) of the first transistor M10 serves as a first input node G1 to receive the first input signal Vin1, a control terminal (gate) of the second transistor M20 serves as a second input node G2 to receive the second input signal Vin2, a first pass terminal (drain) of the first transistor M10 serves as a second output node D1 to provide the second output signal Vout2, a first pass terminal (drain) of the second transistor M20 serves as a first output node D2 to provide the first output signal Vout1, and a second pass terminal (source) of the first transistor M10 is connected to the second pass terminal (source) of the second transistor M20 and connected in parallel to a reference ground gnd or other low-potential reference voltage. Thus, the first transistor M10 and the second transistor M20 amplify the differential | vi1-vi2| of the first input signal Vin1 and the second input signal Vin2 to obtain a first output signal Vout1 and a second output signal Vout2 that are differential signals of each other.
A first pass terminal (drain) of the third transistor M30 and a second pass terminal (source) thereof are coupled to be coupled to the first output node D2, and a control terminal (gate) of the third transistor M30 is coupled to the first input node G1. The source and drain of the third transistor M30 and the drain of the first transistor M10 are respectively connected to two ends of the primary coil of the second transformer to receive the first output signal Vout1 and the second output signal Vout2 which are differential signals with each other, and the gate of the third transistor M30 is connected to the gate of the first transistor M10.
The first path terminal (drain) of the fourth transistor M40 and the second path terminal (source) thereof are connected to be connected to the second output node D1, and the control terminal (gate) of the fourth transistor M40 is connected to the second input node G2. The source and the drain of the fourth transistor M40 and the drain of the second transistor M20 are respectively connected to two ends of the primary coil of the second transformer U20 to receive the first output signal Vout1 and the second output signal Vout2 which are differential signals with each other, and the gate of the fourth transistor M40 is connected to the gate of the second transistor M20.
In this embodiment, since the polarities of the first input signal Vin1 and the second input signal Vin2 are opposite, and the gate charge of the third transistor M30 and the gate charge of the first transistor M10 are opposite, the gate charge of the third transistor M30 can be similar to or even identical to the gate charge of the first transistor M10 by matching the size of the third transistor M30 and the size of the first transistor M10, so that the gate-drain parasitic capacitance Cgd10 of the third transistor M30 relative to the first transistor M10 can be equivalent to a capacitance with a negative capacitance value, and the gate-drain parasitic capacitance d10 of the first transistor M10 is equivalent to being neutralized, that is, the reverse coupling problem caused by the gate-drain parasitic capacitance Cgd10 of the first transistor M10 can be eliminated or reduced, so as to enhance the stability of the differential amplifier circuit. Similarly, the gate charge of the third transistor M30 is opposite to the gate charge of the second transistor M20, and the gate charge of the fourth transistor M40 can be similar to or even identical to the gate charge of the second transistor M20 by matching the size of the fourth transistor M40 with the size of the second transistor M20, so that the gate-drain parasitic capacitance Cgd20 of the fourth transistor M40 relative to the second transistor M20 can be equivalent to a capacitance with a negative capacitance value, and the gate-drain parasitic capacitance Cgd20 of the second transistor M20 is equivalent to being neutralized, that is, the problem of coupling oscillation caused by the gate-drain parasitic capacitance Cgd20 of the second transistor M20 can be eliminated or reduced, so as to enhance the stability of the differential amplifier circuit.
However, when the polarities of the first input signal Vin1 and the second input signal Vin2 are the same, that is, when the differential amplifier operates in the common mode, the gate charge of the third transistor M30 has the same polarity as the gate charge of the first transistor M10, the gate charge of the fourth transistor M40 has the same polarity as the gate charge of the second transistor M20, therefore, the gate-drain parasitic capacitance Cgd10 of the third transistor M30 with respect to the first transistor M10 corresponds to an equivalent capacitance of positive capacitance, the gate-drain parasitic capacitance Cgd20 of the fourth transistor M40 with respect to the second transistor M20 corresponds to an equivalent capacitance of positive capacitance, that is, in the common mode of the differential amplifier, the third transistor M30 and the fourth transistor M40 would instead increase the gate charge of the differential pair, thereby aggravating the parasitic effect of the gate-drain parasitic capacitance and making the stability and gain of the differential amplification circuit worse.
In order to enable the differential amplifier circuit to stably operate in the common mode and to eliminate the parasitic effect of the differential pair transistors, a differential amplifier circuit according to a second embodiment of the present invention will be described below.
Fig. 3 shows a circuit schematic of a differential amplifier circuit according to a second embodiment of the present invention.
As shown in fig. 3, the differential amplifier circuit according to the second embodiment of the present invention operates in a common mode, i.e., the polarities of the first input signal Vin1 and the second input signal Vin2 are the same. The differential amplifier circuit of the present embodiment also includes first to fourth transistors M10 to M40 and first and second transformers U10 and U20, and unlike the first embodiment described above, the differential amplifier circuit of the second embodiment of the present invention further includes a decoupling capacitor Cde1 and a resistor Rde1 connected in series between the center tap of the secondary winding of the first transformer U10 and ground, and a decoupling capacitor Cde2 and a resistor Rde2 connected in series between the center tap of the primary winding of the second transformer U20 and ground. The decoupling capacitors Cde1 and Cde2 and the resistors Rde1 and Rde2 are used for reducing the Q value and the loss of the common mode path of the differential amplifier circuit, so that the differential amplifier circuit can be kept stable and has high gain when the differential amplifier circuit operates in the common mode. Specifically, as shown in fig. 3, a center tap of the secondary coil of the first transformer U10 is connected to a first terminal of a resistor Rde1, a second terminal of the resistor Rde1 is connected to a first terminal of a decoupling capacitor Cde1 and receives a bias voltage Vbias, and a second terminal of the decoupling capacitor Cde1 is grounded; a center tap of the primary coil of the second transformer U20 is connected to a first terminal of the resistor Rde2 and receives the power supply voltage VDD, a second terminal of the resistor Rde2 is connected to a first terminal of the decoupling capacitor Cde2, and a second terminal of the decoupling capacitor Cde2 is grounded.
Other circuits of the second embodiment of the present invention are the same as those of the differential amplifier circuits of the above embodiments, and are not described herein again.
In the differential amplifier circuits according to the first and second embodiments of the present invention, as shown in fig. 2 and 3, since the source and the drain of the third transistor M30 are connected, and the third transistor M30 is always in the cut-off region or the linear region, the gate parasitic capacitance Cg30 of the third transistor M30 is basically obtained by connecting the gate-source parasitic capacitance Cgs30 and the gate-drain parasitic capacitance Cgd30 of the third transistor M30 in parallel, and the gate-source parasitic capacitance Cgs30 is approximately equal to the gate-drain parasitic capacitance Cgd30, that is, Cg30 ═ Cgd30+ Cgs30 ≈ 2 × Cgd30, so it can be seen that when the channel area of the third transistor M30 is approximately half of the channel area of the first transistor M10, the third transistor M30 is connected to the gate parasitic capacitance Cg30 between the first input node in1 and the first output node out1, which is approximately equal to the gate parasitic capacitance Cgd10 of the first transistor M10. In order to neutralize the gate-drain parasitic capacitance Cgd10 of the first transistor M10, the channel length L3 of the third transistor M30 may be set to be the same as the channel length L1 of the first transistor M10, and the channel width W3 of the third transistor M30 may be set approximately to 1/3 to 1/2 of the channel width W1 of the first transistor M10; or the channel width W3 of the third transistor M30 is set to be the same as the channel width W1 of the first transistor M10, and the channel length L3 of the third transistor M30 is set to be approximately 1/2 to 1/3 of the channel length L1 of the first transistor M10.
Similarly, since the source and the drain of the fourth transistor M40 are connected, the fourth transistor M40 is always in an off-region or a linear region, and in order to neutralize the gate-drain parasitic capacitance Cgd20 of the second transistor M20, the channel length L4 of the fourth transistor M40 may be set to be the same as the channel length L2 of the second transistor M20, and the channel width W4 of the fourth transistor M40 may be set approximately to be 1/3 to 1/2 of the channel width W2 of the second transistor M20; or the channel width W4 of the fourth transistor M40 is set to be the same as the channel width W2 of the second transistor M20, and the channel length L4 of the fourth transistor M40 is set to be approximately 1/2 to 1/3 of the channel length L2 of the second transistor M20.
Fig. 4a and 4b are schematic diagrams showing partial structures of differential amplifier circuits according to first and second embodiments of the present invention.
According to the above analysis, as a preferred embodiment, as shown in fig. 4a, the first transistor M10 is formed by connecting n transistors M11 to M1n in parallel, the third transistor M30 is formed by connecting M transistors M31 to M3M in parallel, where n and M are both natural numbers equal to or greater than 1, n is about two to three times (e.g., n is 10, M is 4) of M, the channel widths of the transistors M11 to M1n and the transistors M31 to M3M are equal, the channel lengths are equal, and the length directions of the channels of the respective transistors in the first and third transistors are parallel to each other, the respective transistors are arranged in a row along the width direction of the channel, and the third transistor M30 is disposed adjacent to the first transistor M10. Similarly, as shown in fig. 4b, the second transistor M20 is formed by connecting n transistors M21 to M2n in parallel, the fourth transistor M40 is formed by connecting M transistors M41 to M4M in parallel, the transistors M11 to M1n, the transistors M21 to M2n, the transistors M31 to M3M, and the transistors M41 to M4M are equal in channel width and channel length, and the length directions of the channels of the respective transistors of the second and fourth transistors are parallel to each other, the respective transistors are arranged in a row along the width direction of the channel, and the fourth transistor M40 is disposed adjacent to the second transistor M20. Further, the length directions of the channels of the respective transistors in the first to third transistors are parallel to each other, the respective transistors are arranged in a row along the width direction of the channels, the third transistor M30 is disposed adjacent to the first transistor M10 and the fourth transistor M40, for example, and the third transistor M30 and the fourth transistor M40 are located between the first transistor M10 and the second transistor M20.
As a specific example, as shown in fig. 4a, the drain connections of the n transistors in the first transistor M10 and the Source and drain connections of the M transistors in the third transistor M30 are located on the first side of the row where each transistor is located, the gate connections of the M transistors in the third transistor M30 and the n transistors in the first transistor M10 are located on the second side of the row where each transistor is located, and the Source connections Source _ cm of each transistor in the first transistor M10 are located on the second side of the row where each transistor is located; similarly, as shown in fig. 4b, the connections of the sources and drains of the M transistors in the fourth transistor M40 and the connections of the drains of the n transistors in the second transistor M20 are located on the first side of the row in which each transistor is located, the connections of the gates of the M transistors in the fourth transistor M20 and the connections of the sources _ cm of the respective transistors in the second transistor M20 are located on the second side of the row in which each transistor is located. The first side and the second side of the row of the transistors are opposite, and the direction of each drain connection line, the connection line of the source and the drain, the connection line of the source and the grid is vertical to the length extension direction of each channel.
It can be seen that the transistors are used to replace the MOM capacitors, so that the active regions of the seal-up amplifier can be arranged very tightly, thereby not only reducing the area of the integrated circuit, but also avoiding the parasitic inductance caused by additional connecting wires.
Fig. 5 shows a partial circuit schematic diagram of an alternative embodiment of the differential amplifying circuit of the first and second embodiments of the present invention.
In the above-described first and second embodiments, the source and drain of the third transistor M30 are connected to be connected to the first output node D2, and the gate of the third transistor M30 is connected to the first input node G1, so that the gate-drain parasitic capacitance of the first transistor M10 can be cancelled by the third transistor M30 as a capacitance; the source and drain of the fourth transistor M40 are connected to be connected to the second output node D1, and the gate of the fourth transistor M40 is connected to the second input node G2, so that the gate-drain parasitic capacitance of the second transistor M20 can be cancelled by the fourth transistor M40 as a capacitance. As an alternative embodiment, as shown in fig. 5, the connection of the third transistor M30 and the fourth transistor M40 may be changed, that is: the drain and source of the third transistor M30 are connected to be connected to the first input node G1, and the gate of the third transistor M30 is connected to the first output node D2; the drain of the fourth transistor M40 and its source are connected to the second input node G2, and the gate of the fourth transistor M40 is connected to the second output node D1.
It should be noted that the differential pair transistors (the first transistor and the second transistor) and the third transistor and the fourth transistor for decoupling according to the embodiment of the present invention are not limited to N-channel devices, and may be P-channel devices.
Fig. 6 shows a further alternative embodiment of the first and second embodiments of the invention.
In the above-described first and second embodiments, the source and drain of the third transistor M30 are connected to be connected to the first output node D2, and the gate of the third transistor M30 is connected to the first input node G1, so that the gate-drain parasitic capacitance of the first transistor M10 can be cancelled by the third transistor M30 as a capacitance; the source and drain of the fourth transistor M40 are connected to be connected to the second output node D1, and the gate of the fourth transistor M40 is connected to the second input node G2, so that the gate-drain parasitic capacitance of the second transistor M20 can be cancelled by the fourth transistor M40 as a capacitance. As another alternative, as shown in fig. 6, the source of the third transistor M30 is grounded through a resistor R30 with a large resistance, and the drain of the third transistor M30 is connected to the first output node D2, so that the gate-drain capacitance Cgd30 of the third transistor M30 can also be neutralized with the gate-drain capacitance Cgd10 of the first transistor M10, and the influence of the third transistor M30 on the first output voltage Vout1 is small because the resistance of the resistor R30 is large; similarly, the source of the fourth transistor M40 is grounded through a resistor R40 with a large resistance, and the drain of the fourth transistor M40 is connected to the second output node D1, so that the gate-drain capacitance Cgd40 of the fourth transistor M40 can also be neutralized with the gate-drain capacitance Cgd20 of the second transistor M20, and the resistance of the resistor R40 is large, so that the fourth transistor M40 has little influence on the second output voltage Vout 2. The rest of the circuit parts are the same as the first embodiment or the second embodiment, and are not described again here.
According to the differential amplification circuit provided by the embodiment of the invention, the transistors are arranged between the input end and the output end of the differential pair transistor in a crossed manner, and the gate-drain parasitic capacitance of the differential pair transistor can be neutralized or even counteracted under the signal environment of a differential mode and a common mode, so that the reverse coupling effect of the differential pair transistor is reduced, and the stable gain and the stability of the differential amplifier are improved. Compared with the prior art, the differential amplification circuit provided by the embodiment of the invention has smaller dependence on the process, so that the matching between the transistor for decoupling and the gate-drain parasitic capacitance of the differential pair transistor can be ensured in the process of mass production, thereby being beneficial to weakening the parasitic effect and improving the product quality.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (12)
1. A differential amplification circuit, comprising:
a first transistor and a second transistor forming a differential pair structure, a control terminal of the first transistor being a first input node to receive a first input signal, a control terminal of the second transistor being a second input node to receive a second input signal, a first path terminal of the first transistor being a second output node to provide a second output signal, a first path terminal of the second transistor being a first output node to provide a first output signal;
a third transistor having a control terminal and a first path terminal, a parasitic capacitance being formed between the control terminal and the first path terminal of the third transistor, the parasitic capacitance being connected in parallel to a parasitic capacitance formed between the control terminal and the first path terminal of the third transistor;
a fourth transistor having a control terminal connected to the first path terminal to form a parasitic capacitance therebetween, the parasitic capacitance being connected in parallel to a parasitic capacitance formed between the control terminal of the second transistor and the first path terminal;
a first transformer having a primary winding receiving an input voltage, a secondary winding having a first end for providing the first input signal, and a second end for providing the second input signal;
a second transformer having a primary winding with a first end for receiving the first output signal, a primary winding with a second end for receiving the second output signal, a secondary winding for providing an output signal,
wherein a first terminal of the primary winding of the second transformer is directly coupled to the first terminal of the secondary winding of the first transformer and the control terminal of the first transistor via the third transistor, and a second terminal of the primary winding of the second transformer is directly coupled to the second terminal of the secondary winding of the first transformer and the control terminal of the second transistor via the fourth transistor.
2. The differential amplification circuit of claim 1,
a first path terminal and a second path terminal of the third transistor are connected to be connected to one of the first input node and the first output node, and a control terminal of the third transistor is connected to the other of the first input node and the first output node;
a first path terminal and a second path terminal of the fourth transistor are connected to be connected to one of the second input node and the second output node, and a control terminal of the fourth transistor is connected to the other of the second input node and the second output node.
3. The differential amplifier circuit according to claim 2, wherein the first transistor and the second transistor have the same channel length and width dimensions, and the third transistor and the fourth transistor have the same channel length and width dimensions,
the capacitance value formed by the third transistor between the control end and the first pass end of the third transistor is equal to the capacitance value formed by the first transistor between the control end and the first pass end of the first transistor.
4. The differential amplifier circuit according to claim 3, wherein a channel width-to-length ratio of the third transistor is approximately equal to two to three times a channel width-to-length ratio of the first transistor, and a channel width-to-length ratio of the fourth transistor is approximately equal to two to three times a channel width-to-length ratio of the second transistor.
5. The differential amplification circuit according to claim 3, wherein channel lengths or channel widths of the first to fourth transistors are the same.
6. The differential amplification circuit according to claim 1, wherein the first to fourth transistors are respectively formed of a plurality of MOSFETs, the first transistor includes n MOSFETs connected in parallel, the second transistor includes n MOSFETs connected in parallel, the third transistor includes m MOSFETs connected in parallel, the fourth transistor includes m MOSFETs, each of which has the same channel width,
wherein n and m are both natural numbers greater than or equal to 1, and n is about two times to three times of m.
7. The differential amplification circuit according to claim 6, wherein the first transistor is provided adjacent to the third transistor, the first transistor and each of the MOSFETs in the third transistor are arranged in a row with the first side and the second side of the row opposed, wherein channels of the MOSFETs are parallel to each other,
the gate of each MOSFET in the first transistor is connected to the gate of each MOSFET in the third transistor at the row first side, the source of each MOSFET in the first transistor is connected to the row first side, the drain of each MOSFET in the first transistor is connected to the row second side, and the source and drain of each MOSFET in the third transistor are connected to the row second side.
8. The differential amplifier circuit according to claim 6, wherein said second transistor is disposed adjacent to said fourth transistor, each of said MOSFETs in said second transistor and said fourth transistor is arranged in a row with a first side and a second side of the row opposite to each other, wherein channels of each of said MOSFETs are parallel to each other,
the gate of each MOSFET in the second transistor is connected to the gate of each MOSFET in the fourth transistor at the row first side, the source of each MOSFET in the second transistor is connected at the row first side, the drain of each MOSFET in the fourth transistor is connected at the row second side, and the source and drain of each MOSFET in the fourth transistor are connected at the row second side.
9. The differential amplifier circuit according to claim 6, wherein each MOSFET is of an N-channel type, and the second path terminal of the first transistor and the second path terminal of the second transistor are connected to a ground.
10. The differential amplification circuit of claim 1,
a first pass end of the third transistor is grounded through a second resistor, a second pass end of the third transistor is connected with the first output node, and a control end of the third transistor is connected with a control end of the first transistor;
and a first path end of the fourth transistor is grounded through a third resistor, a second path end of the fourth transistor is connected with the second output node, and a control end of the fourth transistor is connected with a control end of the second transistor.
11. The differential amplifier circuit according to claim 10, wherein the first input signal and the second input signal are common mode signals having the same polarity as each other, the differential amplifier circuit further comprising:
the first end of the first capacitor is connected with the reference ground, the second end of the first capacitor is connected with the first end of the first resistor and receives bias voltage, and the second end of the first resistor is connected with a center tap of a secondary coil of the first transformer; and
a second resistor and a second capacitor, the second capacitor and the second resistor being connected in series between a center tap of the primary winding of the second transformer and a reference ground, the center tap of the primary winding of the second transformer receiving a supply voltage.
12. The differential amplification circuit according to claim 1, wherein the first transistor and the third transistor are disposed adjacent to each other, and a control terminal of the first transistor and a control terminal of the third transistor are connected by a first wiring (G1) having an extending direction perpendicular to a channel length extending direction of the first transistor and the third transistor; the second transistor and the fourth transistor are adjacently arranged, the control end of the second transistor and the control end of the fourth transistor are connected through a second connecting line (G2), and the extending direction of the second connecting line is perpendicular to the extending direction of the channel lengths of the second transistor and the fourth transistor.
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| CN113824413A (en) * | 2021-08-29 | 2021-12-21 | 北京工业大学 | Differential amplifier circuit based on NCFET |
| CN114499425A (en) * | 2022-01-10 | 2022-05-13 | 电子科技大学 | High-stability differential common-source amplifier based on neutralization capacitor |
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| WO2023167864A1 (en) * | 2022-03-01 | 2023-09-07 | Apple Inc. | Amplifier with parasitic capacitance neutralization |
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| CN107592079B (en) | 2021-03-09 |
| CN107592079A (en) | 2018-01-16 |
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