CN112928157B - Display panel and manufacturing method thereof - Google Patents
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- CN112928157B CN112928157B CN202110183961.0A CN202110183961A CN112928157B CN 112928157 B CN112928157 B CN 112928157B CN 202110183961 A CN202110183961 A CN 202110183961A CN 112928157 B CN112928157 B CN 112928157B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000010409 thin film Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 17
- 239000003990 capacitor Substances 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 11
- -1 silicon nitride compound Chemical class 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 13
- 229910010272 inorganic material Inorganic materials 0.000 description 10
- 239000011147 inorganic material Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000000059 patterning Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 239000011810 insulating material Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- OBNDGIHQAIXEAO-UHFFFAOYSA-N [O].[Si] Chemical compound [O].[Si] OBNDGIHQAIXEAO-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 238000009413 insulation Methods 0.000 description 2
- 238000004321 preservation Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000007715 excimer laser crystallization Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/126—Shielding, e.g. light-blocking means over the TFTs
Abstract
The embodiment of the invention discloses a display panel and a manufacturing method thereof. The display panel comprises a thin film transistor and a power line; the thin film transistor comprises a first gate layer, an active layer positioned on the first gate layer and a second gate layer positioned on the active layer; the power line is connected to the first gate layer to make the first gate layer have a first potential, and the orthographic projection of the active layer on the first gate layer is located within the boundary range of the first gate layer. According to the embodiment of the invention, the first gate layer is arranged below the active layer and is connected with the power line, so that the first gate layer has a stable first potential, and electrostatic shielding is generated on the film layer below the first gate layer, so that the reliability of the thin film transistor of the display panel is improved, and the product quality of the display panel is improved.
Description
Technical Field
The invention relates to the field of display, in particular to a display panel and a manufacturing method thereof.
Background
With the improvement of the product quality requirement of the display panel, the Light and high color gamut OLED (Organic Light Emitting Diode) display panel has gained wide attention.
The existing display panel, especially the OLED display panel, adopts a thin film transistor to control current drive, which has high requirements on the reliability of the thin film transistor, and the films of the organic flexible substrate and the like adopted by the display panel have electric charges, and the active layer of the thin film transistor is easily influenced by the electric charges of the films below the active layer, such as the organic flexible substrate, so that the reliability of the thin film transistor is difficult to improve, and the product quality of the display panel is influenced.
Therefore, a display panel and a method for fabricating the same are needed to solve the above-mentioned problems.
Disclosure of Invention
The embodiment of the invention provides a display panel and a manufacturing method thereof, and aims to solve the technical problem that a film layer below an active layer of the conventional display panel, such as an organic flexible substrate, has electric charges, so that the reliability of a thin film transistor is poor.
The embodiment of the invention provides a display panel, which comprises a thin film transistor and a power line;
the thin film transistor comprises a first gate layer, an active layer positioned on the first gate layer and a second gate layer positioned on the active layer;
the power supply line is connected to the first gate layer to enable the first gate layer to have a first potential, and an orthographic projection of the active layer on the first gate layer is located within a boundary range of the first gate layer.
In one embodiment, the display panel further includes a first electrode layer on the first gate layer;
wherein the first gate layer and the first electrode layer have a first overlapping portion.
In one embodiment, the first gate layer includes a first portion overlapping with the active layer and a second portion connected to the first portion, the second portion and the first electrode layer having the first overlapping portion.
In one embodiment, the active layer includes a channel portion and conductor portions on both sides of the channel portion, and the first portion overlaps the channel portion.
In one embodiment, the first electrode layer and the second gate layer are on the same layer and connected to each other.
In an embodiment, the display panel further includes a source drain layer located on the active layer, the source drain layer includes a source and a drain, the source or the drain is located between the first electrode layer and the second gate layer, and the power line is located on a side of the first electrode layer away from the source drain layer.
In an embodiment, the power line and the source/drain electrode layer are in the same layer, the power line includes a third portion disposed opposite to the first electrode layer, and the third portion and the first electrode layer form a first capacitor.
In an embodiment, the display panel further includes a buffer layer between the first gate layer and the active layer, and an orthographic projection of the buffer layer on the first gate layer is within an orthographic projection of the active layer on the first gate layer.
In an embodiment, the buffer layer includes a first sub buffer layer and/or a second sub buffer layer, and a material of the first sub buffer layer and/or the second sub buffer layer includes at least one of a silicon nitride compound and a silicon oxy compound.
The embodiment of the invention also provides a manufacturing method of the display panel, which comprises the following steps:
forming a first gate layer on a substrate;
forming a buffer layer and an active layer on the first gate layer;
forming a second gate layer and a first electrode layer on the active layer;
forming a source drain layer and a power line on the second gate layer and the first electrode layer;
wherein the power line is connected to the first gate layer to make the first gate layer have a first potential, and an orthographic projection of the active layer on the first gate layer is located within a boundary range of the first gate layer.
Has the advantages that: according to the embodiment of the invention, the first gate layer is arranged below the active layer and is connected with the power line, so that the first gate layer has a stable first potential, and electrostatic shielding is generated on the film layer below the first gate layer, so that the reliability of the thin film transistor of the display panel is improved, and the product quality of the display panel is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a second structure provided in the embodiment of the present invention;
FIG. 3 is a schematic diagram of a third structure provided in the embodiment of the present invention;
FIG. 4 is a flowchart illustrating a method of fabricating a display panel according to the present invention;
fig. 5a to 5d are process flow diagrams of a manufacturing method of a display panel according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Furthermore, it should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, and are not intended to limit the present invention.
The active layer of the thin film transistor of the existing display panel is easily influenced by the charges of the film layer below the active layer, such as a flexible substrate, and the problem of poor reliability of the thin film transistor exists.
The embodiment of the invention provides a display panel and a manufacturing method thereof. The following are detailed descriptions. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
Referring to fig. 1 to 3, the display panel 100 includes a thin film transistor and a power line 105;
the thin film transistor comprises a first gate layer 102, an active layer 103 located on the first gate layer 102, and a second gate layer 104 located on the active layer 103;
the power line 105 is connected to the first gate layer 102 to make the first gate layer 102 have a first potential, and an orthographic projection of the active layer 103 on the first gate layer 102 is located within a boundary of the first gate layer 102.
In the embodiment of the invention, the first gate layer 102 is disposed below the active layer 103 and connected to the power line 105, so that the first gate layer 102 has a stable first potential, and electrostatic shielding is generated on a film layer below the first gate layer 102, thereby improving reliability of a thin film transistor of the display panel 100 and improving product quality of the display panel 100.
The technical solution of the present invention will now be described with reference to specific embodiments.
Referring to fig. 1 to fig. 3, in the present embodiment, the display panel 100 further includes a first electrode layer 106, and the first electrode layer 106 is located on the first gate layer 102;
wherein the first gate layer 102 and the first electrode layer 106 have a first overlapping portion.
In this embodiment, the display panel 100 further includes a substrate 101, and the thin film transistor is located on the substrate 101.
In this embodiment, the substrate 101 may be a flexible substrate, and the material of the substrate 101 may be polyimide or other materials.
In this embodiment, the first electrode layer 106 is electrically connected to the second gate layer 104, and the first electrode layer 106 has a second potential. The first potential and the second potential form a potential difference, and the first electrode layer 106 and the first gate layer 102 form a second capacitor.
In this embodiment, the power line 105 is connected to the first gate layer 102 to form the stable first potential, for example, the magnitude of the first potential may be 3.68 volts to 5.52 volts, such as 4.6 volts.
By the first gate layer 102 having the stable first potential, charges in a film layer below the first gate layer 102, such as the substrate 101, are shielded, so that charges in the film layer below the first gate layer 102 are prevented from affecting the active layer 103, especially the channel portion, reliability of the thin film transistor of the display panel 100 is improved, and product quality of the display panel 100 is improved.
In this embodiment, the first gate layer 102 includes a first portion overlapping with the active layer 103 and a second portion connected to the first portion, and the second portion and the first electrode layer 106 have the first overlapping portion.
In this embodiment, the active layer 103 includes a channel portion and conductor portions located on both sides of the channel portion, and the first portion overlaps with the channel portion.
In this embodiment, the material of the active layer 103 may be polysilicon.
In this embodiment, the display panel 100 further includes a source drain layer 107 located on the active layer 103, where the source drain layer 107 includes a source and a drain.
In this embodiment, the first electrode layer 106 may be on the same layer as the source/drain layer 107 and electrically connected to the second gate layer 104.
In this embodiment, the first electrode layer 106 and the second gate layer 104 may be at the same layer and connected to each other.
When the first electrode layer 106 and the second gate layer 104 are on the same layer, the first electrode layer 106 and the second gate layer 104 are formed in the same process using the same material.
In this embodiment, the display panel further includes a source drain layer located on the active layer 103, where the source drain layer includes a source and a drain, the source or the drain is located between the first electrode layer 106 and the second gate layer 104, and the power line 105 is located on a side of the first electrode layer 106 away from the source drain layer.
In this embodiment, the power line 105 and the source/drain layer 107 are in the same layer, the power line 105 includes a third portion disposed opposite to the first electrode layer 106, and the third portion and the first electrode layer 106 form a first capacitor.
In this embodiment, when the first gate layer 106 and the second gate layer 104 are on the same layer, the display panel 100 further includes a first insulating layer 108 located between the first gate layer 102 and the first electrode layer 106, and a second insulating layer 109 located between the first electrode layer 106 and the source drain layer 107.
In this embodiment, the display panel 100 further includes a first via hole and a second via hole, and the source and drain layers 107 are respectively connected to the conductor portions on two sides of the channel portion of the active layer 103 through the first via hole. The first via hole penetrates through the second insulating layer 109 and the first insulating layer 108 located between the source drain layer 107 and the active layer 103. The power line 105 is connected to the second portion of the first gate layer 102 through the second via.
In this embodiment, the power line 105 may be on the same layer as the first electrode layer 106, and at this time, the second via hole penetrates at least the first insulating layer 108. By the power line 105 and the first electrode layer 106 being on the same layer, the depth of the second via hole is reduced, and the problem of wire breakage caused by the fact that the depth of the second via hole is too deep is reduced.
In this embodiment, when the power line 105 and the source drain layer 107 are in the same layer, the second via hole at least penetrates through the first insulating layer 108 and the second insulating layer 109.
Through the arrangement of the third portion, the third portion and the first electrode layer 106 form a first capacitor, and the first gate layer 102 and the first electrode layer 106 form a second capacitor, so that the total capacitance of the storage capacitor is increased, and the product quality of the display panel 100 is improved.
In this embodiment, when the power line 105 and the source/drain layer 107 are in the same layer, the display panel 100 may further include a third insulating layer 110 located between the second insulating layer 109 and the source/drain layer 107.
At this time, the first via hole penetrates through the third insulating layer 110, the second insulating layer 109, and the first insulating layer 108 located between the source drain layer 107 and the active layer 103. The second via hole penetrates the first insulating layer 108, the second insulating layer 109, and the third insulating layer 110.
In this embodiment, the display panel 100 includes a display region and a binding region located at one side of the display region, and the first electrode layer 106, the first gate layer 102, the active layer 103, the second gate layer 104, and the source/drain layer 107 are located in the display region. The bonding region includes an opening filled with a filling layer, and the third insulating layer 110 may be integrally provided with the filling layer.
In this embodiment, the first via hole includes a first sub-via hole, a second sub-via hole and a third sub-via hole, and the second via hole includes a fourth sub-via hole, a fifth sub-via hole and a sixth sub-via hole. The first sub-via and the fourth sub-via penetrate through the first insulating layer 108, the second sub-via and the fifth sub-via penetrate through the second insulating layer 109, and the third sub-via. The sixth sub-via hole penetrates through the third insulating layer 110.
The first sub via hole, the second sub via hole and the third sub via hole may be formed at one time or may be formed separately; similarly, the fourth sub-via hole, the fifth sub-via hole and the sixth sub-via hole may be formed at one time or separately.
When the first sub-via hole, the second sub-via hole, and the third sub-via hole are formed separately, and the fourth sub-via hole, the fifth sub-via hole, and the sixth sub-via hole are formed separately, the first sub-via hole and the fourth sub-via hole are formed in the same process, the second sub-via hole and the fifth sub-via hole are formed in the same process, and the third sub-via hole and the sixth sub-via hole are formed in the same process.
In this embodiment, the display panel further includes a buffer layer 111 located between the first gate layer 102 and the active layer 103.
By arranging the buffer layer 111, the first gate layer 102 and the active layer 103 are separated, so that the first gate layer 102 and the active layer 103 are arranged in an insulating manner, and the influence on the formation quality of the active layer 103 caused by the influence of the first gate layer 102 on the heat preservation effect in the manufacturing process in the formation process of the active layer 103 is reduced while the first gate layer 102 and the active layer 103 are arranged in an insulating manner.
In this embodiment, when the buffer layer 111 is disposed between the first gate layer 102 and the active layer 103, the thickness of the first insulating layer 108 located between the source/drain layer 107 and the active layer 103 is smaller than the thickness of the first insulating layer 108 located in a region except between the source/drain layer 107 and the active layer 103.
In this embodiment, the buffer layer includes a first sub buffer layer and/or a second sub buffer layer, and a material of the first sub buffer layer and/or the second sub buffer layer includes at least one of a silicon nitride compound and a silicon oxy compound.
In this embodiment, the first sub-buffer layer may be made of silicon nitride, such as SiN x The material of the second sub-buffer layer may be an oxygen silicon compound, such as silicon dioxide, silicon monoxide, etc.
The first sub-buffer layer may be on the first gate layer 102, and the second sub-buffer layer may be on the first sub-buffer layer; alternatively, the second sub-buffer layer is located on the first gate layer 102, and the first sub-buffer layer is located on the second sub-buffer layer.
When the material of the first sub-buffer layer is silicon nitride (SiN) x ) When the material of the second sub buffer layer is an oxygen silicon compound, such as silicon dioxide, the thickness of the first sub buffer layer may be 40 nm to 60 nm, preferably 50 nm; the thickness of the second sub-buffer layer may be 240 nm to 360 nm, and is preferably 300 nm.
When the thickness of the first sub-buffer layer is 40 nm to 60 nm, preferably 50 nm, and the thickness of the second sub-buffer layer is 240 nm to 360 nm, preferably 300 nm, the thickness of the buffer layer 111 ensures that the influence of the thermal insulation effect in the process of forming the first gate layer 102 on the active layer 103 is minimized, and the influence of the too small capacitance of the second capacitor caused by the too large distance between the first electrode layer 106 and the first gate layer 102 on the product quality of the display panel 100 is not affected.
In this embodiment, an orthogonal projection of the buffer layer on the first gate layer 102 may be located within an orthogonal projection of the active layer 103 on the first gate layer 102.
By locating the orthographic projection of the buffer layer 111 on the first gate layer 102 in the orthographic projection of the active layer 103 on the first gate layer 102, the distance between the first electrode layer 106 and the first gate layer 102 is advantageously reduced, and the capacitance of the second capacitor is increased. In addition, when the first sub-buffer layer and/or the second sub-buffer layer are made of a silicon nitride compound, the dielectric constant of the silicon nitride compound is relatively large, so that the capacitance of the second capacitor can be increased when the first sub-buffer layer and/or the second sub-buffer layer are kept away from the region of the first gate layer 102 opposite to the first electrode layer 106.
In this embodiment, the display panel 100 may be a liquid crystal display panel, an OLED display panel, or another type of display panel.
In this embodiment, the display panel 100 may further include a protection layer 112 located between the first gate layer 102 and the substrate 101, where the protection layer 112 is used to keep the temperature of the active layer 103 at all places during the manufacturing process of the display panel 100 consistent, so as to avoid the influence of the uneven temperature distribution of the active layer 103 on the working performance of the active layer 103 during the manufacturing process.
In this embodiment, the display panel 100 further includes a planarization layer 113 located on the source/drain layer 107; when the display panel 100 is an OLED display panel, the display panel 100 further includes a pixel defining layer 114 on the planarization layer 113, the pixel defining layer 114 including a plurality of spacers; the display panel 100 further includes a light emitting device layer located between the spacers, the light emitting device layer includes an anode layer 115, a light emitting material layer located on the anode layer 115, and a cathode layer, and the anode layer 115 is electrically connected to the source drain layer 107; the display panel 100 further includes a support 116 on the pixel defining layer 114.
In this embodiment, the first gate layer 102 is disposed below the active layer 103 and connected to the power line 105, so that the first gate layer 102 has a stable first potential, and the first gate layer 102 and the first electrode layer 106 form a capacitor, thereby generating an electrostatic shield for a film layer below the first gate layer 102, improving reliability of the thin film transistor of the display panel 100, and improving product quality of the display panel 100.
Referring to fig. 1 to 4 and fig. 5a to 5d, an embodiment of the present invention further discloses a method for manufacturing a display panel, including:
S100, a first gate layer 102 is formed on a substrate 101.
And S200, forming a buffer layer 111 and an active layer 103 on the first gate layer 102.
And S300, forming a second gate layer 104 and a first electrode layer 106 on the active layer 103.
And S400, forming a source drain layer 107 and a power line 105 on the second gate layer 104 and the first electrode layer 106.
Wherein the power line 105 is connected to the first gate layer 102 to make the first gate layer 102 have a first potential, and an orthographic projection of the active layer 103 on the first gate layer 102 is located within a boundary of the first gate layer 102.
In the manufacturing method of the display panel according to the embodiment of the invention, the first gate layer 102 is disposed below the active layer 103 and connected to the power line 105, so that the first gate layer 102 has a stable first potential, and the first gate layer 102 and the first electrode layer 106 form a capacitor to shield a film layer below the first gate layer 102, thereby improving reliability of a thin film transistor of the display panel 100 and improving product quality of the display panel 100.
The technical solution of the present invention will now be described with reference to specific embodiments.
Referring to fig. 1 to 4 and fig. 5a to 5d, in the present embodiment, the step S100 of forming the first gate layer 102 on the substrate 101 may include:
and S110, forming a first conductor material layer on the substrate 101.
In this embodiment, the first conductive material layer may be formed on the substrate 101 by chemical vapor deposition or physical vapor deposition, or other methods.
S120, the first conductive material layer is subjected to a first patterning process to form the first gate layer 102.
In this embodiment, the step S200 of forming the buffer layer 111 and the active layer 103 on the first gate layer 102 may include:
s210, forming a first inorganic material layer on the first gate layer 102.
And S220, forming a second inorganic material layer on the first inorganic material.
And S230, forming a semiconductor material layer on the second inorganic material layer.
S240, the first inorganic material layer, the second inorganic material layer and the semiconductor material layer are processed by a first predetermined process to form the buffer layer 111 and the active layer 103.
In this embodiment, step S240 may include:
s241, the first inorganic material layer, the second inorganic material layer, and the semiconductor material layer are subjected to a second patterning process to form the buffer layer 111 and the first semiconductor layer.
S242, the first semiconductor layer is processed by a second predetermined process to form the active layer 103.
Alternatively, step S240 may include:
and S243, forming a second semiconductor layer on the semiconductor material layer through a third preset process.
S244, the second semiconductor layer, the first inorganic material layer, and the second inorganic material layer are subjected to a third patterning process to form the buffer layer 111 and the active layer 103.
In this embodiment, the second predetermined process and the third predetermined process include an excimer laser crystallization process.
In this embodiment, the buffer layer 111 includes a first sub-buffer layer and a second sub-buffer layer, and the buffer layer 111 is configured to separate the first gate layer 102 and the active layer 103, so that the first gate layer 102 and the active layer 103 are insulated from each other, and at the same time, the influence on the formation quality of the active layer 103 caused by the effect of the first gate layer 102 on the heat preservation effect in the manufacturing process is reduced in the formation process of the active layer 103 of the first gate layer 102.
The material of the first sub-buffer layer may be a silicon nitride compound, such as SiN x The material of the second sub-buffer layer may be an oxygen silicon compound, such as silicon dioxide, silicon monoxide, etc.
When the material of the first sub-buffer layer is silicon nitride (SiN) x ) When the material of the second sub buffer layer is an oxygen silicon compound, such as silicon dioxide, the thickness of the first sub buffer layer may be 40 nm to 60 nm, preferably 50 nm; the thickness of the second sub-buffer layer may be 240 nm to 360 nm, and is preferably 300 nm.
When the thickness of the first sub-buffer layer is 40 nm to 60 nm, preferably 50 nm, and the thickness of the second sub-buffer layer is 240 nm to 360 nm, preferably 300 nm, the thickness of the buffer layer 111 ensures that the influence of the thermal insulation effect in the process of forming the first gate layer 102 on the active layer 103 is minimized, and the influence of the too small capacitance of the second capacitor caused by the too large distance between the first electrode layer 106 and the first gate layer 102 on the product quality of the display panel 100 is not affected.
After step S200 and before step S300, the method for manufacturing a display panel further includes:
s500, forming a first insulating layer 108 on the first gate layer 102.
In this embodiment, the step S300 of forming the second gate layer 104 and the first electrode layer 106 on the active layer 103 may include:
And S310, forming a second conductor material layer on the active layer 103.
And S320, forming the second gate layer 104 and the first electrode layer 106 by the second conductor material layer through a third patterning process.
After step S300 and before step S400, the method for manufacturing a display panel further includes:
s600, forming a second insulating layer 109 and a third insulating layer 110 on the second gate layer 104 and the first electrode layer 106.
In this embodiment, the step S400 of forming the source/drain layer 107 and the power line 105 on the second gate layer 104 and the first electrode layer 106 may include:
and S410, forming a third conductor material layer on the second gate layer 104 and the first electrode layer 106.
And S420, forming the source drain layer 107 and the power line 105 by the third conductor material layer through fourth patterning treatment.
In this embodiment, step S410 may include:
s411, forming a first via hole and a second via hole on the active layer 103 and the first gate layer 102, wherein the first via hole and the second via hole penetrate through the first insulating layer 108, the second insulating layer 109, and the third insulating layer 110.
S412, forming the third material layer on the third insulating layer 110.
Or, the first via hole includes a first sub-via hole, a second sub-via hole and a third sub-via hole, the second via hole includes a fourth sub-via hole, a fifth sub-via hole and a sixth sub-via hole, the first sub-via hole, the second sub-via hole and the third sub-via hole are formed respectively, and when the fourth sub-via hole, the fifth sub-via hole and the sixth sub-via hole are formed respectively, step S500 may include:
s510, forming a first insulating material layer on the first gate layer 102.
S520, forming the first insulating layer 108 by performing a fifth patterning process on the first insulating material layer, where the first insulating layer 108 includes a first sub-via and the fourth sub-via.
Step S600 may include:
s610, forming a second insulating material layer on the second gate layer 104 and the first electrode layer 106.
And S620, forming the second insulating layer 109 by performing a sixth patterning process on the second insulating material layer, where the second insulating layer 109 includes the second sub-via and the fifth sub-via.
And S630, forming a third insulating material layer on the second insulating layer 109.
S640, forming the third insulating layer 110 by performing a seventh patterning process on the third insulating material layer, where the third insulating layer 110 includes the third sub-via and the sixth sub-via.
In the embodiment of the invention, the first gate layer 102 is disposed below the active layer 103 and connected to the power line 105, so that the first gate layer 102 has a stable first potential, the first gate layer 102 and the first electrode layer 106 form a capacitor, and a film layer below the first gate layer 102 is shielded, so that reliability of a thin film transistor of the display panel 100 is improved, and product quality of the display panel 100 is improved.
The embodiment of the invention discloses a display panel and a manufacturing method thereof. The display panel comprises a thin film transistor and a power line; the thin film transistor comprises a first gate layer, an active layer positioned on the first gate layer and a second gate layer positioned on the active layer; the power line is connected to the first gate layer to make the first gate layer have a first potential, and the orthographic projection of the active layer on the first gate layer is located within the boundary range of the first gate layer. According to the embodiment of the invention, the first gate layer is arranged below the active layer and is connected with the power line, so that the first gate layer has a stable first potential, and electrostatic shielding is generated on the film layer below the first gate layer, so that the reliability of the thin film transistor of the display panel is improved, and the product quality of the display panel is improved.
The display panel and the manufacturing method thereof provided by the embodiment of the invention are described in detail above, and the principle and the embodiment of the invention are explained by applying a specific example, and the description of the embodiment is only used for helping to understand the method and the core idea of the invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (7)
1. A display panel comprises a thin film transistor and a power line;
the thin film transistor comprises a first gate layer, an active layer positioned on the first gate layer and a second gate layer positioned on the active layer;
a first electrode layer on the first gate layer, the first gate layer and the first electrode layer having a first overlapping portion;
the source drain layer is positioned on the active layer and comprises a source electrode and a drain electrode, the source electrode or the drain electrode is positioned between the first electrode layer and the second gate layer, and the power line is positioned on one side, far away from the source drain layer, of the first electrode layer;
The power line and the source drain electrode layer are on the same layer, the power line comprises a third part arranged opposite to the first electrode layer, and the third part and the first electrode layer form a first capacitor;
the power supply line is connected to the first gate layer to enable the first gate layer to have a first potential, and the orthographic projection of the active layer on the first gate layer is located within the boundary range of the first gate layer.
2. The display panel according to claim 1, wherein the first gate layer includes a first portion overlapping with the active layer and a second portion connected to the first portion, the second portion and the first electrode layer having the first overlapping portion.
3. The display panel according to claim 2, wherein the active layer includes a channel portion and conductor portions on both sides of the channel portion, and wherein the first portion overlaps the channel portion.
4. The display panel according to claim 1, wherein the first electrode layer and the second gate layer are on the same layer and are connected to each other.
5. The display panel according to claim 1, further comprising a buffer layer between the first gate layer and the active layer, wherein an orthographic projection of the buffer layer on the first gate layer is within an orthographic projection of the active layer on the first gate layer.
6. The display panel according to claim 5, wherein the buffer layer comprises a first sub-buffer layer and/or a second sub-buffer layer, and a material of the first sub-buffer layer and/or the second sub-buffer layer comprises at least one of a silicon nitride compound and a silicon oxy-compound.
7. A method for manufacturing a display panel is characterized by comprising the following steps:
forming a first gate layer on a substrate;
forming a buffer layer and an active layer on the first gate layer;
forming a second gate layer and a first electrode layer on the active layer;
forming a source drain layer and a power line on the second gate layer and the first electrode layer;
wherein the power supply line is connected to the first gate layer to make the first gate layer have a first potential, and an orthographic projection of the active layer on the first gate layer is located within a boundary range of the first gate layer;
the first gate layer and the first electrode layer have a first overlapping portion;
the source drain electrode layer comprises a source electrode and a drain electrode, the source electrode or the drain electrode is positioned between the first electrode layer and the second gate layer, and the power line is positioned on one side of the first electrode layer, which is far away from the source drain electrode layer;
The power line and the source drain electrode layer are on the same layer, the power line comprises a third portion arranged opposite to the first electrode layer, and the third portion and the first electrode layer form a first capacitor.
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| US20140332771A1 (en) * | 2013-05-09 | 2014-11-13 | Samsung Display Co., Ltd. | Organic light emitting diode display |
| US20160005803A1 (en) * | 2014-07-03 | 2016-01-07 | Lg Display Co., Ltd. | Organic electroluminescent device |
| US20200411619A1 (en) * | 2019-06-28 | 2020-12-31 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Array substrate, manufacturing method thereof, and display device |
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| US20030111954A1 (en) * | 2001-12-14 | 2003-06-19 | Samsung Sdi Co., Ltd. | Flat panel display device with face plate and method for fabricating the same |
| US20140332771A1 (en) * | 2013-05-09 | 2014-11-13 | Samsung Display Co., Ltd. | Organic light emitting diode display |
| US20160005803A1 (en) * | 2014-07-03 | 2016-01-07 | Lg Display Co., Ltd. | Organic electroluminescent device |
| US20200411619A1 (en) * | 2019-06-28 | 2020-12-31 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Array substrate, manufacturing method thereof, and display device |
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