CN112927735A

CN112927735A - Memory and memory system

Info

Publication number: CN112927735A
Application number: CN202011222355.7A
Authority: CN
Inventors: 郑会柱; 保罗·费伊
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2019-12-06
Filing date: 2020-11-05
Publication date: 2021-06-08

Abstract

The application discloses a memory and a storage system. The memory includes: a plurality of rows, each row of the plurality of rows coupled to a plurality of memory cells; a target row determination circuit adapted to determine a row, which is likely to lose data, among the plurality of rows as a target row; and a transfer circuit adapted to transfer, when the number of target rows determined by the target row determination circuit is equal to or greater than the threshold value, information indicating that the number of target rows reaches the threshold value to the memory controller.

Description

Memory and memory system

Cross Reference to Related Applications

Priority is claimed for U.S. provisional patent application No. 62/944,577 filed on 6.12.2019 and U.S. patent application No. 16/939,696 filed on 27.7.2020, which are all incorporated herein by reference.

Technical Field

Various embodiments of the present invention relate to memory and storage systems.

Background

As the integration degree of the memory increases, a gap between a plurality of word lines included in the memory decreases. As the gap between word lines decreases, the coupling effect between adjacent word lines increases.

The word line is switched between an inactive state and an active state each time data is input to or output from the memory cell. The increased coupling effect between adjacent word lines may cause damage to data of memory cells coupled to word lines adjacent to the frequently activated word lines. This phenomenon is known as row hammering or word line disturb, and this problem is that the data of the memory cells is damaged before the memory cells are refreshed.

Fig. 1 is a schematic diagram illustrating a row hammer phenomenon. Fig. 1 shows a portion of a cell array included in a memory device.

In fig. 1, 'WLL' may represent a word line having an excessive activation time, which may be referred to as a frequently activated word line, and 'WLL-1' and 'WLL + 1' may represent word lines disposed adjacent to the frequently activated word line WLL, which may be referred to as adjacent word lines. 'CL' may represent memory cells coupled to a frequently activated word line WLL, and 'CL-1' may represent memory cells coupled to an adjacent word line WLL-1, and 'CL + 1' may represent memory cells coupled to an adjacent word line WLL + 1. The memory cells CL, CL-1, and CL +1 may include cell transistors TL, TL-1, and TL +1 and cell capacitors CAPL, CAPL-1, and CAPL +1, respectively.

In FIG. 1, when a frequently activated word line WLL is activated or deactivated, voltages of neighboring word lines WLL-1 and WLL +1 may increase or decrease due to a coupling effect between neighboring word lines WLL, WLL-1 and WLL +1, thereby affecting the charge amounts of the cell capacitors CL-1 and CL + 1. Therefore, when the frequently activated word line WLL is switched between an inactive state and an active state, the amount of charge stored in the cell capacitors CAPL-1 and CAPL +1 included in the memory cells CL-1 and CL +1 may change, and data of the memory cells may be degraded.

In addition, electromagnetic waves generated when a word line is switched between an inactive state and an active state may corrupt data by charging electrons into or discharging electrons from cell capacitors of memory cells coupled to adjacent word lines.

The method for improving the row hammer phenomenon may include: detecting a row that has been activated too many times (i.e., a wordline), and additionally refreshing rows adjacent to the row that has been activated too many times. Such additional refresh operations may typically be performed hidden when performing typical refresh operations. For example, whenever a refresh command is applied to the memory N times (where N is an integer equal to or greater than 1), the memory may perform hidden additional refresh operations without the memory controller's knowledge, in addition to typical refresh operations.

Recently, research has been conducted on a low temperature memory operating at a cryogenic temperature (cryogenic memory). At a low temperature, charge is hardly discharged from the cell capacitor of the memory, and thus the refresh operation may be rarely performed or may not be performed at all. That is, since the data retention time of the memory cell is greatly increased at a low temperature, a refresh command may be rarely applied to the memory compared to the general memory. However, even in low temperature memory, data loss occurs due to row hammering. Thus, rarely applying refresh commands to the memory inevitably reduces the number of additional refresh operations performed in the memory, which is problematic.

Disclosure of Invention

Embodiments of the present invention are directed to a technique for refreshing rows that require refreshing due to a row hammer phenomenon.

According to an embodiment of the present invention, a memory includes: a plurality of rows, each row of the plurality of rows coupled to a plurality of memory cells; a target row determination circuit adapted to determine a row, which is likely to lose data, among the plurality of rows as a target row; and a transfer circuit (transfer circuit) adapted to transfer, when the number of target rows determined by the target row determination circuit is equal to or larger than a threshold value, information indicating that the number of target rows reaches the threshold value to the memory controller.

According to another embodiment of the present invention, a storage system includes: a memory controller; and a memory, wherein the memory comprises: a plurality of rows, each row of the plurality of rows coupled to a plurality of memory cells; a target row determination circuit adapted to determine a row, which is likely to lose data, among the plurality of rows as a target row; and a transfer circuit adapted to transfer, when the number of target rows determined by the target row determination circuit is equal to or greater than a threshold value, information indicating that the number of target rows reaches the threshold value to a memory controller, wherein the memory controller is adapted to transfer, when the information is received from a memory, a command for refreshing the target rows to the memory.

According to still another embodiment of the present invention, a storage system includes: a memory controller; and a memory, wherein the memory comprises: a plurality of rows, each row of the plurality of rows coupled to a plurality of memory cells; a target row determination circuit adapted to determine a row, which is likely to lose data, among the plurality of rows as a target row; and a transfer circuit adapted to transfer, when the number of target rows determined by the target row determination circuit is equal to or greater than a threshold value, information indicating that the number of target rows reaches the threshold value to the memory controller, wherein the memory controller is adapted not to apply a command to the memory for a predetermined period after receiving the information from the memory.

According to yet another embodiment of the present invention, a method for operating a memory system including a memory controller and a memory includes: determining, by a memory, a row that is likely to lose data among a plurality of rows as a target row; determining, by the memory, whether the number of target rows reaches a threshold; and transmitting, by the memory, information indicating that the number of target rows reaches the threshold value to the memory controller.

According to yet another embodiment of the present invention, a method for operating a memory includes: determining an adjacent row disposed adjacent to the row activated for too many times as a target row; checking whether the number of target rows reaches a threshold value; notifying a memory controller when the number of target rows reaches a threshold; and performing a refresh operation on the target row.

Drawings

Fig. 1 is a schematic diagram illustrating a row hammer phenomenon and illustrating a portion of a cell array included in a memory device.

FIG. 2 is a block diagram illustrating a memory system 200 according to an embodiment of the invention.

FIG. 3 is a flow chart describing a method for operating the memory system 200 shown in FIG. 2 according to an embodiment of the present invention.

FIG. 4 is a flow chart describing a method for operating the memory system 200 shown in FIG. 2 according to another embodiment of the present invention.

FIG. 5 is a flow chart describing a method for operating the memory system 200 shown in FIG. 2 according to yet another embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

It is noted that references to "one embodiment," "another embodiment," and the like do not necessarily mean only one embodiment, and different references to any such phrases are not necessarily to the same embodiment(s).

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element described below may also be referred to as a second element or a third element without departing from the spirit and scope of the present invention.

It will be further understood that the terms "comprises," "comprising," "includes" and "including," when used in this specification, specify the presence of stated elements, and do not preclude the presence or addition of one or more other elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, the singular forms may also include the plural forms and vice versa, unless the context clearly dictates otherwise. The terms a and an, as used in this application and the appended claims, are generally to be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form.

Referring to fig. 2, a memory system 200 may include a memory controller 210 and a memory 220.

Memory controller 210 may control the operation of memory 220 based on the request of HOST. HOST may include a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), an Application Processor (AP), and the like. Memory controller 210 may include a host interface 211, a scheduler 212, a command generator 213, and a memory interface 215. The memory controller 210 may be included in a CPU, GPU, AP, or the like. In this case, in this configuration, HOST may refer to a structure other than the memory controller 210. For example, when the memory controller 210 is included in the CPU, the HOST shown in the drawing may represent a constituent element other than the memory controller 210 in the CPU.

HOST interface 211 may be an interface for communication between HOST and memory controller 210.

Scheduler 212 may determine the order of requests indicated to memory 220 among the requests from HOST. To improve the performance of memory 220, scheduler 212 may change the order in which requests are received from HOST HOST and the order of operations to be indicated to memory 220. For example, although HOST first requests a read operation of memory 220 and then subsequently requests a write operation, scheduler 212 can change the order of the requested operations so that the write operation is performed before the read operation.

Scheduler 212 may schedule refresh operations between operations requested from HOST to prevent data loss from memory 220. When the memory system 200 operates in a low temperature environment, the data retention time of the memory 220 may sharply increase. Thus, in low temperature environments, the scheduler 212 may be less able to schedule refresh operations. For example, scheduler 212 may schedule refresh operations in a manner that refreshes memory cells of memory 220 only once per day. In addition, when information indicating that the number of rows classified as the target row reaches the threshold value is transmitted from the memory 220, that is, when information indicating that the number of rows of which data is likely to be lost due to the row hammer phenomenon is equal to or greater than the threshold value is transmitted from the memory 220, the scheduler 212 may schedule an additional refresh operation to prevent data loss.

The command generator 213 may generate commands to be applied to the memory 220 according to the order of operations determined by the scheduler 212.

The memory interface 215 may be an interface between the memory controller 210 and the memory device 220. The command CMD and the address ADD may be transferred from the memory controller 210 to the memory 220 through the memory interface 215, and the DATA may be transferred/received. The memory interface 215 may also be referred to as a PHY interface.

The memory 220 may perform operations directed by the memory controller 210. The memory 220 may include a command receiving circuit 221, an address receiving circuit 222, a data transmitting/receiving circuit 223, a command decoder 224, a target row determining circuit 225, an address counter 226, and a memory array 227.

The command receiving circuit 221 may receive a command CMD transmitted from the memory interface 215 of the memory controller 210, and the address receiving circuit 222 may receive an address ADD transmitted from the memory interface 215 of the memory controller 210. The DATA transmission/reception circuit 223 may receive DATA transmitted from the memory interface 215 during a write operation and transmit the DATA to the memory interface 215 during a read operation. The memory 220 may be provided with a plurality of command pads (not shown), a plurality of address pads (not shown), and a plurality of data pads (not shown). The command receiving circuit 221 may receive a command CMD through a command pad, and the address receiving circuit 222 may receive an address ADD through an address pad, and the DATA transmitting/receiving circuit 223 may transmit/receive DATA through a DATA pad.

The command decoder 224 may decode a command CMD received through the command receiving circuit 221 to generate an internal command signal. The internal command signals may include an active signal ACT, a precharge signal PCG, a read signal RD, a write signal WT, a refresh signal REF, and an additional refresh signal ADD _ REF.

The target row determination circuit 225 may determine a row (i.e., a word line) that is likely to lose data, among a plurality of rows of the memory array 227, as a target row. The target row determination circuit 225 may select a row set adjacent to a row activated too many times as a target row based on the address ADD and the activation signal ACT received through the address receiving circuit 222. For example, when the fourth row is activated (i.e., accessed) too many times, a third row and a fifth row adjacent to the fourth row may be selected as the target row. The additional refresh address ADD _ REF _ ADD output from the target row determination circuit 225 may be an address representing a target row. When the number of target rows is equal to or greater than the threshold value (e.g., 2), the target row determination circuit 225 may transmit information ADD _ REF _ REQ (which is simply referred to as additional refresh operation request information) indicating that the number of target rows reaches the threshold value to the memory controller 210 through the data transmission/reception circuit 223.

The address counter 226 may change the refresh address REF _ ADD each time the refresh signal REF is activated. The refresh address REF _ ADD generated in the address counter 226 may not be used for the additional refresh operation but may be used for the normal refresh operation.

The memory array 227 may perform operations indicated by internal command signals ACT, PCG, RD, WT, REF, and ADD REF. In an additional refresh operation in which the additional refresh signal ADD _ REF is activated, the memory array 227 may perform a refresh operation on a row selected by the target address (i.e., additional refresh address) ADD _ REF _ ADD output from the target row determination circuit 225. In addition, in a refresh operation in which the refresh signal REF is activated, the memory array 227 may perform a refresh operation on a row selected by the refresh address REF _ ADD. In addition, the address ADD transferred from the memory controller 210 may be used during an activation operation, a read operation, and a write operation of the memory array 227. The memory array 227 may include constituent cells (such as a cell array) for operations such as an activation operation, a precharge operation, a read operation, a write operation, a refresh operation, and an additional refresh operation, row circuits for activating/deactivating rows of the cell array, and column circuits for inputting/outputting data to/from the cell array.

Referring to fig. 3, in step S301, the target row determining circuit 225 of the memory 220 may determine a row in which data is likely to be lost as a target row. For example, the target row determination circuit 225 may determine a row disposed adjacent to an excessively accessed row as a target row.

When the number of target lines is equal to or greater than the threshold value ('yes' in step S303), information ADD _ REF _ REQ indicating that the number of target lines is equal to or greater than the threshold value is activated, and in step S305, the information ADD _ REF _ REQ may be transferred to the memory controller 210 through the data transfer/reception circuit 223. Here, although the information ADD _ REF _ REQ is illustrated as being transferred to the memory controller 210 through the data transfer/reception circuit 223 in fig. 2, those skilled in the art will recognize that the information ADD _ REF _ REQ may be transferred to the memory controller 210 through another path, for example, the information ADD _ REF _ REQ may be transferred to the memory controller 210 through another type of pad. For reference, when the number of target lines is less than the threshold value ('no' in step S303), the process returns to step S301.

When the information ADD _ REF _ REQ is transmitted to the memory controller 210 through the DATA transmission/reception circuit 223, the information ADD _ REF _ REQ may be transmitted in a period in which DATA is not transmitted between the memory controller 210 and the memory 220. For example, since the DATA is not transferred between the memory controller 210 and the memory 220 during the activation operation, the memory 220 may transfer the information ADD _ REF _ REQ to the memory controller 210 within a predetermined period after the activation command is applied to the memory 220.

In step S307, the memory controller 210 may transmit an additional refresh command to the memory 220 in response to the information ADD _ REF _ REQ. Additional refresh commands can be transmitted to memory 220 via command CMD.

The command decoder 224 of the memory 220 may decode the command CMD to activate the additional refresh signal ADD _ REF, and in response to the activated additional refresh signal ADD _ REF, a target row designated by the target address ADD _ REF _ ADD may be refreshed in step S309. Here, one or more target rows may be refreshed, and the refreshed target row may no longer be the target row.

Subsequently, the process returns to step S301.

According to the operation method of fig. 3, when the number of target rows requiring additional refresh operations in the memory 220 is equal to or greater than the threshold value, the memory 220 may transmit information ADD _ REF _ REQ, indicating that the number of target rows requiring additional refresh operations in the memory 220 is equal to or greater than the threshold value, to the memory controller 210. Then, the memory controller 210 may apply an additional refresh command to the memory 220 in response to the information ADD _ REF _ REQ, and may refresh a target row in the memory 220. Therefore, even in a memory system that rarely performs a refresh operation, such as a low-temperature memory system, a target row that needs to be refreshed due to a row hammer phenomenon can be refreshed immediately.

Referring to fig. 4, the steps in fig. 4 (refer to S401, S403, and S405) may be performed in the same manner as the operations of steps S301, S303, and S305 shown in fig. 3.

In step S407, the memory controller 210 may transmit a refresh command to the memory 220 in response to the information ADD _ REF _ REQ. The refresh command may be transmitted to the memory 220 through the command CMD.

The command decoder 224 of the memory 220 may decode the command CMD to activate the refresh signal REF, and in response to the refresh signal REF being activated, may refresh the row specified by the refresh address REF _ ADD. In addition, in step S409, the target row specified by the target address ADD _ REF _ ADD may be additionally refreshed in the refresh operation period. That is, the memory controller 210 may apply a refresh command to the memory 220 in response to the information ADD _ REF _ REQ, and the memory 220 may perform a normal refresh operation and an additional refresh operation in a refresh operation period. When a refresh command is applied to the memory 220, an additional refresh operation may be performed after the refresh operation is performed as the command decoder 224 activates the refresh signal REF, and then the additional refresh signal ADD _ REF is activated.

Subsequently, the process returns to step S401.

According to the operation method of fig. 4, when the number of target rows in the memory 220 requiring the additional refresh operation is equal to or greater than the threshold value, the memory 220 may transfer information ADD _ REF _ REQ, indicating that the number of target rows in the memory 220 requiring the additional refresh operation is equal to or greater than the threshold value, to the memory controller 210. Further, the memory controller 210 may apply a refresh command to the memory 220 in response to the information ADD _ REF _ REQ, and may perform a refresh operation and an additional refresh operation in the memory 220. Therefore, even in a memory system that rarely performs a refresh operation (such as a low-temperature memory system), a target row that needs to be refreshed due to a row hammer phenomenon can be refreshed immediately.

Referring to fig. 5, the steps in fig. 5 (refer to S501, S503, and S505) may be performed in the same manner as the operations of steps S301, S303, and S305 shown in fig. 3.

When the memory controller 210 receives the information ADD _ REF _ REQ, the memory controller 210 may not apply any command to the memory 220 within a predetermined period after receiving the information ADD _ REF _ REQ in step S507. That is, when the information ADD _ REF _ REQ is received, the memory controller 210 may not instruct any operation to the memory 220 for a predetermined period of time.

In step S509, the memory 220 may perform an additional refresh operation within a predetermined period of time after the information ADD _ REF _ REQ is transmitted to the memory controller 210. Since the operation is not instructed to the memory 220 during the predetermined period, the memory 220 can perform an additional refresh operation within the predetermined period. The target row determination circuit 225 can transfer the activated information ADD _ REF _ REQ to the memory controller 210 through the data transfer/reception circuit 223 and simultaneously transfer the information ADD _ REF _ REQ to the command decoder 224. The command decoder 224 may activate the additional refresh signal ADD _ REF in response to the reception of the activated information ADD _ REF _ REQ, and as a result, may perform an additional refresh operation. When the additional refresh operation is performed, the target row being refreshed may no longer be the target row.

Subsequently, the process returns to step S501.

According to the operation method of fig. 5, when the number of target rows in the memory 220 requiring the additional refresh operation is equal to or greater than the threshold value, the memory 220 may transfer information ADD _ REF _ REQ, indicating that the number of target rows in the memory 220 requiring the additional refresh operation is equal to or greater than the threshold value, to the memory controller 210. Then, the memory controller 210 may not apply any command to the memory 220 during a predetermined time in response to the information ADD _ REF _ REQ, and the memory 220 may perform an additional refresh operation during the predetermined time. Therefore, even in a memory system that rarely performs a refresh operation (such as a low-temperature memory system), a target row that needs to be refreshed due to a row hammer phenomenon can be immediately refreshed.

According to an embodiment of the present invention, a row requiring refresh due to a row hammer phenomenon may be refreshed.

Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A memory, comprising:

a plurality of rows, each row of the plurality of rows coupled to a plurality of memory cells;

a target row determination circuit adapted to determine a row in which data is likely to be lost among the plurality of rows as a target row; and

a transfer circuit adapted to transfer, when the number of target rows determined by the target row determination circuit is equal to or larger than a threshold value, information indicating that the number of target rows reaches the threshold value to a memory controller.

2. The memory of claim 1, wherein the target row is refreshed when the memory controller applies an additional refresh command to the memory in response to the information.

3. The memory of claim 1, wherein when the memory controller applies a refresh command to the memory in response to the information, the target row is refreshed in a refresh operation period in response to the refresh command.

4. The memory of claim 1, wherein the target row is refreshed within a predetermined period of time after the information is transferred without receiving a command from the memory controller.

5. The memory of claim 1, wherein the transfer circuit transfers the information to the memory controller through a data pad.

6. The memory of claim 5, wherein the transfer circuit transfers the information to the memory controller in a predetermined period of time after an activate command is applied from the memory controller.

7. A storage system, comprising:

a memory controller; and

a memory for storing a plurality of data to be transmitted,

wherein the memory comprises:

a transfer circuit adapted to transfer, when the number of target rows determined by the target row determination circuit is equal to or larger than a threshold value, information indicating that the number of target rows reaches the threshold value to a memory controller,

wherein the memory controller is adapted to transmit a command to refresh the target row to the memory upon receiving the information from the memory.

8. The memory system of claim 7, wherein the command is an additional refresh command, and

the memory refreshes the target row in response to the additional refresh command.

9. The memory system of claim 7, wherein the command is a refresh command, and

the memory refreshes the target row in a refresh operation period in response to the refresh command.

10. The memory system of claim 7, wherein the transfer circuit transfers the information to the memory controller through a data pad.

11. The memory system according to claim 10, wherein the transmission circuit transmits the information to the memory controller in a predetermined period after an activation command is applied from the memory controller to the memory.

12. A storage system, comprising:

a memory controller; and

a memory for storing a plurality of data to be transmitted,

wherein the memory comprises:

wherein the memory controller is adapted to not apply a command to the memory for a predetermined period of time after receiving the information from the memory.

13. The memory system of claim 12, wherein the memory refreshes the target row for the predetermined period of time.

14. The memory system according to claim 12, wherein the transmission circuit transmits the information to the memory controller through a data pad in a predetermined period after an activation command is applied from the memory controller to the memory.

15. A method for operating a memory system including a memory controller and a memory, the method comprising:

determining, by the memory, a line that is likely to lose data among a plurality of lines as a target line;

determining, by the memory, whether a number of target rows reaches a threshold; and

communicating, by the memory, information indicating that the number of target rows reaches a threshold value to the memory controller.

16. The method of claim 15, further comprising:

transmitting, by the memory controller, an additional refresh command to the memory in response to the information; and

refreshing, by the memory, the target row in response to the additional refresh command.

17. The method of claim 16, further comprising:

transmitting, by the memory controller, a refresh command from the memory controller to the memory in response to the information; and

refreshing, by the memory, the target row in a refresh operation period in response to the refresh command.

18. The method of claim 16, further comprising:

refreshing, by the memory, the target row in a predetermined period of time after the information is transmitted without receiving a command from the memory controller.

19. A method for operating a memory, the method comprising:

determining an adjacent row disposed adjacent to the row activated for too many times as a target row;

checking whether the number of the target rows reaches a threshold value;

notifying a memory controller when the number of target rows reaches the threshold; and

and executing a refreshing operation on the target row.

20. The method of claim 19, wherein the refresh operation is performed on the target row in a predetermined period of time after the memory controller is notified without receiving a command from the memory controller.