CN112925293B - Method, system, device, processor and storage medium for realizing detection aiming at different load feedback waveforms of BCM (binary coded modulation) - Google Patents
Method, system, device, processor and storage medium for realizing detection aiming at different load feedback waveforms of BCM (binary coded modulation) Download PDFInfo
- Publication number
- CN112925293B CN112925293B CN202110095918.9A CN202110095918A CN112925293B CN 112925293 B CN112925293 B CN 112925293B CN 202110095918 A CN202110095918 A CN 202110095918A CN 112925293 B CN112925293 B CN 112925293B
- Authority
- CN
- China
- Prior art keywords
- sampling
- request
- load
- queue
- judging whether
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0259—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterized by the response to fault detection
- G05B23/0262—Confirmation of fault detection, e.g. extra checks to confirm that a failure has indeed occurred
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24065—Real time diagnostics
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to a method for realizing detection aiming at different load feedback waveforms of a BCM (binary coded modulation), which comprises the steps of adjusting the sampling rate and the sampling width of each load according to the control mode of the load, and configuring ADC (analog to digital converter) resources and channels; according to the control state of the load, adding the sampling requests into the queues of the corresponding resources in sequence; and loading the information in the request queue according to the state of the DMA to realize sampling. The invention also relates to a corresponding system, device, processor and computer readable storage medium thereof. By adopting the method, the system, the device, the processor and the computer readable storage medium for realizing detection aiming at different load feedback waveforms of the BCM, the load adopts a table management mode, can adjust the sampling rate and the sampling width according to the actual load, and is easy to maintain. And the system calls ADC management and DMA management periodically, a certain load is added into a corresponding request queue when needing sampling, and then one-time sampling of the certain load is completed according to an idle state allocation request of the DMA, so that the high-efficiency utilization of resources is realized. When the design is carried out, the number of ADC and DMA resources is checked, and the logic processing of software can still be completely universal when the ADC resources and the DMA resources are changed.
Description
Technical Field
The invention relates to the technical field of automobile electronic control, in particular to a method, a system, a device, a processor and a computer readable storage medium for realizing detection aiming at different load feedback waveforms of a BCM (binary coded modulation).
Background
BCM is used as an important component of automobile body electronics, and is used for detecting overcurrent and overload by using load feedback in order to protect devices. The BCM controls various loads, such as halogen lamps, LED lamps, electromagnetic valves and the like, the control modes are different, some loads need direct driving, and some loads need PWM driving. The feedback waveforms are then also different, especially for loads that behave in PWM form.
Therefore, it is necessary to provide a method for detecting different feedback waveforms and improving the versatility of software.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method, a system, a device, a processor and a computer readable storage medium thereof, which are simple and convenient to operate, good in universality and wide in application range and can realize detection of different load feedback waveforms of BCM.
To achieve the above object, the present invention provides a method, system, apparatus, processor and computer readable storage medium for detecting different load feedback waveforms of BCM, comprising:
the method for realizing detection aiming at different load feedback waveforms of the BCM is mainly characterized by comprising the following steps:
(1) according to the control mode of the load, adjusting the sampling rate and the sampling width of each load, and configuring ADC resources and channels;
(2) according to the control state of the load, adding the sampling requests into the queues of the corresponding resources in sequence;
(3) and loading the information in the request queue according to the state of the DMA to realize sampling.
Preferably, the step (1) further comprises the following steps:
and calculating the sampling capacity according to the sampling rate and the sampling width of different feedback waveforms, and allocating a proper storage space.
Preferably, the step (2) specifically comprises the following steps:
(2.1) sequentially taking out the control states from the loads;
(2.2) judging whether the current load is in an output state, if so, pointing to a preset AD channel; otherwise, switching to the next load;
(2.3) judging whether the AD channel belongs to the ADC0, if so, firstly setting a sampling rate for the AD channel, and then calculating the sampling capacity by using the sampling width; otherwise, continuing the step (2.6);
(2.4) packaging the AD channel address and the sampling capacity corresponding to the ADC0 to generate request information;
(2.5) adding the generated request information into the queue 0 by using a queue management mode;
(2.6) judging whether the AD channel belongs to ADC1, if so, firstly setting a sampling rate for the AD channel, and then calculating a sampling capacity by using a sampling width; otherwise, continuing the step (2.9);
(2.7) packaging the AD channel address and the sampling capacity corresponding to the ADC1 to generate request information;
(2.8) adding the generated request information into the queue 1 by using a queue management mode;
(2.9) judging whether all the loads are inquired, if so, finishing the step; otherwise, switching to the next load and continuing to the step (2.3).
Preferably, the step (3) specifically includes the following steps:
(3.1) judging whether the DMA0 is in an idle state, if so, continuing to the step (3.2); otherwise, configuring DMA information;
(3.2) judging whether the request queue 0 is empty, if so, continuing to the step (3.3); otherwise, continuing the step (3.4);
(3.3) judging whether the request state of the current member pointed by the request queue is finished, if so, removing the current member from the request queue 0 if the request of the current member in the queue 0 finishes sampling, then pointing the queue to the next member, and taking out the request information; otherwise, continuing the step (3.4);
(3.4) judging whether the request queue 1 is not empty, if so, continuing to the step (3.5); otherwise, exiting the step;
(3.5) judging whether the request state of the current member pointed by the request queue 1 is completed, if so, completing sampling of the request of the current member, removing the current member from the request queue 1, wherein the queue points to the next member, taking out the request information, and configuring DMA0 information; otherwise, the step is exited.
Preferably, the step (3) further comprises the following steps:
(3.6) configuring a source address of the DMA0 to point to a channel address corresponding to the ADC0 or the ADC1, starting a DMA function and starting AD conversion, wherein the number of sampling points is the length of a target address;
(3.7) judging whether the DMA1 is in an idle state, if so, continuing to the step (3.8); otherwise, exiting the step;
(3.8) judging whether the request queue 0 is not empty, if so, continuing to the step (3.9); otherwise, continuing to judge the request queue 1 and continuing to step (3.10);
(3.9) judging whether the request state of the current member pointed by the request queue is completed, and if so, removing the current member from the request queue 0. Then the queue points to the next member, takes out the request information and configures the DMA 1; otherwise, continuing the step (3.10);
(3.10) judging whether the request queue 1 is empty, if so, continuing to the step (3.11); otherwise, exiting the step;
(3.11) judging whether the request state of the current member pointed by the request queue is completed, and if so, removing the current member from the request queue 1. Then the queue points to the next member and takes out the request information; otherwise, the step is exited.
Preferably, the source address of the DMA1 configured in step (1) points to the channel address corresponding to the ADC0 or ADC1, and the number of sampling points is the length of the target address.
The system for realizing detection aiming at different load feedback waveforms of the BCM is mainly characterized by comprising the following steps:
the ADC resource and channel configuration module is used for adjusting the sampling rate and the sampling width of each load according to the control mode of the load and configuring ADC resources and channels;
the sampling request adding module is used for sequentially adding the sampling requests into the queues of the corresponding resources according to the control state of the load;
and the sampling processing module is used for loading the information in the request queue according to the state of the DMA to realize sampling.
The device for realizing detection aiming at different load feedback waveforms of the BCM is mainly characterized by comprising the following components:
a processor configured to execute computer-executable instructions;
a memory storing one or more computer-executable instructions that, when executed by the processor, are configured to implement the steps of the method for detecting different load feedback waveforms of a BCM as described above.
The processor for implementing detection of different load feedback waveforms of the BCM is mainly characterized in that the processor is configured to execute computer-executable instructions, and the computer-executable instructions, when executed by the processor, are used for implementing the steps of the method for implementing detection of different load feedback waveforms of the BCM.
The computer-readable storage medium is characterized by having stored thereon a computer program executable by a processor to perform the steps of the above-described method for detecting different load feedback waveforms of a BCM.
By adopting the method, the system, the device, the processor and the computer readable storage medium for realizing detection aiming at different load feedback waveforms of the BCM, the load adopts a table management mode, can adjust the sampling rate and the sampling width according to the actual load, and is easy to maintain. And the system calls ADC management and DMA management periodically, a certain load is added into a corresponding request queue when needing sampling, and then one-time sampling of the certain load is completed according to an idle state allocation request of the DMA, so that the high-efficiency utilization of resources is realized. When the design is carried out, the number of ADC resources and DMA resources is checked, so that the logic processing of software can still be completely universal when the ADC resources and the DMA resources are changed.
Drawings
Fig. 1 is a schematic diagram of the load, ADC and DMA linkage for implementing the method of detecting different load feedback waveforms of BCM according to the present invention.
Fig. 2 is a flowchart illustrating ADC management for implementing the method for detecting different load feedback waveforms of BCM according to the present invention.
Fig. 3 is a flow chart of DMA management for implementing the method for detecting different load feedback waveforms of BCM according to the present invention.
Detailed Description
In order that the technical contents of the present invention can be more clearly described, the present invention will be further described with reference to specific embodiments.
The method for detecting different load feedback waveforms of the BCM comprises the following steps:
(1) according to the control mode of the load, adjusting the sampling rate and the sampling width of each load, and configuring ADC resources and channels;
calculating sampling capacity according to the sampling rate and the sampling width of different feedback waveforms, and allocating a proper storage space;
(2) according to the control state of the load, adding the sampling requests into the queues of the corresponding resources in sequence;
(2.1) sequentially taking out the control states from the load;
(2.2) judging whether the current load is in an output state, if so, pointing to a preset AD channel; whether or not
Then, switching to the next load;
(2.3) judging whether the AD channel belongs to the ADC0, if so, setting a sampling rate for the AD channel, and then calculating the sampling capacity by using the sampling width; otherwise, continuing the step (2.6);
(2.4) packaging the AD channel address and the sampling capacity corresponding to the ADC0 to generate request information;
(2.5) adding the generated request information into the queue 0 by using a queue management mode;
(2.6) judging whether the AD channel belongs to the ADC1, if so, firstly setting a sampling rate for the AD channel, and then setting a sampling rate for the AD channel
Calculating sampling capacity by using the sampling width; otherwise, continuing the step (2.9);
(2.7) packaging the AD channel address and the sampling capacity corresponding to the ADC1 to generate request information;
(2.8) adding the generated request information into the queue 1 by using a queue management mode;
(2.9) judging whether all the loads are inquired, if so, finishing the step; otherwise, switching to the next load, and continuing the step (2.3);
(3) loading information in the request queue according to the state of the DMA to realize sampling;
(3.1) judging whether the DMA0 is in an idle state, if so, continuing to the step (3.2); otherwise, configuring DMA information;
(3.2) judging whether the request queue 0 is empty, if so, continuing to the step (3.3); otherwise, continuing the step (3.4);
(3.3) judging whether the request state of the current member pointed by the request queue is finished, if so, removing the current member from the request queue 0 if the request of the current member in the queue 0 finishes sampling, then pointing the queue to the next member, and
taking out the request information; otherwise, continuing the step (3.4);
(3.4) judging whether the request queue 1 is not empty, if so, continuing to the step (3.5); otherwise, exiting the step;
(3.5) judging whether the request state of the current member pointed by the request queue 1 is completed, if so, completing sampling of the request of the current member, removing the current member from the request queue 1, wherein the queue points to the next member, taking out the request information, and configuring DMA0 information; otherwise, the step is exited.
(3.6) configuring the source address of the DMA0 to point to the channel address corresponding to the ADC0 or the ADC1, and taking the number of sampling points as a target
The length of the address, starting DMA function, and starting AD conversion;
(3.7) judging whether the DMA1 is in an idle state, if so, continuing to the step (3.8); otherwise, exiting the step;
(3.8) judging whether the request queue 0 is not empty, if so, continuing to the step (3.9); otherwise, continue to judge and ask
Finding the queue 1 and continuing the step (3.10);
(3.9) judging whether the request state of the current member pointed by the request queue is completed, and if so, removing the current member from the request queue 0. Then the queue points to the next member, takes out the request information and configures the DMA 1; otherwise, it is continued
Continuing the step (3.10);
(3.10) judging whether the request queue 1 is empty, if so, continuing to the step (3.11); otherwise, exiting the step;
(3.11) judging whether the request state of the current member pointed by the request queue is completed, if so, removing the current member from the request queue 1. Then the queue points to the next member and takes out the request information; otherwise, the step is exited.
As a preferred embodiment of the present invention, in the step (1), the source address of the DMA1 is configured to point to the channel address corresponding to the ADC0 or the ADC1, and the number of sampling points is the length of the target address.
As a preferred embodiment of the present invention, the system for detecting different load feedback waveforms of BCM is implemented, which includes:
the ADC resource and channel configuration module is used for adjusting the sampling rate and the sampling width of each load according to the control mode of the load and configuring ADC resources and channels;
the sampling request adding module is used for sequentially adding the sampling requests into the queues of the corresponding resources according to the control state of the load;
and the sampling processing module is used for loading the information in the request queue according to the state of the DMA to realize sampling.
As a preferred embodiment of the present invention, the apparatus for implementing detection for different load feedback waveforms of BCM includes:
a processor configured to execute computer-executable instructions;
a memory storing one or more computer-executable instructions that, when executed by the processor, perform the steps of the above-described method for implementing detection of different load feedback waveforms of a BCM.
As a preferred embodiment of the present invention, the processor for implementing detection for BCM different load feedback waveforms is configured to execute computer-executable instructions, which when executed by the processor, implement the above-mentioned steps of implementing the method for detecting BCM different load feedback waveforms.
As a preferred embodiment of the present invention, the computer readable storage medium has stored thereon a computer program executable by a processor to perform the steps of the above-described method for detecting different load feedback waveforms of a BCM.
In a specific embodiment of the present invention, a general detection method for different load feedback waveforms of BCM is provided, which includes: adjusting the sampling rate and the sampling width according to the load, and configuring ADC resources and channels; according to the control state of the load, adding the sampling request information into the queue of the corresponding resource in sequence; and loading the request information in the queue according to the state of the DMA to realize sampling. The invention realizes software generalization and improves the utilization rate of MCU resources.
According to the background, the invention designs a universal detection method for different load feedback waveforms of the BCM.
The AD function of the MCU is utilized to realize single sampling, the sampling rate is set according to different load feedback waveforms, the time requirement is high, the higher sampling rate is set, the single sampling time is shortened, and the loss of sampling points is avoided;
then, the DMA function is utilized to realize interval sampling, the sampling width is reasonably set, and if enough data can be obtained in a short time through feedback, the smaller sampling width is set; otherwise, the sampling width is increased, and incomplete waveforms are avoided;
calculating sampling capacity according to sampling rates and sampling widths of different feedback waveforms, and allocating a proper storage space; and a plurality of DMA channels work in parallel, and after a certain channel finishes sampling, the load waiting for sampling is immediately put into use. The memory space is RAM, which is used as the target address of DMA and is used for recording the sampling result.
According to the method, enough waveform data can be obtained only by setting reasonable sampling rate and sampling width for different load feedback waveforms for fault detection, software logic is completely common, and resource utilization is efficient.
The general detection method for feedback waveforms of different loads of the BCM comprises the following steps: according to the control mode of the load, adjusting the sampling rate and the sampling width of each load; a method for adding the sampling requests into the queue in sequence according to the control state of the load; and loading the information in the request queue according to the state of the DMA.
The method for adjusting the sampling rate and the sampling width of each load further comprises the following steps:
a load characteristic table and load members, and a sampling rate and a sampling width in the load members; the load characteristics table points to the manner in which the ADC resources and channels are managed in the ADC.
The method for adding the sampling requests into the queue in sequence further comprises the following steps:
the control state and the scheduling method of the load members in the load characteristic table; request queues corresponding to ADC resources; requesting the AD channel address and the sampling capacity packed in the queue; the request queue points to the way the channels are allocated in the DMA management.
The method for loading the information in the request queue further comprises the following steps:
judging the DMA channel state; the status of the request queue and the completion of the requests in the queue; a method for updating request completion status and managing request queue when DMA is completed; and requesting the packed information in the queue to configure the DMA.
FIG. 1 shows a schematic diagram of the load, ADC and DMA linkage:
s101, establishing a load characteristic table, wherein each load is preset with a sampling rate and a sampling width and points to a certain channel of a certain ADC resource.
S102, when a certain AD channel pointed by a certain load needs to execute sampling, a request is generated and added into a request queue of a corresponding resource according to the sequence.
S103, checking the occupation condition of the current DMA channel according to the request sequence in S102, allocating the requests in the queue to an idle channel, and then starting interval sampling once.
Fig. 2 shows a flow chart of ADC management:
s201, taking out the control state from the load in sequence.
S202, judging whether the current load is in an output state or not.
And S203, if the current load is not in the output, switching to the next load.
And S204, if the current load is in an output state, pointing to a preset AD channel.
S205, whether the AD channel belongs to the ADC0 is judged.
And S206, if the channel is the ADC0 channel, setting a sampling rate for the AD channel, and calculating the sampling capacity by using the sampling width.
And S207, packaging the AD channel address and the sampling capacity corresponding to the ADC0 to generate request information.
S208, adding the generated request information into the queue 0 by using a queue management mode.
S209, judging whether the AD channel belongs to the ADC 1.
And S210, if the channel of the ADC1 is adopted, setting a sampling rate for the AD channel, and calculating the sampling capacity by using the sampling width.
And S211, packaging the AD channel address and the sampling capacity corresponding to the ADC1 to generate request information.
S212, the generated request information is added into the queue 1 by using a queue management mode.
S213, judging whether all the loads are inquired, if so, ending; if not, the process returns to S203.
The ADC management is called by a system cycle, and is executed according to the process every time, so that all loads needing to be sampled are added into a request queue.
FIG. 3 shows a DMA management flow chart:
s301, judge DMA0 is in idle state.
S302, if the DMA0 is in an idle state currently, judging whether the request queue 0 is empty.
S303, if the request queue 0 is not empty, judging whether the request state of the current member pointed by the request queue is finished.
S304, if the request of the current member in the queue 0 finishes sampling, removing the current member from the request queue 0. The queue then points to the next member and fetches the request message.
S305, if the request queue 0 is empty or the determination in S303 is not satisfied, determine whether the request queue 1 is empty.
S306, if the request queue 1 is not empty, judging whether the request state of the current member pointed by the request queue is finished. If the request state is not completed, the process is directly exited.
S307, if the request of the current member in the queue 1 completes sampling, the current member is removed from the request queue 1. The queue then points to the next member and fetches the request message.
S308, configuring the source address of the DMA0 to point to the channel address corresponding to the ADC0 or the ADC1, wherein the number of sampling points is the length of the target address. Then starting DMA function and starting AD conversion.
S309, if the DMA0 is not in the idle state, whether the DMA1 is in the idle state is judged. If the DMA1 is not in the idle state, the process is directly exited.
S310, if the DMA1 is in the idle state currently, judging whether the request queue 0 is empty.
S311, if the request queue 0 is not empty, judging whether the request state of the current member pointed by the request queue is finished.
S312, if the request of the current member in the queue 0 completes the sampling, the current member is removed from the request queue 0. The queue then points to the next member and fetches the request message.
S313, if the request queue 0 is empty or the determination in S310 is not satisfied, determine whether the request queue 1 is empty.
S314, if the request queue 1 is not empty, judging whether the request state of the current member pointed by the request queue is finished. If the request state is not completed, the process is directly exited.
S315, if the sampling of the request of the current member in the queue 1 is completed, removing the current member from the request queue 1. The queue then points to the next member and fetches the request message.
S316, configuring the source address of the DMA1 to point to the channel address corresponding to the ADC0 or the ADC1, wherein the number of sampling points is the length of the target address. Then starting DMA function and starting AD conversion.
The DMA management is called by the system cycle, is executed according to the process each time, and updates the completion state of the current request by using the DMA interruption generated when the interval sampling is completed, thereby completing one interval sampling of a certain load.
For a specific implementation of this embodiment, reference may be made to the relevant description in the above embodiments, which is not described herein again.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that the terms "first," "second," and the like in the description of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, the meaning of "a plurality" means at least two unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by suitable instruction execution devices. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
By adopting the method, the system, the device, the processor and the computer readable storage medium for realizing detection aiming at different load feedback waveforms of the BCM, the load adopts a table management mode, can adjust the sampling rate and the sampling width according to the actual load, and is easy to maintain. The system calls ADC management and DMA management periodically, a certain load is added into a corresponding request queue when needing sampling, and then one-time sampling of the certain load is completed according to the idle state distribution request of the DMA, so that the high-efficiency utilization of resources is realized. When the design is carried out, the number of ADC resources and DMA resources is checked, so that the logic processing of software can still be completely universal when the ADC resources and the DMA resources are changed.
In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (10)
1. A method for realizing detection aiming at different load feedback waveforms of a BCM (binary coded modulation), is characterized by comprising the following steps:
(1) according to the control mode of the load, adjusting the sampling rate and the sampling width of each load, and configuring ADC resources and channels;
(2) according to the control state of the load, adding the sampling requests into the queues of the corresponding resources in sequence;
(3) loading information in the request queue according to the state of the DMA to realize sampling;
the method further comprises the following steps:
single sampling is realized by using the AD function of the MCU, and the sampling rate is set according to different load feedback waveforms;
then, the DMA function is utilized to realize interval sampling, the sampling width is reasonably set, and if sufficient data can be obtained in a short time through feedback, the smaller sampling width is set; otherwise, increasing the sampling width;
calculating sampling capacity according to sampling rates and sampling widths of different feedback waveforms, and allocating a proper storage space; and a plurality of DMA channels work in parallel, and after a certain channel finishes sampling, the load waiting for sampling is immediately put into use.
2. The method of claim 1, wherein the step (1) further comprises the steps of:
and calculating the sampling capacity according to the sampling rate and the sampling width of different feedback waveforms, and allocating a proper storage space.
3. The method according to claim 1, wherein the step (2) specifically comprises the following steps:
(2.1) sequentially taking out the control states from the loads;
(2.2) judging whether the current load is in an output state, if so, pointing to a preset AD channel; otherwise, switching to the next load;
(2.3) judging whether the AD channel belongs to the ADC0, if so, setting a sampling rate for the AD channel, and then calculating the sampling capacity by using the sampling width; otherwise, continuing the step (2.6);
(2.4) packaging the AD channel address and the sampling capacity corresponding to the ADC0 to generate request information;
(2.5) adding the generated request information into the queue 0 by using a queue management mode;
(2.6) judging whether the AD channel belongs to ADC1, if so, firstly setting a sampling rate for the AD channel, and then calculating a sampling capacity by using a sampling width; otherwise, continuing the step (2.9);
(2.7) packaging the AD channel address and the sampling capacity corresponding to the ADC1 to generate request information;
(2.8) adding the generated request information into the queue 1 by using a queue management mode;
(2.9) judging whether all the loads are inquired, if so, finishing the step; otherwise, switching to the next load and continuing to the step (2.3).
4. The method according to claim 1, wherein the step (3) specifically comprises the following steps:
(3.1) judging whether the DMA0 is in an idle state, if so, continuing to the step (3.2); otherwise, configuring DMA information;
(3.2) judging whether the request queue 0 is empty, if so, continuing to the step (3.3); otherwise, continuing the step (3.4);
(3.3) judging whether the request state of the current member pointed by the request queue is finished, if so, removing the current member from the request queue 0 if the request of the current member in the queue 0 finishes sampling, then pointing the queue to the next member, and taking out the request information; otherwise, continuing the step (3.4);
(3.4) judging whether the request queue 1 is not empty, if so, continuing to the step (3.5); otherwise, the step is exited;
(3.5) judging whether the request state of the current member pointed by the request queue 1 is completed, if so, completing sampling of the request of the current member, removing the current member from the request queue 1, wherein the queue points to the next member, taking out the request information, and configuring DMA0 information; otherwise, the step is exited.
5. The method of claim 4, wherein the step (3) further comprises the steps of:
(3.6) configuring a source address of the DMA0 to point to a channel address corresponding to the ADC0 or the ADC1, starting a DMA function and starting AD conversion, wherein the number of sampling points is the length of a target address;
(3.7) judging whether the DMA1 is in an idle state, if so, continuing to the step (3.8); otherwise, the step is exited;
(3.8) judging whether the request queue 0 is not empty, if so, continuing to the step (3.9); otherwise, continuing to judge the request queue 1 and continuing to step (3.10);
(3.9) judging whether the request state of the current member pointed by the request queue is completed, and if so, removing the current member from the request queue 0. Then the queue points to the next member, takes out the request information and configures the DMA 1; otherwise, continuing the step (3.10);
(3.10) judging whether the request queue 1 is empty, if so, continuing to the step (3.11); otherwise, exiting the step;
(3.11) judging whether the request state of the current member pointed by the request queue is completed, if so, removing the current member from the request queue 1. Then the queue points to the next member and takes out the request information; otherwise, the step is exited.
6. The method of claim 5, wherein the source address of the DMA1 configured in step (1) points to the channel address corresponding to the ADC0 or ADC1, and the number of sampling points is the length of the target address.
7. A system for implementing detection for different load feedback waveforms of a BCM, the system comprising:
the ADC resource and channel configuration module is used for adjusting the sampling rate and the sampling width of each load according to the control mode of the load and configuring ADC resources and channels;
the sampling request adding module is used for sequentially adding the sampling requests into the queues of the corresponding resources according to the control state of the load;
and the sampling processing module is used for loading the information in the request queue according to the state of the DMA to realize sampling.
8. An apparatus for implementing detection for different load feedback waveforms of a BCM, the apparatus comprising:
a processor configured to execute computer-executable instructions;
memory storing one or more computer-executable instructions for implementing the steps of any one of claims 1 to 6 for implementing the method of detecting different load feedback waveforms of a BCM when executed by the processor.
9. A processor configured to execute computer-executable instructions for implementing detection for BCM distinct load feedback waveforms, wherein the computer-executable instructions, when executed by the processor, implement the steps of the method of implementing detection for BCM distinct load feedback waveforms as claimed in any one of claims 1 to 6.
10. A computer-readable storage medium, having stored thereon a computer program executable by a processor to perform the steps of any of claims 1 to 6 of a method of performing detection for different load feedback waveforms of a BCM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110095918.9A CN112925293B (en) | 2021-01-25 | 2021-01-25 | Method, system, device, processor and storage medium for realizing detection aiming at different load feedback waveforms of BCM (binary coded modulation) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110095918.9A CN112925293B (en) | 2021-01-25 | 2021-01-25 | Method, system, device, processor and storage medium for realizing detection aiming at different load feedback waveforms of BCM (binary coded modulation) |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112925293A CN112925293A (en) | 2021-06-08 |
| CN112925293B true CN112925293B (en) | 2022-09-06 |
Family
ID=76166925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110095918.9A Active CN112925293B (en) | 2021-01-25 | 2021-01-25 | Method, system, device, processor and storage medium for realizing detection aiming at different load feedback waveforms of BCM (binary coded modulation) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112925293B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5978742A (en) * | 1997-04-04 | 1999-11-02 | Tektronix, Inc. | Method and apparatus for digital sampling of electrical waveforms |
| CN101577535A (en) * | 2003-03-21 | 2009-11-11 | D2音频有限公司 | Device and method for sample rate conversion |
| CN102512176A (en) * | 2011-12-06 | 2012-06-27 | 中国科学院深圳先进技术研究院 | Digital signal processing method for light-frequency conversion type pulse oximeter |
| CN102637031A (en) * | 2012-05-11 | 2012-08-15 | 长沙邦胜电子科技有限公司 | Industrial energy-saving monitoring system based on wireless sensor network |
| CN202947939U (en) * | 2012-12-05 | 2013-05-22 | 北京理工大学 | Striking equivalent underwater explosion impact loading experiment testing device system |
| CN103235174A (en) * | 2013-04-26 | 2013-08-07 | 广西电网公司电力科学研究院 | Voltage online monitoring device for power system |
| CN103424608A (en) * | 2013-07-31 | 2013-12-04 | 江苏林洋电子股份有限公司 | Low cost rapid high precision alternating voltage signal sampling system |
| CN110609499A (en) * | 2019-09-18 | 2019-12-24 | 深圳市航顺芯片技术研发有限公司 | Method and device for switching analog-to-digital converter (ADC) real-time sampling and non-real-time sampling |
| CN111521866A (en) * | 2020-05-15 | 2020-08-11 | 湖南银河电气有限公司 | Gyro motor output power stability monitoring method and device |
| CN111726047A (en) * | 2020-06-29 | 2020-09-29 | 德尔福科技(苏州)有限公司 | Rotary transformer software decoding method suitable for motor control |
| CN111929685A (en) * | 2020-08-03 | 2020-11-13 | 启航汽车有限公司 | Radar detection method and device based on linear frequency modulation continuous wave, radar device and motor vehicle |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4316282A (en) * | 1979-11-23 | 1982-02-16 | Rca Corporation | Multichannel frequency translation of sampled waveforms by decimation and interpolation |
| US5342990A (en) * | 1990-01-05 | 1994-08-30 | E-Mu Systems, Inc. | Digital sampling instrument employing cache-memory |
| EP0750290B1 (en) * | 1995-06-19 | 2002-09-25 | Yamaha Corporation | Method and device for forming a tone waveform by combined use of different waveform sample forming resolutions |
| US5784284A (en) * | 1995-12-29 | 1998-07-21 | Snap-On Tools Company | Technique for plotting a variable-width signal in a fixed-width plot area |
| CN2678250Y (en) * | 2004-01-09 | 2005-02-09 | 李剑 | PWM controller using DMA technology |
| JP4729273B2 (en) * | 2004-06-21 | 2011-07-20 | アンリツ株式会社 | Frequency detection method, sampling device, and waveform observation system |
| US7834574B2 (en) * | 2007-11-26 | 2010-11-16 | Gm Global Technology Operations, Inc. | Phase current sampling and regulating apparatus and methods, and electric motor drive systems |
| US7933027B1 (en) * | 2008-06-27 | 2011-04-26 | The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration | Processing waveform-based NDE |
| CN109710548A (en) * | 2018-12-21 | 2019-05-03 | 荆门博谦信息科技有限公司 | A kind of DMA control data transmission method, system and equipment |
-
2021
- 2021-01-25 CN CN202110095918.9A patent/CN112925293B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5978742A (en) * | 1997-04-04 | 1999-11-02 | Tektronix, Inc. | Method and apparatus for digital sampling of electrical waveforms |
| CN101577535A (en) * | 2003-03-21 | 2009-11-11 | D2音频有限公司 | Device and method for sample rate conversion |
| CN102512176A (en) * | 2011-12-06 | 2012-06-27 | 中国科学院深圳先进技术研究院 | Digital signal processing method for light-frequency conversion type pulse oximeter |
| CN102637031A (en) * | 2012-05-11 | 2012-08-15 | 长沙邦胜电子科技有限公司 | Industrial energy-saving monitoring system based on wireless sensor network |
| CN202947939U (en) * | 2012-12-05 | 2013-05-22 | 北京理工大学 | Striking equivalent underwater explosion impact loading experiment testing device system |
| CN103235174A (en) * | 2013-04-26 | 2013-08-07 | 广西电网公司电力科学研究院 | Voltage online monitoring device for power system |
| CN103424608A (en) * | 2013-07-31 | 2013-12-04 | 江苏林洋电子股份有限公司 | Low cost rapid high precision alternating voltage signal sampling system |
| CN110609499A (en) * | 2019-09-18 | 2019-12-24 | 深圳市航顺芯片技术研发有限公司 | Method and device for switching analog-to-digital converter (ADC) real-time sampling and non-real-time sampling |
| CN111521866A (en) * | 2020-05-15 | 2020-08-11 | 湖南银河电气有限公司 | Gyro motor output power stability monitoring method and device |
| CN111726047A (en) * | 2020-06-29 | 2020-09-29 | 德尔福科技(苏州)有限公司 | Rotary transformer software decoding method suitable for motor control |
| CN111929685A (en) * | 2020-08-03 | 2020-11-13 | 启航汽车有限公司 | Radar detection method and device based on linear frequency modulation continuous wave, radar device and motor vehicle |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112925293A (en) | 2021-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20150301854A1 (en) | Apparatus and method for hardware-based task scheduling | |
| US20170329632A1 (en) | Device scheduling method, task manager and storage medium | |
| WO2009153620A1 (en) | A system, method and computer program product for scheduling a processing entity task | |
| CN112988362B (en) | Task processing method and device, electronic equipment and storage medium | |
| US8581765B2 (en) | Low-memory-usage arbitrary waveform representation or generation | |
| EP2565786A1 (en) | Information processing device and task switching method | |
| CN113627775B (en) | Scheduling method, device, equipment and storage medium of robot | |
| JP5040050B2 (en) | Multi-channel DMA controller and processor system | |
| CN114510339B (en) | Computing task scheduling method and device, electronic equipment and readable storage medium | |
| CN106776395A (en) | A kind of method for scheduling task and device of shared cluster | |
| CN105677744A (en) | Method and apparatus for increasing service quality in file system | |
| WO2023066233A1 (en) | Program flashing method and apparatus for controller, and controller and storage medium | |
| CN108279976B (en) | Compiling resource scheduling method, computer and computer readable storage medium | |
| CN112925293B (en) | Method, system, device, processor and storage medium for realizing detection aiming at different load feedback waveforms of BCM (binary coded modulation) | |
| CN105138489A (en) | ID management unit for cache space of network data packages | |
| KR100841548B1 (en) | Processing system | |
| CN108292236B (en) | Information processing method and device | |
| US7245248B2 (en) | A/D converter and a microcontroller including the same | |
| CN111143068B (en) | File operation method and device and embedded controller | |
| CN112559403A (en) | Processor and interrupt controller therein | |
| CN112463028B (en) | I/O processing method, system, equipment and computer readable storage medium | |
| CN109522121A (en) | A kind of memory application method, device, terminal and computer readable storage medium | |
| CN112463027B (en) | I/O processing method, system, equipment and computer readable storage medium | |
| CN113806035A (en) | Distributed scheduling method and service server | |
| CN110045911B (en) | Analog-to-digital conversion control circuit and singlechip analog-to-digital conversion circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |