CN112925139A - Control switch of drive circuit, array substrate and display panel - Google Patents
Control switch of drive circuit, array substrate and display panel Download PDFInfo
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- CN112925139A CN112925139A CN202110332578.7A CN202110332578A CN112925139A CN 112925139 A CN112925139 A CN 112925139A CN 202110332578 A CN202110332578 A CN 202110332578A CN 112925139 A CN112925139 A CN 112925139A
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- 239000000758 substrate Substances 0.000 title claims abstract description 34
- 239000010409 thin film Substances 0.000 claims abstract description 92
- 239000004973 liquid crystal related substance Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 abstract description 16
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- WABPQHHGFIMREM-AKLPVKDBSA-N lead-210 Chemical compound [210Pb] WABPQHHGFIMREM-AKLPVKDBSA-N 0.000 description 61
- 238000010586 diagram Methods 0.000 description 13
- 230000004888 barrier function Effects 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 230000001154 acute effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
Abstract
The application discloses control switch, array substrate and display panel of a driving circuit, the control switch comprises a thin film transistor, the driving circuit further comprises a source electrode lead connected with the thin film transistor, the thin film transistor comprises a source electrode, a drain electrode and a grid electrode, the source electrode comprises at least two source electrode branches arranged in parallel and a source electrode trunk connected with each source electrode branch; the drain electrode and the source electrode are arranged on the same layer and comprise at least one drain electrode branch, the drain electrode branch is arranged between the adjacent source electrode branches, and the grid electrode is arranged corresponding to the source electrode and the drain electrode; the source lead is connected with the source, and an extension line of the source lead does not overlap with the drain branch. By adopting the driving circuit in the scheme, even if the etching is uneven, the short circuit of the source electrode and the drain electrode can not be caused, and the production yield of products can be improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a control switch of a driving circuit, an array substrate and a display panel.
Background
At present, display technologies are widely applied to televisions, mobile phones, and public information displays, and display panels for displaying pictures are also various and can display rich and colorful pictures. More and more Display panels, such as Thin Film Transistor-Liquid Crystal Display (TFT-LCD) panels, Organic Light Emitting Display (OLED) panels, etc., require a Gate Driver on Array (GOA) technology to integrate an Array substrate line driving circuit on an Array substrate in the Display panel to form a scan Driver for the Display panel, so as to reduce the product cost from both the material cost and the manufacturing process.
In general, when a GOA circuit is manufactured, a source, a drain and a source lead in a thin film transistor are arranged in the same layer and etched at the same time, but the problem of uneven etching is easily caused when an etching process is performed; moreover, as the integration degree of the GOA circuit is higher and higher, the channel spacing between the source and the drain is smaller and smaller, and therefore when the etching is not uniform, the source lead is easily connected with the source and the drain at the same time, so that the source and the drain are short-circuited.
Disclosure of Invention
The application aims to provide a control switch of a driving circuit, an array substrate and a display panel, and the driving circuit is prevented from causing source and drain short circuit when etching is not uniform.
The application discloses control switch of a driving circuit, the control switch comprises a thin film transistor, the driving circuit further comprises a source electrode lead wire connected with the thin film transistor, the thin film transistor comprises a source electrode, a drain electrode and a grid electrode, the source electrode comprises at least two source electrode branches arranged in parallel and a source electrode trunk connected with each source electrode branch; the drain electrode and the source electrode are arranged on the same layer and comprise at least one drain electrode branch and a drain electrode trunk connected with each drain electrode branch, and the drain electrode branches and the source electrode branches are arranged in parallel and alternately to form a channel; the grid is arranged corresponding to the source electrode and the drain electrode, the source electrode lead is connected with the source electrode, and the extension line of the source electrode lead is not overlapped with the drain electrode branch.
Optionally, the source lead is disposed on a side of the source trunk away from the source branch, and is connected to the source trunk, and an extension line of the source lead is parallel to the drain branch.
Optionally, the source electrode branches are connected to two ends of the source electrode trunk and are a first source electrode branch and a second source electrode branch, and at least one source electrode lead is provided and corresponds to at least one of the first source electrode branch and the second source electrode branch.
Optionally, the source branches are connected to two ends of the source trunk and are a first source branch and a second source branch, and the source branches are connected to a region between two ends of the source trunk and are a third source branch, and the third source branches are arranged between the first source branch and the second source branch in parallel; the source electrode lead is provided with at least one and is arranged corresponding to at least one of the first source electrode branch, the second source electrode branch and the third source electrode branch.
Optionally, the width of the source lead is smaller than the distance between two adjacent drain branches.
Optionally, the source branches include a first source branch and a second source branch connected to two ends of the source trunk; the thin film transistor further comprises an extension part, the extension part is connected with the source electrode lead, and the extension part is connected with the end part, far away from the source electrode trunk, of the first source electrode branch and/or the second source electrode branch; in a first direction, the first source branch and/or the second source branch connected with the extension portion protrude from other source branches, and an end portion of the source lead connected with the extension portion protrudes from a side edge of the drain trunk far away from the source; wherein the first direction is an extending direction of the source branch.
Optionally, a third source branch is connected to a region between two ends of the source trunk in the source branches, and the third source branch is arranged between the first source branch and the second source branch in parallel; in the drain electrode branches, a first drain electrode branch and a second drain electrode branch are connected with two ends of the drain electrode main body, a third drain electrode branch is connected with an area between two ends of the drain electrode main body, and the third drain electrode branches are arranged between the first drain electrode branch and the second drain electrode branch in parallel;
the first drain electrode branches are arranged between two adjacent first source electrode branches and the third source electrode branches in parallel, the second drain electrode branches are arranged between two adjacent second source electrode branches and the third source electrode branches in parallel, and the third drain electrode branches are arranged between two adjacent third source electrode branches in parallel; the number of the third drain branches is one less than the number of the third source branches.
Optionally, the driving circuit includes a frame start signal line, a gate voltage control line, a clock signal line, and a plurality of GOA units, an input end of each GOA unit is connected to the frame start signal line, the gate voltage control line, and the clock signal line, and an output end of each GOA unit is connected to the scan line to drive the scan line;
the GOA unit comprises a first thin film transistor, a second thin film transistor, a third thin film transistor and a fourth thin film transistor, wherein a source electrode of the first thin film transistor is respectively connected with the gate voltage control line and a source electrode of the second thin film transistor through two source electrode leads, a drain electrode of the first thin film transistor is respectively communicated with a source electrode of the third thin film transistor and a gate electrode of the fourth thin film transistor, and a gate electrode of the first thin film transistor is connected with a gate electrode of the second thin film transistor;
the drain electrode of the second thin film transistor is connected with the source electrode of the fourth thin film transistor, and the grid electrode of the second thin film transistor is connected with the grid electrode of the fourth thin film transistor; the drain of the third thin film transistor is communicated with the frame start signal line, and the drain of the fourth thin film transistor is communicated with the clock signal line.
The application also discloses an array substrate, which comprises the driving circuit and the scanning line driven by the driving circuit.
The application also discloses a display panel, which comprises the array substrate, a color film substrate arranged opposite to the array substrate, and a liquid crystal layer arranged between the array substrate and the color film substrate.
Compared with the scheme that the source lead is directly and vertically connected with the source branch in the thin film transistor at present, the connection position of the source lead and the source is changed, so that when the metal layer where the source, the drain and the source lead are located is etched unevenly, even if the end part of the source lead is not etched cleanly, the end part of the source lead protrudes from the source branch or the source trunk, the end part of the source lead still cannot intersect with the drain branch because the extension line of the source lead does not overlap with the drain branch; therefore, by adopting the driving circuit, even if the etching is not uniform, the short circuit of the source electrode and the drain electrode can not be caused, and the production yield of products can be improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
FIG. 1 is a schematic plan view of an array substrate;
FIG. 2 is an enlarged view of a portion of FIG. 1 at position M;
FIG. 3 is a schematic illustration of an exemplary GOA in partial section;
FIG. 4 is a partial schematic view of another exemplary GOA;
fig. 5 is a schematic diagram in an ideal state based on fig. 3;
fig. 6 is a schematic diagram in an ideal state based on fig. 4;
FIG. 7 is a partial schematic diagram of a driving circuit according to a first embodiment of the present application;
FIG. 8 is a partial schematic diagram of another driver circuit provided in the first embodiment of the present application;
fig. 9 is a partial schematic diagram of a driving circuit including another type of thin film transistor according to the first embodiment of the present application;
fig. 10 is a partial schematic diagram of a driving circuit including another type of thin film transistor according to the first embodiment of the present application;
FIG. 11 is a partial schematic diagram of a driving circuit according to a second embodiment of the present application;
FIG. 12 is a partial schematic diagram of another driver circuit provided in a second embodiment of the present application;
FIG. 13 is a partial schematic diagram of a driving circuit according to a third embodiment of the present application;
fig. 14 is a schematic diagram of a display panel according to an embodiment of the present application.
100, an array substrate; 200. a drive circuit; 201. a first thin film transistor; 202. a second thin film transistor; 203. a third thin film transistor; 204. a fourth thin film transistor; 210. a source lead; 220. a thin film transistor; 230. a source electrode; 231. a source electrode branch; 232. a first source branch; 233. a second source branch; 234. a third source branch; 235. a source trunk; 240. a drain electrode; 241. a drain branch; 242. a first drain branch; 243. a second drain branch; 244. a third drain branch; 245. a drain stem; 250. an extension portion; 260. a gate electrode; 300. scanning a line; 400. a display panel; 500. a color film substrate; 600. and a liquid crystal layer.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application will now be described in detail with reference to the drawings and alternative embodiments, it being understood that any combination of the various embodiments or technical features described below may form new embodiments without conflict.
As shown in fig. 1 and 2, a schematic plan view of an array substrate is provided, where a scan line 300 is disposed in a display region of the array substrate 100, and a driving circuit 200, which may be an array substrate row driving circuit, is disposed in a non-display region of the array substrate 100, where the driving circuit 200 includes a frame start signal line (STV), a gate voltage control line (VGL), a clock signal line (CKV), and a plurality of GOA units, where input ends of the GOA units are connected to the STV, the VGL, and the CKV, and output ends of the GOA units are connected to the scan line 300, so as to drive the scan line 300; the gate voltage control line is connected to one thin film transistor 220 in the GOA unit through a source lead 210, and charges the thin film transistor 220.
Specifically, the GOA unit includes a first thin film transistor 201, a second thin film transistor 202, a third thin film transistor 203 and a fourth thin film transistor 204, a source 230 of the first thin film transistor 201 is connected to the gate voltage control line and the source 230 of the second thin film transistor 202 through two source leads 210, respectively, a drain 240 of the first thin film transistor 201 is connected to the source 230 of the third thin film transistor 203 and a gate 260 of the fourth thin film transistor 204, respectively, and the gate 260 of the first thin film transistor 201 is connected to the gate 260 of the second thin film transistor 202; a drain electrode 240 of the second thin film transistor 202 is connected to a source electrode 230 of the fourth thin film transistor 204, and a gate electrode 260 of the second thin film transistor 202 is connected to a gate electrode 260 of the fourth thin film transistor 204; the drain 240 of the third thin film transistor 203 is in communication with the frame start signal line, and the drain 240 of the fourth thin film transistor 204 is in communication with the clock signal line.
In the GOA cell shown in fig. 2, there are four interconnected tfts and other traces, and it can be seen that there are three blank areas, namely area a, area B and area C; between the region B and the region C, the two tfts 220 are connected by the source lead 210, before the metal layer is etched into the source 230, the drain 240 and other metal line patterns, an etching barrier layer needs to be formed on the source 230, the drain 240 and other metal line patterns, and then a barrier layer pattern is formed by using a developing solution.
As shown in fig. 3 and 4, which are partial schematic views of two exemplary GOAs, when the metal patterns corresponding to the regions D and E are not etched uniformly, the source lead 210 in fig. 3 and 4 may extend into the channel of the source 230 of the tft 220 and even communicate with the drain 240, resulting in a short circuit between the source and drain 240.
Fig. 5 and 6 are schematic views based on fig. 3 and 4, respectively, in an ideal state, but this requires a large amount of developer to ensure that the barrier layer corresponding to the regions D and E is completely etched, so that the source lead 210 does not protrude from the source 230 and extends into the channel of the source 230 when the metal pattern is etched later.
In view of this, the present application provides a control switch of a driving circuit 200 that still does not cause short circuit between a source 230 and a drain 240 when etching is not uniform, the control switch includes a thin film transistor 220, as shown in fig. 1, fig. 2, and fig. 7 to fig. 13, the thin film transistor 220 in the driving circuit 200 includes a source 230, a drain 240, and a gate 260, the source 230 includes at least two source branches 231 arranged in parallel, and a source trunk 235 connecting the source branches 231; the drain 240 and the source 230 are disposed on the same layer, and include at least one drain branch 241 and a drain trunk 245 connecting each drain branch 241, wherein the drain branches 241 and the source branches 231 are disposed in parallel and alternately to form a channel; the gate 260 is arranged corresponding to the source 230 and the drain 240; the source lead 210 is connected to the source 230, and an extension line of the source lead 210 does not overlap with the drain branch 231.
The source lead 210 may be connected to only the source branch 231, only the source stem 235, or both the source branch 231 and the source stem 235. When there is only one drain branch 241, the drain stem 245 is a part of the drain branch 241 and is connected to other structures in the driving circuit 200. The extension line of the source lead 210 does not overlap the drain branch 241, and further, the source lead 210 does not overlap the drain stem 245 and even the entire drain 240.
According to the method, the connection position of the source lead 210 and the source branch 231 is changed, so that the extension line of the source lead 210 is not overlapped with the drain 240, the source lead 210 is positioned in the region B or the region C, the space of the region B or the region C is further reduced, the consumption of a developing solution in the region B or the region C is reduced, the region D and the region E can obtain more developing energy, the barrier layer corresponding to the region D and the region E is completely etched, and the problem of uneven etching of a metal layer pattern is solved, so that the source lead 210 does not protrude out of the source 230 and extends into a channel of the source 230; moreover, even if the problem of uneven etching occurs, which results in that the end of the source lead 210 is not etched clean when the source lead 210 is etched, so that the end of the source lead 210 protrudes out of the source branch 231, the end of the source lead 210 does not intersect with the drain branch 241 because the extension line of the source lead 210 does not overlap with the drain branch 241; in summary, with the driving circuit 200 of the present disclosure, even if the etching is not uniform, the source 230 and the drain 240 are not shorted, which is beneficial to improving the production yield of the product.
Specifically, the following embodiments are provided to prevent the source 230 and the drain 240 from being short-circuited when the extension line of the source lead 210 does not overlap with the drain 240. As shown in fig. 7-10, the source lead is disposed on a side of the source trunk away from the source branch, and is connected to the source trunk, and an extension line of the source lead is parallel to the drain branch; the source lead is overlapped or even coincident with at least one of the source branches. As shown in fig. 11-13, the source lead is perpendicular to the extension line of the source branch, and the extension line of the source trace does not overlap the drain.
As shown in fig. 7, which is a partial schematic diagram of a driving circuit 200, as an embodiment of the present application, a control switch of the driving circuit 200 is disclosed, the control switch includes a thin film transistor 220, the driving circuit further includes a source lead 210 connected to the thin film transistor 220, the thin film transistor 220 includes a source 230 and a drain 240, the source 230 includes a first source branch 232 and a second source branch 233 arranged in parallel, and a source trunk 235 connecting the first source branch 232 and the second source branch 233, where the first source branch 232, the source trunk 235 and the second source branch 233 form a U-shaped pattern; the drain 240 comprises a first drain branch 242, the first drain branch 242 being disposed between the first source branch 232 and the second source branch 233; the source lead 210 is connected to an end of the first source branch 232, and the source lead 210 and the source branch 231 are located on the same straight line, so that the source lead 210 is also connected to the source stem 235. In this embodiment, the structure of the existing tft 220 is not required to be changed, and only the connection position of the source lead 210 to the first source branch 232 needs to be changed; moreover, when the first source branch 232 or the second source branch 233 is vertically connected to the source trunk 235, the source lead 210 is vertically connected to the source trunk and further connected to the first source branch 232, so that the contact area between the source branch 231 and the thin film transistor 220 is increased, and the charging effect of the source lead 210 on the thin film transistor 220 is improved.
Of course, as shown in fig. 8, the source lead 210 may also be connected to the second source branch 233, or two source leads 210 are provided in the driving circuit 200, one source lead 210 connects the VGL line to the tft 220, and the other source lead 210 connects two tfts 220, that is, one tft is connected to two source leads 210, which is specifically designed according to the use situation and shown in fig. 2; in this case, the source lead 210 is also designed as described above, and a part of the source lead 210 is aligned with the source branch 231.
As shown in fig. 9 and 10, two driving circuits 200 with different types of tfts 220 are illustrated. In fig. 9, among the source branches 231, a first source branch 232 and a second source branch 233 connected to two ends of the source stem 235 are provided, a third source branch 234 connected to a region between two ends of the source stem 235 is provided, the third source branch 234 is disposed between the first source branch 232 and the second source branch 233 and connected to a middle end of the source stem 235, and the source 230 has two parallel connected U-shaped structures; the drain 240 includes a first drain branch 242, a second drain branch 243 and a drain trunk 245, the first drain branch 242 and the second drain branch 243 are respectively connected to two ends of the drain trunk 245, and the drain 240 is U-shaped. The first drain branch 242 is located between the first source branch 232 and the third source branch 234, and the second drain branch 243 is located between the second source branch 233 and the third source branch 234; on the side remote from the drain 240, the source lead 210 is connected to the third source branch 234 and is aligned with the third source branch 234. Of course, the source leads 210 may overlap with the extending direction of the first source branch 232, may overlap with the extending direction of the second source branch 233, or two source leads 210 may be connected to two of the first source branch 232, the second source branch 233, and the third source branch 234, respectively.
In fig. 10, among the source branches 231, a first source branch 232 and a second source branch 233 connected to two ends of the source stem 235, and a third source branch 234 connected to a region between two ends of the source stem 235, the third source branch 234 is disposed in parallel between the first source branch 232 and the second source branch 233, and the source 230 has a plurality of U-shaped structures connected in parallel; the drain 240 includes a first drain branch 242, a second drain branch 243, a drain trunk 245 and at least one third drain branch 244, the first drain branch 242 and the second drain branch 243 are respectively connected to two ends of the drain trunk 245, the third drain branch 244 is disposed between the first drain branch 242 and the second drain branch 243 in parallel and connected to the drain trunk 245, and the drain 240 is also in the shape of a plurality of U-shaped structures connected in parallel.
The first drain branch 242 is located between the first source branch 232 and the third source branch 234, the second drain branch 243 is located between the second source branch 233 and the third source branch 234, and the third drain branch 244 is located between two adjacent third source branches 234. On the side away from the drain 240, the source lead 210 overlaps with the extending direction of the first source branch 232; of course, the source leads may also overlap with the extending direction of the second source branch 233, overlap with the extending direction of the third source branch 234, or two source leads 210 may be respectively connected to two of the first source branch 232, the second source branch 233, and the third source branch 234.
In the present embodiment, all of the source branches 231 and the drain branches 241 are strip-shaped structures, and may be rectangular, oval or other shapes. The extending direction of the source branch 231 is perpendicular to the extending direction of the source trunk 235, and the extending direction of the drain branch 241 is perpendicular to the extending direction of the drain trunk 245; of course, the angle between the extending direction of the source branch 231 and the extending direction of the source trunk 235 may form an acute angle, and the angle between the extending direction of the drain branch 241 and the extending direction of the drain trunk 245 is also an acute angle.
In fig. 7-10, the widths of the source branch 231, the source stem 235, the drain branch 241 and the drain stem 245 are all equal, and the widths of the channels between the adjacent source branch 231 and the drain branch 241 are also equal, so as to improve the conductivity of the thin film transistor 220.
In addition, in order to further prevent the source 230 and the drain 240 from being shorted, the width of the source lead 210 is narrowed in this embodiment, so that the width of the source lead 210 is smaller than the width of the source branch 231, so that more developing energy can be concentrated between the source branch 231 and the drain branch 241 when etching the barrier layer pattern, so that the pattern is completely etched in the subsequent metal pattern etching process; meanwhile, since the width of the source wire 210 is narrow, a barrier pattern required correspondingly when the source wire 210 is etched is narrow, even when the developing energy is insufficient, the barrier pattern is not completely etched, resulting in widening of the side surface of the source wire 210, and since a large space exists between the source wire 210 and the drain branch 241, the source wire 210 is difficult to be connected to the drain electrode 240, resulting in short-circuiting of the source electrode 230 and the drain electrode 240.
Of course, the width of the source lead 210 may be equal to the width of the source branch 231, such that the extension lines of the source lead 210 and the source branch 231 are overlapped, and the conductive effect of the thin film transistor 220 is more uniform. Meanwhile, the width of the source lead 210 can be smaller than the distance between the source branch 231 and the drain branch 241, so that when the source lead 210 is not overlapped with the source branch 231 due to uneven etching, and the source lead 210 is not connected with the drain 240 when the source lead 210 is partially overlapped with the extension line direction of the source branch 231, the source lead 210 is not connected with the drain 240, and the source 230 and the drain 240 are short-circuited.
As shown in fig. 11, which is a partial schematic diagram of another driving circuit 200, as another embodiment of the present application, a control switch of another driving circuit 200 is further disclosed, where the control switch includes a thin film transistor 220, the driving circuit further includes a source lead 210 connected to the thin film transistor 220, the thin film transistor 220 includes a source 230 and a drain 240, the source 230 includes a first source branch 232 and a second source branch 233 arranged in parallel, and a source trunk 235 connected to the first source branch 232 and the second source branch 233, and the first source branch 232 and the second source branch 233 are respectively connected to two ends of the source trunk 235; the drain 240 comprises a first drain branch 242, the first drain branch 242 being arranged in the channel between the first source branch 232 and the second source branch 233.
The thin film transistor 220 further comprises an extension portion 250, wherein the extension portion 250 is connected to an end portion of the first source branch 232 away from the source stem 235, in a first direction, the first source branch connected to the extension portion 250 protrudes out of other source branches, and an end portion of the source lead connected to the extension portion protrudes out of a side edge of the drain stem away from the source; wherein the first direction is an extending direction of the source branch.
In this embodiment, after the first source branch 232 is extended toward the drain 240, the extended portion forms an extension 250, and the extension 250 protrudes from the drain 240, so that the source lead 210 is connected to the portion of the extension 250 protruding from the drain 240, and the extension of the source 230 does not overlap with the drain 240. Therefore, the shape of the source wire 210 does not need to be changed, and only the position of the source wire 210 needs to be changed; in the present embodiment, by changing the source lead 210, when the source 230 and the drain 240 patterns are etched, more developing energy can be obtained near the first source branch 232, so that the corresponding barrier layer pattern is completely etched, and the channel between the first source branch 232 and the first drain branch 242 is completely etched in the subsequent etching process. And even if the end of the source lead 210 is not etched clean when the source lead 210 is etched such that the end of the source lead 210 protrudes from the first source branch 232, the end of the source lead 210 does not intersect the drain electrode 240 since the extension line of the source lead 210 does not overlap the drain electrode 240; therefore, the source 230 and the drain 240 are not shorted when the etching is not uniform, which is beneficial to improving the production yield of the product.
Of course, as shown in fig. 12, an extension portion 250 may be disposed at an end of the second source branch 233 facing the drain 240, the source lead 210 is vertically connected to the extension portion 250, and the specific design of the extension portion 250 refers to the extension portion 250 connected to the first source branch 232, which is not described herein again; or two source leads 210 are disposed in the driving circuit 200, at this time, the first source branch 232 and the second source branch 233 are both provided with the extension portion 250, and the two source leads 210 are respectively connected to the first source branch 232 or the second source branch 233, which is specifically designed according to the use situation.
Moreover, the present embodiment is also applicable to other types of thin film transistors 220, including the thin film transistor 220 having three source branches 231 in fig. 9 and the thin film transistor 220 having more than three source branches 231 in fig. 10, but the extension portion 250 is only connected to the first source branch 232 and/or the second source branch 233 at two ends of the source 230, and the details are shown in fig. 11 and are not described herein for too much.
As shown in fig. 13, another driving circuit 200 is disclosed, which is different from the previous embodiment in that the extension portion 250 is connected to the other end of the first source branch 232 and/or the second source branch 233, i.e. the extension portion 250 is an extension portion of the drain branch 241 towards the handle portion of the drain 240; one end of the extension portion 250 is connected to the first source branch 232, the other end is vertically connected to an extension line of the source trunk 235, and the source lead 210 coincides with the extension line of the source trunk 235. Specifically, since the source 230 is U-shaped, the connection between the first source branch 232 and the source stem 235 is not a right angle, in this embodiment, the first source branch 232 and the source stem 235 extend together until intersecting, a portion between the intersection and the first source branch 232 is an extension 250, a portion between the intersection and the source stem 235 is a portion of the source lead 210, and the source lead 210 is perpendicular to the extension 250 and passes through the extension 250 to coincide with the source stem 235.
In this embodiment, the source lead 210 is extended along the source trunk 235, and the source lead 210 is connected to the first source branch 232 and the source trunk 235, so as to improve the charging effect of the source lead 210 on the thin film transistor 220; in addition, even if the end of the source lead 210 is not etched clean when the source lead 210 is etched, so that the end of the source lead 210 protrudes from the extension 250, the end only protrudes into the source stem 235 and is not connected to the drain 240, and thus the source 230 and the drain 240 are not shorted.
As for the type of the tft 220 in the present embodiment, the connection manner between the source lead 210 and the extension portion 250 in the other source branch 231 may also be combined with the above-mentioned embodiments, and details thereof are not repeated herein.
As shown in fig. 14, which is a schematic diagram of a display panel, as another embodiment of the present application, a display panel 400 is further disclosed, where the display panel 400 includes the array substrate 100 shown in fig. 1, a color filter substrate 500 disposed opposite to the array substrate 100, and a liquid crystal layer 600 disposed between the array substrate 100 and the color filter substrate 500, and a non-display region of the array substrate 100 includes the driving circuit 200. In addition, the thin film transistor 220 in the present application is not only suitable for the row driving circuit of the array substrate in the non-display area, but also suitable for the active switch in the display area of the array substrate 100.
The technical solution of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels may be used, and the above solution can be applied.
It should be noted that the inventive concept of the present application can form many embodiments, but the present application has a limited space and cannot be listed one by one, so that, on the premise of no conflict, any combination between the above-described embodiments or technical features can form a new embodiment, and after the embodiments or technical features are combined, the original technical effect will be enhanced.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (10)
1. A control switch of a driving circuit, the control switch comprising a thin film transistor, the driving circuit further comprising a source lead connected to the thin film transistor, the thin film transistor comprising:
the source electrode comprises at least two source electrode branches arranged in parallel and a source electrode trunk connected with each source electrode branch; and
the drain electrode is arranged on the same layer as the source electrode and comprises at least one drain electrode branch and a drain electrode trunk connected with each drain electrode branch, and the drain electrode branches and the source electrode branches are arranged in parallel and alternately to form a channel; and
the grid electrode is arranged corresponding to the source electrode and the drain electrode;
wherein the source lead is connected with the source, and an extension line of the source lead does not overlap with the drain branch.
2. The control switch of the driving circuit according to claim 1, wherein the source lead is disposed on a side of the source stem away from the source branch, and connected to the source stem, and an extension line of the source lead is parallel to the drain branch.
3. The control switch of the driving circuit according to claim 2, wherein the source branches connected to both ends of the source trunk are a first source branch and a second source branch, and at least one of the source leads is disposed corresponding to at least one of the first source branch and the second source branch.
4. The control switch of the driving circuit according to claim 2, wherein the source branches are a first source branch and a second source branch connected to two ends of the source trunk, and a third source branch connected to a region between two ends of the source trunk, the third source branch being disposed in parallel between the first source branch and the second source branch;
the source electrode lead is provided with at least one and is arranged corresponding to at least one of the first source electrode branch, the second source electrode branch and the third source electrode branch.
5. The control switch of the driving circuit according to any one of claims 2 to 4, wherein the width of the source lead is smaller than the spacing between two adjacent drain branches.
6. The control switch of the driving circuit according to claim 1, wherein the source branches include a first source branch and a second source branch connected to two ends of the source trunk;
the thin film transistor further comprises an extension part, the extension part is connected with the source electrode lead, and the extension part is connected with the end part, far away from the source electrode trunk, of the first source electrode branch and/or the second source electrode branch;
in a first direction, the first source branch and/or the second source branch connected with the extension portion protrude from other source branches, and an end portion of the source lead connected with the extension portion protrudes from a side edge of the drain trunk far away from the source;
wherein the first direction is an extending direction of the source branch.
7. The control switch of the driving circuit according to claim 6, wherein a region of the source branches connected to the two ends of the source trunk is a third source branch, and the third source branch is disposed between the first source branch and the second source branch in parallel;
in the drain electrode branches, a first drain electrode branch and a second drain electrode branch are connected with two ends of the drain electrode main body, a third drain electrode branch is connected with an area between two ends of the drain electrode main body, and the third drain electrode branches are arranged between the first drain electrode branch and the second drain electrode branch in parallel;
the first drain electrode branches are arranged between two adjacent first source electrode branches and the third source electrode branches in parallel, the second drain electrode branches are arranged between two adjacent second source electrode branches and the third source electrode branches in parallel, and the third drain electrode branches are arranged between two adjacent third source electrode branches in parallel;
the number of the third drain branches is one less than the number of the third source branches.
8. The control switch of the driving circuit according to claim 1, wherein the driving circuit comprises a frame start signal line, a gate voltage control line, a clock signal line, and a plurality of GOA cells, an input terminal of each of the GOA cells is connected to the frame start signal line, the gate voltage control line, the clock signal line, and an output terminal of the GOA cell is connected to a scan line, driving the scan line;
the GOA unit comprises a first thin film transistor, a second thin film transistor, a third thin film transistor and a fourth thin film transistor, wherein a source electrode of the first thin film transistor is respectively connected with the gate voltage control line and a source electrode of the second thin film transistor through two source electrode leads, a drain electrode of the first thin film transistor is respectively communicated with a source electrode of the third thin film transistor and a gate electrode of the fourth thin film transistor, and a gate electrode of the first thin film transistor is connected with a gate electrode of the second thin film transistor;
the drain electrode of the second thin film transistor is connected with the source electrode of the fourth thin film transistor, and the grid electrode of the second thin film transistor is connected with the grid electrode of the fourth thin film transistor;
the drain of the third thin film transistor is communicated with the frame start signal line, and the drain of the fourth thin film transistor is communicated with the clock signal line.
9. An array substrate comprising the driving circuit according to any one of claims 1 to 8, and scanning lines driven by the driving circuit.
10. A display panel comprising the array substrate of claim 9, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.
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