CN1129174C - Method for manufacturing bipolar transistor capable of supressing deterioration of transistor characteristics - Google Patents
Method for manufacturing bipolar transistor capable of supressing deterioration of transistor characteristics Download PDFInfo
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- CN1129174C CN1129174C CN99103424A CN99103424A CN1129174C CN 1129174 C CN1129174 C CN 1129174C CN 99103424 A CN99103424 A CN 99103424A CN 99103424 A CN99103424 A CN 99103424A CN 1129174 C CN1129174 C CN 1129174C
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- polysilicon layer
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- semiconductor substrate
- insulating barrier
- bipolar transistor
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 230000006866 deterioration Effects 0.000 title 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 94
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims description 86
- 230000007797 corrosion Effects 0.000 claims description 23
- 238000005260 corrosion Methods 0.000 claims description 23
- 230000004888 barrier function Effects 0.000 claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 230000003628 erosive effect Effects 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims 2
- 238000003475 lamination Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 238000001039 wet etching Methods 0.000 abstract 1
- 229910052796 boron Inorganic materials 0.000 description 16
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 4
- -1 boron ion Chemical class 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000007850 degeneration Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000012010 growth Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
Abstract
In a method for manufacturing a bipolar transistor, a first insulating layer (2), a first polycrystalline silicon layer (3), and a second insulating layer (4) are sequentially formed on a semiconductor substrate (1). Then, the second insulating layer and the first polycrystalline silicon layer are patterned to form an opening therein. Then, the first insulating layer is over etched by using the second insulating layer and the first polycrystalline silicon layer as a mask. Then, a second polycrystalline silicon layer is formed on the entire surface. Then, an oxidizing process is performed upon the second polycrystalline silicon layer except for a part of the second polycrystalline silicon layer under the first polycrystalline silicon layer, and the oxidized part of the second polycrystalline silicon layer is removed by a wet etching process. Then, impurities of the second conductivity type are implanted into the semiconductor substrate to form a base region.
Description
The present invention relates to be used to make the method for bipolar transistor.
In first art methods that is used for making bipolar transistor, first polysilicon layer of first insulating barrier, second conductivity type and second insulating barrier are formed on the first conductive-type semiconductor substrate successively.Second insulating barrier and first polysilicon layer are patterned to form opening therein then.Then, use second insulating barrier and first polysilicon layer to make mask, excessive erosion (over etched) first insulating barrier.On whole surface, form second polysilicon layer again.With second polysilicon layer part second polysilicon layer of isotropic etch technology corrosion below first polysilicon layer.Second conductive-type impurity is injected in the Semiconductor substrate to form the base.On the sidewall of first and second polysilicon layers, form side wall insulating layer.On the base, form the 3rd polysilicon layer of first conductivity type then.Carry out annealing operation at last.The impurity of second conductivity type is diffused into the Semiconductor substrate through second polysilicon layer from first polysilicon layer and engages (graft) base to form as a result, and first conductive-type impurity is diffused into the base to form the emitter region from the 3rd polysilicon layer.This will explain in the back in detail.
But in above-mentioned first art methods, because Semiconductor substrate also is to be corroded in the isotropic etch technology that is used for corroding second polysilicon layer, characteristics of transistor is degenerated.For example, may produce leakage current, and the joint base can not be electrically connected with the basic unit that increases base resistance.
In second art methods that is used for making bipolar transistor, second polysilicon layer of first art methods is oxidized, and its oxidized part is removed (referring to JP-A-62-169364) with dry corrosion process.
But in above-mentioned second art methods,,, transistor characteristic degenerates so being still because Semiconductor substrate is used to remove the dry corrosion process damage of the oxidized portion of second polysilicon layer.
The objective of the invention is to suppress the degeneration of the characteristic of bipolar transistor.
According to purpose of the present invention, in the method that is used for making bipolar transistor, first polysilicon layer of first insulating barrier, second conductivity type and second insulating barrier are formed on the first conductive-type semiconductor substrate successively; Second insulating barrier and first polysilicon layer are patterned to form opening therein then; Then, use second insulating barrier and first polysilicon layer to do mask excessive erosion (over etched) first insulating barrier; On whole surface, form second polysilicon layer again; Second polysilicon layer except second polysilicon layer of the first polysilicon layer lower part is carried out oxidation technology, and remove the oxidized portion of second polysilicon layer with wet corrosion technique; The impurity of second conductivity type is injected in the Semiconductor substrate to form the base then; On the sidewall of first and second polysilicon layers, form side wall insulating layer; On the base, form the 3rd polysilicon layer of first conductivity type; Impurity with first conductivity type is injected in the 3rd polysilicon layer then; Carry out annealing operation at last; As a result, the impurity of second conductivity type is diffused into the Semiconductor substrate through second polysilicon layer from first polysilicon layer and engages the base to form, and the impurity of first conductivity type is diffused into the base to form the emitter region from the 3rd polysilicon layer; Like this, because Semiconductor substrate almost can not be corroded at the wet corrosion technique that is used to corrode second polysilicon layer,, transistor characteristic do not descend so almost.
By being compared with the prior art explanation with reference to the accompanying drawings, the easier quilt of the present invention is understood, wherein:
Figure 1A is the profile of explaining the art methods be used to make bipolar transistor to 1K; With
Fig. 2 A-2L is the profile of embodiment of explaining the method for bipolar transistor constructed in accordance.
Before introducing most preferred embodiment of the present invention, at first explain the art methods that is used to make bipolar transistor with reference to Figure 1A-1K.
At first, with reference to Figure 1A, N type single crystalline substrate 1 is implemented oxidation technology to form silicon oxide layer 2.The polysilicon layer 3 of doped with boron is deposited on the silicon oxide layer 2.Silicon nitride layer 4 is deposited on the polysilicon layer 3 of doped with boron then.
Then, use photoetching process on silicon nitride layer 4, to form photoresist graph layer 5 with reference to Figure 1B.Graph layer 5 is made mask with photoresist then, with the polysilicon layer 3 of dry corrosion process corroding silicon nitride layer 4 and doped with boron.Like this, form openings in polysilicon layer 2 inside of silicon nitride layer 4 and doped with boron.Remove photoresist graph layer 5 then.
Refer again to Fig. 1 C, make mask, with wet corrosion technique side corrosion oxidation silicon layer 2 with the polysilicon layer 3 of silicon nitride layer 4 and doped with boron.
With reference to Fig. 1 D, un-doped polysilicon layer 6 is deposited on the whole surface.
With reference to Fig. 1 E, unadulterated polysilicon layer 6 is corroded with isotropic etch technology.As a result, only on the sidewall of silicon oxide layer 2, stay unadulterated polysilicon layer 6.In this case, approximately the thick monocrystalline substrate 1 of 300-2000 also is corroded.
With reference to Fig. 1 F, use silicon nitride layer 4 to make mask, the boron ion is injected in the monocrystalline substrate 1.As a result, in the monocrystalline substrate 1 inner P type basic unit 7 that forms.
With reference to Fig. 1 G, silicon oxide layer 8 and silicon nitride layer 9 are deposited on the whole surface successively.
With reference to Fig. 1 H,, use wet corrosion technique corrosion oxidation silicon layer 8 afterwards with dry corrosion process corroding silicon nitride layer 9.As a result, form side wall insulating layer with silicon oxide layer 8 and silicon nitride layer 9.
With reference to Fig. 1 I, polysilicon layer 10 is deposited on the whole surface, and then, arsenic ion is injected in the polysilicon layer 10.Use photoetching and etching process composition polysilicon layer 10 then.The result forms the polysilicon layer 10 of arsenic doped.
With reference to Fig. 1 J, carry out annealing operation then, the result, the boron ion is diffused into monocrystalline substrate 1 from the polysilicon layer 3 of doped with boron through unadulterated polysilicon layer 6, engages base 11 in the monocrystalline substrate 1 inner P+ of formation type thus.Simultaneously, arsenic ion is diffused into P type basic unit 7 from the polysilicon layer 10 of arsenic doped, thereby in the P type basic unit 7 inner N type emitter regions 12 that form.
At last, with reference to Fig. 1 K, form emitter 13E and base stage 13B.Notice that base stage 13B is connected to through polysilicon layer 3 and 6 and engages base 11.So just finished the NPN transistor that has as the monocrystalline substrate 1 of the collector electrode that is connected with the collector electrode (not shown).
But in the method shown in Figure 1A-1K, because monocrystalline substrate 1 is also in the isotropic etch process quilt corrosion that is used to corrode unadulterated polysilicon layer 6, so transistor characteristic descends.For example, leakage current may increase, and P+ type joint base 11 can not be electrically connected with the P type basic unit 7 that increases base resistance.
Below with reference to the embodiment of Fig. 2 A-2K introduction according to the method for manufacturing bipolar transistor of the present invention.
At first with reference to Fig. 2 A, use the mode same with Figure 1A, n type single crystal silicon substrate 1 is carried out oxidation technology to form the thick silicon oxide layer 2 of 200-1000 , the polysilicon layer 3 of the doped with boron that about then 1000-3000 is thick is deposited on the silicon oxide layer 2.The silicon nitride layer 4 that 500-3000 is thick then is deposited on the polysilicon layer 3 of doped with boron.
With reference to Fig. 2 B,, use photoetching process on silicon nitride layer 4, to form the thick photoresist graph layer 5 of about 1 μ m in the mode same with Figure 1B.Graph layer 5 is made mask with photoresist, with the polysilicon layer 3 of dry corrosion process corroding silicon nitride layer 4 and doped with boron.Thereby the polysilicon layer 2 inner openings that form in silicon nitride layer 4 and doped with boron.Remove photoresist graph layer 5 then.
With reference to Fig. 2 C, in the mode same, make mask, with the thick silicon oxide layer 2 of the wet corrosion technique side about 1000-3000 of corrosion with the polysilicon layer 3 of silicon nitride layer 4 and doped with boron with Fig. 1 C.
With reference to Fig. 2 D, in the mode same with Fig. 1 D, the thick unadulterated polysilicon layer 6 of the about 200-1000 of deposit on whole surface.
With reference to Fig. 2 E, carry out oxidation technology, the result, the expose portion of unadulterated polysilicon layer 6 is transformed into silicon oxide layer 6a.
With reference to Fig. 2 F, use hydrogen fluoride wet corrosion technique corrosion oxidation silicon layer 6a.As a result, only on the sidewall of silicon oxide layer 2, stay unadulterated polysilicon layer 6.Notice that monocrystalline substrate 1 is corroded hardly in this case.
With reference to Fig. 2 G, in the mode same, make mask with silicon nitride layer 4 with Fig. 1 F, the boron ion is injected in the monocrystalline substrate 1.The result is in the monocrystalline substrate 1 inner P type basic unit 7 that forms.
With reference to Fig. 2 H, in the mode same with Fig. 1 G, silicon oxide layer 8 and the thick silicon nitride layer 9 of about 500-3000 that about 200-1000 is thick are deposited on the whole surface successively.
With reference to Fig. 2 I, in the mode same with Fig. 1 H, with dry corrosion process deep etch silicon nitride layer 9, afterwards, with wet corrosion technique corrosion oxidation silicon layer 8.As a result, form side wall insulating layer with silicon oxide layer 8 and silicon nitride layer 9.
With reference to Fig. 2 J, in the mode same with Fig. 1 I, the polysilicon layer 10 that about 1000-3000 is thick is deposited on the whole surface, and arsenic ion is injected in the polysilicon layer 10 then.Use photoetching and etching process composition polysilicon layer 10 again.The result forms the polysilicon layer 10 of arsenic doped.
With reference to Fig. 2 K,, carry out annealing operation at about 700 to 1200 ℃ in the mode same with Fig. 1 J.The boron ion is diffused into monocrystalline substrate 1 from the polysilicon layer 3 of doped with boron through unadulterated polysilicon layer 6 as a result, engages base 11 in the monocrystalline substrate 1 inner P+ of formation type thus.Simultaneously, arsenic ion is diffused into P type basic unit 7 from the polysilicon layer 10 of arsenic doped, thus the 7 inner N type emitter regions 12 that form in P type base.
At last, with reference to Fig. 2 L,, form emitter 13E and base stage 13B in the mode same with Fig. 1 K.Notice that base stage 13B is connected to joint base 11 through polysilicon layer 3 and 6.Like this, just finished the NPN transistor that has as the monocrystalline substrate 1 of the collector electrode that is connected with the collector electrode (not shown).
In the method shown in Fig. 2 A-2L, because monocrystalline substrate 1 is corroded hardly at the wet corrosion technique that is used for corroding unadulterated polysilicon layer 6, so can suppress leakage current, and the P+ type engages the P type basic unit 7 that base 11 can be connected to the increase of inhibition base resistance reliably.
In the above-described embodiments, can in polysilicon layer 3 and 10 growths, foreign ion be incorporated into wherein, or ion injects after growth.
And, owing to remove unadulterated polysilicon layer 6 with oxidation technology and wet corrosion technique, rather than be used for the method etching process, so manufacturing cost can reduce.
Notice that the present invention is applicable to that also collector electrode buries the stratotype bipolar transistor, (pull-out) collector electrode of wherein pulling out is formed on the front surface of monocrystalline substrate.In addition, the present invention also is applicable to the method for making PNP transistor.
As mentioned above, according to the present invention, owing to Semiconductor substrate is corroded in the removal technology of unadulterated polysilicon layer hardly, so can suppress the degeneration of transistor characteristic.
Claims (6)
1. make the method for bipolar transistor, may further comprise the steps:
Semiconductor substrate (1) at first conductivity type goes up formation first insulating barrier (2);
On described first insulating barrier, form first polysilicon layer (3) of second conductivity type;
On described first polysilicon layer, form second insulating barrier (4);
Described second insulating barrier of composition and described first polysilicon layer are to form opening at described second insulating barrier and described first polysilicon layer inside;
After forming described opening, make mask with described second insulating barrier and described first polysilicon layer, described first insulating barrier of excessive erosion;
After described first insulating barrier of excessive erosion, on the whole surface of the exposure of described Semiconductor substrate, described first and second insulating barriers and described first polysilicon layer, form second polysilicon layer (6);
Described second polysilicon layer described second polysilicon layer part below described first polysilicon layer is carried out oxidation technology;
Remove the oxidized portion of described second polysilicon layer with wet corrosion technique;
After the oxidized portion of removing described second polysilicon layer, the impurity that injects described second conductivity type in described Semiconductor substrate forms the base with the inside in described Semiconductor substrate;
Form after the described base, on the sidewall of described first and second polysilicon layers, form side wall insulating layer (8,9);
After forming described side wall insulating layer, on the described base of described Semiconductor substrate, form the 3rd polysilicon layer (10) of described first conductivity type;
In described the 3rd polysilicon layer, inject the impurity of described first conductivity type; And
Carry out annealing process, thereby the impurity of described second conductivity type is diffused into the described Semiconductor substrate through described second polysilicon layer from described first polysilicon layer, thereby engage base (11) inner formation of described Semiconductor substrate, and the impurity of described first conductivity type is diffused into the described base of described Semiconductor substrate from described the 3rd polysilicon layer, thereby in inner formation emitter region (12), described base.
2. the method for manufacturing bipolar transistor according to claim 1, wherein said second polysilicon layer is unadulterated.
3. the method for manufacturing bipolar transistor according to claim 1, wherein said Semiconductor substrate is to be made by monocrystalline silicon.
4. the method for manufacturing bipolar transistor according to claim 1, wherein said first insulating barrier is to be made by silica.
5. the method for manufacturing bipolar transistor according to claim 1, wherein said second insulating barrier is to be made by silicon nitride.
6. the method for manufacturing bipolar transistor according to claim 1, wherein said side wall insulating layer comprises the lamination of silica and silicon nitride.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10084713A JP3005517B2 (en) | 1998-03-30 | 1998-03-30 | Method for manufacturing semiconductor device |
| JP084713/98 | 1998-03-30 | ||
| JP084713/1998 | 1998-03-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1230771A CN1230771A (en) | 1999-10-06 |
| CN1129174C true CN1129174C (en) | 2003-11-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99103424A Expired - Fee Related CN1129174C (en) | 1998-03-30 | 1999-03-30 | Method for manufacturing bipolar transistor capable of supressing deterioration of transistor characteristics |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6124181A (en) |
| EP (1) | EP0948040B1 (en) |
| JP (1) | JP3005517B2 (en) |
| KR (1) | KR100301531B1 (en) |
| CN (1) | CN1129174C (en) |
| DE (1) | DE69901752T2 (en) |
| TW (1) | TW417275B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1082758A2 (en) * | 1998-11-13 | 2001-03-14 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device comprising a bipolar transistor |
| EP1630863B1 (en) | 2004-08-31 | 2014-05-14 | Infineon Technologies AG | Method of fabricating a monolithically integrated vertical semiconducting device in an soi substrate |
| US7300850B2 (en) * | 2005-09-30 | 2007-11-27 | Semiconductor Components Industries, L.L.C. | Method of forming a self-aligned transistor |
| DE102007010563A1 (en) * | 2007-02-22 | 2008-08-28 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | Selective growth of polycrystalline silicon-containing semiconductor material on a silicon-containing semiconductor surface |
| JP5239254B2 (en) * | 2007-08-22 | 2013-07-17 | サンケン電気株式会社 | Method for manufacturing insulated gate type semiconductor device |
| CN105097506B (en) * | 2014-04-29 | 2018-11-27 | 无锡华润上华科技有限公司 | The manufacturing method of polysilicon emitter vertical NPN transistor |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62169364A (en) * | 1985-07-31 | 1987-07-25 | Hitachi Denshi Ltd | Manufacture of semiconductor device |
| JPH04122029A (en) * | 1990-09-13 | 1992-04-22 | Nec Corp | Manufacture of semiconductor device |
| JPH04192335A (en) * | 1990-11-24 | 1992-07-10 | Nec Corp | Manufacture of semiconductor device |
| JPH0669217A (en) * | 1992-08-20 | 1994-03-11 | Fujitsu Ltd | Production of semiconductor device |
| JPH06168951A (en) * | 1992-12-01 | 1994-06-14 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH06275633A (en) * | 1993-03-22 | 1994-09-30 | Miyazaki Oki Electric Co Ltd | Bipolar semiconductor device and its manufacture |
| JPH0766214A (en) * | 1993-08-26 | 1995-03-10 | Oki Electric Ind Co Ltd | Manufacture of bi-polar semiconductor integrated circuit device |
| JP2720793B2 (en) * | 1994-05-12 | 1998-03-04 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| US5523244A (en) * | 1994-12-19 | 1996-06-04 | Hughes Aircraft Company | Transistor fabrication method using dielectric protection layers to eliminate emitter defects |
| JP2746225B2 (en) * | 1995-10-16 | 1998-05-06 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
-
1998
- 1998-03-30 JP JP10084713A patent/JP3005517B2/en not_active Expired - Fee Related
-
1999
- 1999-03-29 TW TW088105054A patent/TW417275B/en not_active IP Right Cessation
- 1999-03-29 KR KR1019990010768A patent/KR100301531B1/en not_active IP Right Cessation
- 1999-03-30 CN CN99103424A patent/CN1129174C/en not_active Expired - Fee Related
- 1999-03-30 US US09/281,286 patent/US6124181A/en not_active Expired - Fee Related
- 1999-03-30 DE DE69901752T patent/DE69901752T2/en not_active Expired - Fee Related
- 1999-03-30 EP EP99106474A patent/EP0948040B1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990078358A (en) | 1999-10-25 |
| DE69901752D1 (en) | 2002-07-18 |
| JPH11283991A (en) | 1999-10-15 |
| DE69901752T2 (en) | 2003-02-06 |
| US6124181A (en) | 2000-09-26 |
| TW417275B (en) | 2001-01-01 |
| EP0948040A1 (en) | 1999-10-06 |
| JP3005517B2 (en) | 2000-01-31 |
| EP0948040B1 (en) | 2002-06-12 |
| CN1230771A (en) | 1999-10-06 |
| KR100301531B1 (en) | 2001-10-29 |
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