CN112910565A - PAM4 signal receiving and demodulating circuit applied to high-speed optical interconnection - Google Patents
PAM4 signal receiving and demodulating circuit applied to high-speed optical interconnection Download PDFInfo
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- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
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Abstract
The invention discloses a receiving and demodulating circuit of a four-order pulse modulation (PAM4) signal applied to high-speed optical interconnection, which comprises: the trans-impedance amplifier is used for converting an input PAM4 current signal into a PAM4 voltage signal, amplifying the PAM4 voltage signal, balancing high-frequency attenuation of the PAM4 voltage signal and eliminating intersymbol interference; a level shifter for shifting the three eyes of the PAM4 voltage signal eye to a zero level, respectively; the limiting amplifier is used for separating the upper eye, the middle eye and the lower eye of the PAM4 voltage signal eye diagram and converting the PAM4 voltage signal eye diagram into three thermometer codes from a four-order pulse modulation (PAM4) code; the retimer is used for retiming the three thermometer codes, eliminating the delay of the three signals and synchronously inputting the three signals into the decoding circuit; and the decoder is used for realizing exclusive-OR logic of the three paths of input thermometer codes, decoding one path of high-order NRZ signals, and directly outputting the other path of low-order NRZ signals through the sampled middle eye signals.
Description
Technical Field
The invention relates to the technical field of high-speed optical interconnection, in particular to a PAM4 signal receiving and demodulating circuit applied to high-speed optical interconnection.
Background
The popularity of electronic devices, high-quality video streams, automotive electronics, and the internet of things has led to an explosive growth in global data traffic. In the field of optical interconnection, as the demand of the underlying transmission capacity is getting larger and larger, and limited by the aspects of power consumption and system complexity, the traditional multiplexing technology gradually reaches the limit in the aspect of ultra-high speed transmission of >25 Gb/s. Therefore, the next generation optical transceiver must develop a new approach to improve the data throughput.
Addressing the above difficulties, introducing a form of modulation of the fourth order pulse modulation (PAM4) is an effective approach because it can alleviate bandwidth limitations by lowering the operating frequency of the optoelectronic devices and electronic circuits. The PAM4 signal uses 4 consecutive binary coded (00, 01, 11, 10) representation of the level amplitude for information transmission. Compared with a conventional non-return-to-zero (NRZ) code signal, each amplitude of the PAM4 signal contains two bits of information, so the data transmission rate of the PAM4 signal is increased by one time under the same bandwidth, that is, the bandwidth efficiency of the PAM4 is twice that of the NRZ. The channel loss of the PAM4 signal is also greatly reduced due to the increased bandwidth efficiency. However, PAM4 modulation to increase the data bit rate by increasing the number of pulse amplitude modulation levels comes at the expense of noise sensitivity. Compared with the NRZ signal, the PAM4 signal has three eyes and four levels in one period, and the opening degree of each eye is only one third of that of the NRZ signal. Under the same error rate condition, the signal-to-noise ratio required for transmitting the PAM4 signal is three times that of the NRZ signal, so that higher requirements are put on the design of a PAM4 signal demodulation circuit in terms of linearity and noise. In view of the advantages of the PAM4 signal in high-speed data transmission and the challenges of circuit design, it is of great significance to deeply research the receiving and demodulating circuit of the PAM4 signal.
The PAM4 receiving demodulation circuit design is greatly different from the traditional optical receiver front-end circuit. Because the PAM4 signal has 4 levels, it needs to be restored into two parallel NRZ codes in the circuit design. This requires that, in addition to the transimpedance amplifier module and the limiting amplifier module which are widely used in the conventional optical receiver circuit, a decision circuit module is introduced to identify 4 levels, a sampling circuit module eliminates the delay caused by the preceding stage circuit, and a decoding circuit module realizes decoding. These high speed demodulation circuit modules clearly present challenges to the design of PAM4 receive demodulation circuits.
Since PAM4 modulation is widely considered as the most suitable implementation for ultra-high speed optical interconnection systems, transceiver circuits for PAM4 signals have become the focus of domestic and foreign research. In the year 2015, the number of the main raw materials,the American Bell laboratory develops a 112Gb/s PAM4 optical transceiver based on a 0.18 mu m SiGe BiCMOS process, and successfully realizes transmission on 2km standard single-mode fiber[1]However, the rear-end demodulation module adopts an analog-to-digital converter for processing, so that the complexity and the power consumption of the system are increased; in 2018, Inphi corporation designed a dual-channel 2 x 64Gb/s PAM4 transimpedance amplifier based on 0.13 μm SiGe BiCMOS process[2]The noise is reduced significantly, but only a solution of a front-end circuit of the receiver is provided, and the whole design of the receiver is not carried out. In addition, IHP company designs two 100Gb/s fully differential linear trans-impedance amplifiers based on 0.13 μm SiGe BiCMOS process, and realizes a transmission rate of 50GBaud under the PAM4 modulation technology[3]. At present, the research on PAM4 receiving and demodulating circuits at home and abroad is mostly concentrated on the aspect of simulating front-end circuits of optical receivers, the receiving and demodulating whole circuits are still in module-level design, the circuit design complexity is high, the power consumption is large, and the practical application value is not high.
Reference documents:
[1]Shahramian S,Lee J,Weiner J,et al.A 112Gb/s 4-PAM transceiver chipset in 0.18μm SiGe BiCMOS technology for optical communication systems[C].IEEE Compound Semi Int Circuit Symposium(CSICS),New Orleans,LA,USA:IEEE 2015:1-4.
[2]Awny A,Nagulapalli R,Kroh M,et al.A Linear Differential Transimpedance Amplifier for100-Gb/s Integrated Coherent Optical Fiber Receivers[J].IEEE Transactions on Microwave Theory and Techniques,2018:1-14.
[3]Lopez I G,Awny A,Rito P,et al.100Gb/s Differential Linear TIAs With Less Than 10pA/√Hz in 130-nm SiGe:C BiCMOS[J].IEEE Journal of Solid State Circuits,2018,PP(99):1-12.
disclosure of Invention
In order to solve the problems that an NRZ optical receiving end circuit is complex in design, the system energy efficiency is improved, and the chip cost is reduced, the invention provides a PAM4 signal receiving demodulation circuit applied to high-speed optical interconnection, and provides a novel analog circuit design scheme with high linearity, so that the design complexity is simplified, the system power consumption is reduced, and the design of a single-path 50Gb/s PAM4 receiving demodulation whole circuit is realized, which is described in detail in the following:
a receive demodulation circuit for a fourth order pulse modulated signal for use in a high speed optical interconnect, the circuit comprising:
the trans-impedance amplifier is used for converting an input PAM4 current signal into a PAM4 voltage signal, amplifying the PAM4 voltage signal, balancing high-frequency attenuation of the PAM4 voltage signal and eliminating intersymbol interference;
a level shifter for shifting the three eyes of the PAM4 voltage signal eye to a zero level, respectively;
the limiting amplifier is used for separating the upper eye, the middle eye and the lower eye of the PAM4 voltage signal eye diagram and converting the PAM4 voltage signal eye diagram into three thermometer codes from a four-order pulse modulation (PAM4) code;
the retimer is used for retiming the three thermometer codes, eliminating the delay of the three signals and synchronously inputting the three signals into the decoding circuit;
and the decoder is used for realizing exclusive-OR logic of the three paths of input thermometer codes, decoding one path of high-order NRZ signals, and directly outputting the other path of low-order NRZ signals through the sampled middle eye signals.
Wherein the transimpedance amplifier adopts a fully differential structure and consists of a common emitter amplifier and an emitter follower,
the common emitter amplifier is a main amplifier, the emitter follower is used for level shift and impedance feedback, the base input photoelectric current of the common emitter amplifier is shunted and fed back in parallel through a feedback resistor RfTo the emitter of an emitter follower cascode, the output signal of which is fed to a transistor Q1The collector electrode of (1).
Furthermore, the limiting amplifier adopts three stages of Cherry-Hooper basic structure unit cascade connection, different feedback values are set between each stage, and conjugate poles of the circuit are staggered.
Wherein the retimer is comprised of a two-stage latch.
Furthermore, each input of the decoder drives a pair of differential pairs separately, and the current of the other path is half of the current of the differential pairs so as to balance the DC level of the output signal and enable the output signal to be outputThe swing of the output signal is kept as IssR；IssIs tail current, R is load resistance;
one of the two paths of output is a two-level signal, the other path is a three-level signal, and a differential output result is realized by the difference of the two paths of output levels.
The technical scheme provided by the invention has the beneficial effects that:
1. the invention adopts PAM4 modulation mode, under the condition of the same bandwidth, the transmission rate is twice of that of the traditional NRZ modulation, and a new scheme is provided for designing a high-speed receiving circuit;
2. the invention realizes the demodulation of the high-speed PAM4 signal in the analog domain, and avoids introducing an analog-to-digital converter and a demultiplexer module with complex structure and high power consumption, thereby simplifying the system architecture and reducing the system power consumption;
3. according to the thermometer code characteristic, the invention uses the two-stage MOS tube structure to realize the high-speed decoder, thereby simplifying the design difficulty of the traditional decoder. Compared with the traditional analog circuit decoder, the sequential logic problem caused by path difference is avoided.
In summary, the PAM4 signal receiving and demodulating circuit applied to high-speed optical interconnection provided by the invention has the advantages of simple structure, low power consumption, easy design and implementation, and the like, and is expected to be widely applied.
Drawings
Fig. 1 is an overall architecture diagram of a receiving demodulation circuit of a PAM4 signal;
FIG. 2 is a circuit diagram of a transimpedance amplifier;
fig. 3 is a circuit diagram of a limiting amplifier unit;
FIG. 4 is a retimer circuit;
FIG. 5 is a circuit diagram of a decoder;
fig. 6 is a schematic diagram of the overall simulation result of the PAM4 receiving demodulation circuit.
Wherein, (a) is high eye diagram output; (b) is output for the low eye diagram.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below.
Example 1
An embodiment of the present invention provides a PAM4 receiving and demodulating circuit applied to high-speed optical interconnection, and referring to fig. 1 to 5, the circuit includes:
a trans-impedance amplifier for receiving and amplifying PAM4 signal and providing enough bandwidth for system;
a level shifter for achieving shifting of the three eyes of the PAM4 signal eye to zero levels, respectively;
the set of limiting amplifiers is used for realizing three-eye separation of an eye pattern of the PAM4 signal and converting the eye pattern of the PAM4 signal into three thermometer codes from fourth-order pulse modulation (PAM4) codes;
a retimer, which is used to retime the three thermometer codes, eliminate the delay of the three signals, and realize the synchronous input to the decoding circuit;
and the decoder is used for restoring the input three thermometer codes into two NRZ code signals, finishing PAM4 signal decoding and realizing impedance matching in the circuit.
The overall demodulation scheme for the PAM4 signal is:
the high-speed transimpedance amplifier converts an input PAM4 current signal into a PAM4 voltage signal and amplifies the voltage amplitude which can be identified and processed by a subsequent circuit.
The level shifter carries out direct current level shifting on the PAM4 voltage signal, and four levels are identified through the limiting amplifier, so that the function of threshold judgment is realized.
Where the four levels are denoted 0,1,2,3, respectively, the three eyes, i.e. the four levels, are separated by a limiting amplifier.
And the retimer composed of high-speed latches can limit amplitude of the PAM4 voltage signal and complete retiming of the three thermometer codes. After the three thermometer codes pass through a PAM4 demodulation circuit, high-order and low-order NRZ signals can be output.
Example 2
The scheme of example 1 is further described below in conjunction with fig. 1-6, and is described in detail below:
as shown in fig. 1, the PAM4 receiving and demodulating circuit designed in the embodiment of the present invention has a transimpedance amplifier at the foremost end of the system for equalizing high-frequency attenuation of a PAM4 signal, eliminating inter-symbol interference, and providing sufficient gain for a post-stage circuit. Followed by a level shifter that shifts the center of the three eyes of the PAM4 input signal to a zero level, respectively, generating a three-way PAM4 signal. The generated PAM4 signal is processed by a limiting amplifier, and then the upper eye, the middle eye and the lower eye are separated.
Because the structures of the three level shifters are not identical, a certain delay occurs in the signal, and a retiming module is introduced to eliminate the signal delay. And the sampled three thermometer code signals are synchronously input into a decoder module to realize exclusive-or logic operation, a high-order NRZ signal is decoded, and a low-order NRZ signal is directly output by a sampled middle eye signal to finish the receiving and decoding process.
Fig. 2 is a circuit diagram of a transimpedance amplifier according to an embodiment of the present invention. The circuit topology adopts a fully differential structure from the aspects of sensitivity and bandwidth. The transimpedance amplifier is composed of a common emitter amplifier and an emitter follower, the common emitter amplifier is a main amplifier, and the emitter follower is mainly responsible for level shifting and impedance feedback. The base input photocurrent of the common emitter amplifier is fed back via shunt in parallel via a feedback resistor RfTo the emitter of an emitter follower cascode, the output signal of which is fed to a transistor Q1The collector electrode of (1). The input impedance of the circuit is reduced by the active feedback path.
Fig. 3 shows a limiting amplifier unit circuit. The circuit clips and amplifies the level-shifted signal again to extract a single eye in the eye pattern. Because the amplitude is too small to realize the effect of taking out a single eye hole, the embodiment of the invention adopts a Cherry-Hooper type structure circuit with a larger input range for design. In the Cherry-Hooper type structure, a first-stage emitter follower is introduced between two stages of common-emitter amplifiers to serve as a feedback path, so that two low-frequency poles form conjugate poles, and the influence of the capacitance effect of a cascade node on the bandwidth is relieved. In addition, the multistage cascade structure also needs to consider the static working point of a later stage circuit, so that a resistor R is introduced2To reduce the outputA level value. The whole limiting amplifier module adopts three-stage Cherry-Hooper basic structure unit cascade connection, different feedback values are set between each stage, conjugate poles of the circuit are staggered, and bandwidth deterioration caused by cascade connection is relieved.
Figure 4 is a retimer architecture. Due to the difference of the level shift circuit structures, the wiring of three signals in an actual layout is difficult to be completely matched, so that time difference exists between the three signals after amplitude limiting and amplification. Therefore, a retiming circuit module is introduced to retime the three signals, ensure that the signals are synchronously input into a later-stage decoding circuit, and reduce the error rate of the decoding circuit. The retiming circuit is formed of two stages of latches. When the clock CLK + is at a high level, the sampling tube Q1And Q2The circuit begins to sample the input signal, the latch output follows, and when the clock CLK + is low, the latch Q is turned on3And Q4And working, latching the sampling data, and keeping the output of the latch unchanged. For a single stage latch, sampling of the input signal does not achieve retiming. For example, when the input signal and the clock delay are half cycles, the ratio of the high level to the low level of the sampled output is 1:3, i.e., the single-stage latch can not output the ideal signal although the system delay is eliminated. For this purpose, a second stage latch is introduced, the two stages having the same amplitude and opposite phase of the input clock. After the signal passes through the second-stage latch with the inverted clock, the signal is restored to be a square wave signal with the high-low level ratio of 1: 1.
Fig. 5 is a circuit diagram of a decoder, and a signal synchronized by a retimer is a thermometer code inputted by three paths of differential inputs, wherein low-order data is a middle-path signal directly outputted by a limiting amplifier, and high-order data needs to be demodulated.
The decoding circuit is a three-input exclusive-OR gate. Conventional three-input xor gates are typically implemented using gilbert cells. Since the gilbert cell requires the stacking of multiple stages of MOS transistors, it is difficult to satisfy design criteria in a high-speed circuit.
The embodiment of the invention designs a decoder circuit structure as shown in fig. 5 according to the characteristics of thermometer codes. Each input drives a pair of differential pairs separately, and the current of the other path is half of that of the differential pairsTo balance the DC level of the output signal and to maintain the swing of the output signal at IssAnd R is shown in the specification. One of the two paths of outputs is a two-level signal, the other one is a three-level signal, and a differential output result is realized by the difference of the two paths of levels. And considering the nonideal characteristic of the differential waveform of the two output levels, the resistance value of the load is adjusted to about 70 omega in the circuit, so that impedance matching is realized. Because the structure does not need to stack multiple layers of transistors, the parasitic capacitance of the circuit is greatly reduced; meanwhile, the path difference of the three inputs to the output end is reduced, and the sequential logic problem caused by the path difference is effectively avoided.
Fig. 6 shows the overall simulation result of the PAM4 reception demodulation circuit. The diagram (a) is a high-order NRZ signal directly output through the decoding circuit, and the diagram (b) is a low-order NRZ signal directly output through the output buffer stage circuit after retiming. As can be seen from the figure, two paths of 25Gb/s NRZ signals can be demodulated by one path of 25GBoud PAM4 signals, the eye diagram quality is good, no obvious jitter, overshoot and undershoot exist, the cross point is clear, and the output swing amplitude is 590mV and 400mV respectively.
In conclusion, the PAM4 receiving and demodulating circuit designed by the invention can realize the receiving and demodulating of the high-speed PAM4 signal of 50 Gb/s. The invention realizes the whole circuit design of the receiving demodulation circuit in an analog domain and analyzes each functional module in detail. Compared with the traditional optical receiver and the reported PAM4 receiver, the receiving and demodulating circuit provided by the invention has the advantages of simple framework, low power consumption, easiness in design and implementation and the like, and provides a new solution for high-speed optical interconnection.
In the embodiment of the present invention, except for the specific description of the model of each device, the model of other devices is not limited, as long as the device can perform the above functions.
Those skilled in the art will appreciate that the drawings are only schematic illustrations of preferred embodiments, and the above-described embodiments of the present invention are merely provided for description and do not represent the merits of the embodiments.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (5)
1. A receiving and demodulating circuit for PAM4 signals applied to a high-speed optical interconnect, the circuit comprising:
the trans-impedance amplifier is used for converting an input PAM4 current signal into a PAM4 voltage signal, amplifying the PAM4 voltage signal, balancing high-frequency attenuation of the PAM4 voltage signal and eliminating intersymbol interference;
a level shifter for shifting the three eyes of the PAM4 voltage signal eye to a zero level, respectively;
the limiting amplifier is used for separating the upper eye, the middle eye and the lower eye of the PAM4 voltage signal eye diagram and converting the PAM4 voltage signal eye diagram into three thermometer codes from a four-order pulse modulation (PAM4) code;
the retimer is used for retiming the three thermometer codes, eliminating the delay of the three signals and synchronously inputting the three signals into the decoding circuit;
and the decoder is used for realizing exclusive-OR logic of the three paths of input thermometer codes, decoding one path of high-order NRZ signals, and directly outputting the other path of low-order NRZ signals through the sampled middle eye signals.
2. The PAM4 signal receiving and demodulating circuit applied to high-speed optical interconnection as claimed in claim 1, wherein the transimpedance amplifier adopts a fully differential structure and is composed of a common emitter amplifier and an emitter follower,
the common emitter amplifier is a main amplifier, the emitter follower is used for level shift and impedance feedback, the base input photoelectric current of the common emitter amplifier is shunted and fed back in parallel through a feedback resistor RfTo the emitter of an emitter follower cascode, the output signal of which is fed to a transistor Q1The collector electrode of (1).
3. The PAM4 signal receiving and demodulating circuit applied to high-speed optical interconnection as claimed in claim 1, wherein the limiting amplifier employs three-stage Cherry-Hooper basic structure unit cascade, each stage is set with different feedback value, and conjugate poles of the circuit are staggered.
4. The PAM4 signal receiving and demodulating circuit for high speed optical interconnect according to claim 1, wherein the retimer is formed of two-stage latches.
5. The PAM4 signal receiving and demodulating circuit applied to high-speed optical interconnection according to claim 1, wherein each input of the decoder separately drives a pair of differential pairs, and the current of the additional path is half of the current of the differential pairs to balance the DC level of the output signal and keep the swing of the output signal at IssR；IssIs tail current, R is load resistance;
one of the two paths of outputs is a two-level signal, the other one is a three-level signal, and a differential output result is realized by the difference of the two paths of levels.
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| CN114614908A (en) * | 2021-11-24 | 2022-06-10 | 杭州太明科技有限公司 | Optical receiver and trans-impedance amplifier chip thereof |
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Cited By (4)
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| CN113595949A (en) * | 2021-09-30 | 2021-11-02 | 苏州浪潮智能科技有限公司 | Self-adaptive PAM4 decision feedback equalization circuit |
| CN113595949B (en) * | 2021-09-30 | 2021-12-21 | 苏州浪潮智能科技有限公司 | Self-adaptive PAM4 decision feedback equalization circuit |
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| CN114614908A (en) * | 2021-11-24 | 2022-06-10 | 杭州太明科技有限公司 | Optical receiver and trans-impedance amplifier chip thereof |
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