CN112994798B - PAM4 transmitter driving circuit for high-speed optical interconnection - Google Patents

PAM4 transmitter driving circuit for high-speed optical interconnection Download PDF

Info

Publication number
CN112994798B
CN112994798B CN202110181511.8A CN202110181511A CN112994798B CN 112994798 B CN112994798 B CN 112994798B CN 202110181511 A CN202110181511 A CN 202110181511A CN 112994798 B CN112994798 B CN 112994798B
Authority
CN
China
Prior art keywords
pam4
bandwidth
output
signals
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110181511.8A
Other languages
Chinese (zh)
Other versions
CN112994798A (en
Inventor
谢生
薛竹君
毛陆虹
石岱泉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tianjin University
Original Assignee
Tianjin University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tianjin University filed Critical Tianjin University
Priority to CN202110181511.8A priority Critical patent/CN112994798B/en
Publication of CN112994798A publication Critical patent/CN112994798A/en
Application granted granted Critical
Publication of CN112994798B publication Critical patent/CN112994798B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters
    • H04B10/516—Details of coding or modulation
    • H04B10/5161—Combination of different modulation schemes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters
    • H04B10/516—Details of coding or modulation
    • H04B10/524—Pulse modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters
    • H04B10/516—Details of coding or modulation
    • H04B10/54—Intensity modulation
    • H04B10/541—Digital intensity or amplitude modulation

Landscapes

  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

The invention discloses a PAM4 transmitter driving circuit for high-speed optical interconnection, which comprises: four input buffer stages for providing input impedance matching; the four D triggers are used for sampling and timing the input signals and eliminating phase difference; two 2:1 multiplexers convert four paths of 25Gb/s NRZ signals into two paths of 50Gb/s NRZ signals; two broadband amplifiers, which shape the output signal of the multiplexer and increase the bandwidth; a Current Mode Logic (CML) adder, which superimposes two paths of NRZ signals into one path of PAM4 signal to realize doubling of single-path data transmission rate; the broadband output buffer stage is used for providing output impedance matching, integrating two bandwidth expansion modes and improving the bandwidth of a transmission path. The invention does not need to use passive inductor, has small chip area and is expected to be applied to the next generation of 100G/200G/400G Ethernet.

Description

PAM4 transmitter driving circuit for high-speed optical interconnection
Technical Field
The invention relates to the field of optical interconnection and high-speed optical transceiving communication systems, in particular to a PAM4 (four-level pulse amplitude modulation) transmitter driving circuit for high-speed optical interconnection.
Background
In recent years, novel technologies such as internet of things, cloud computing and intelligent sensing are developed vigorously, so that data traffic is increased explosively. In order to support such huge data traffic, a large number of data centers are required to be newly built to speed up information exchange and transmission. However, the number of data centers cannot be increased infinitely, and the fundamental solution to the problem of traffic explosion is to increase the data transmission, exchange and processing capacity per unit time. This therefore places higher demands on the transmission and switching rates within the backbone network and the data centre. Limited by 'electronic bottleneck', the traditional electrical interconnection is difficult to adapt to ultra-high-speed data transmission of more than 10Gb/s, and the optical fiber communication technology with the advantages of high bandwidth, large capacity, low loss and the like becomes the key for solving the problems. Therefore, in the face of rapidly increasing mass data, it is one of the current research hotspots to increase the transmission rate of the optical interconnection chip.
Currently, the main idea for increasing the transmission rate of an optical interconnect is to increase the number of parallel optical channels or/and to increase the amount of information carried by the transmission signal. However, the number of parallel optical channels cannot be increased infinitely, otherwise the complexity of the system is increased and the cost of the system is increased greatly. Therefore, increasing the optical-electrical bandwidth to support higher rates is one of the main research directions in optical fiber communication technology. With the release of 100G/200G/400G Ethernet optical communication standard, the transmission rate of a single channel needs to reach 50Gb/s and above[14]The traditional optical transmitter with a non-return-to-zero (NRZ) modulation format encounters great challenges in bandwidth expansion and chip cost, and introduction of complex pre-emphasis and equalization techniques for improving performance often occupies a larger area and consumes more power, so a new solution must be sought.
To achieve higher transmission rates, the industry has begun to consider using multi-level modulation to overcome this problem. Four-level pulse amplitude modulation (PAM4) uses 4 different signal levels to transmit data information, and each symbol period may represent 2 bits of logic information. Therefore, to achieve the same bit rate signal transmission capability, the PAM4 signal has a baud rate of only half that of the NRZ signal, as does the bandwidth requirement. In view of the above-mentioned advantages of PAM4, it has been increasingly studied in recent years. However, unlike the optical transmitter of the conventional NRZ modulation format, the PAM4 modulation format imposes many new requirements on the design of the transmitter, wherein how to construct the superposition modulation architecture promotes the one-way transmission rate of the PAM4 transmitter as a research hotspot.
To solve the problem, the development is carried out at home and abroadMany studies have been conducted and great progress has been made in PAM4 optical transmitters. For example, linfujiang et al designs a PAM4 transmitter of Current Mode Logic (CML), which realizes large-swing output of PAM4 signals, but the transmission rate is only 5Gb/s, and very high power consumption is consumed due to introduction of extra-large tail current[1](ii) a The Lihu et al designs a super long distance transmission module based on PAM4 technology[2]However, the PAM4 signal is generated by a formed encoder and is not integrated into a circuit. Furthermore, Soenen W et al realized a 50Gb/s PAM4 optical transmitter driving circuit in CML technology, but the gate circuit in the pre-emphasis design limits the high-speed performance[3](ii) a Rito P et al also realize 100Gb/s PAM4 optical transmitter driving circuit based on CML technology, but the inductance introduced for increasing the circuit bandwidth occupies a large chip area[4]。
At present, no domestic patent about PAM4 high-speed optical transmitter is published. In summary, there is also much research space to achieve the increase in transmission rate of PAM4 optical transmitters with limited complexity and power consumption against the background of the demand for higher rate network switching.
Reference documents:
[1] wan little wave, Linfujiang, an ultra-large-amplitude 5Gb/s PAM4 transmitter design [ J ] information technology and network security, 2019,38(02):37-40.
[2] The 50Gbit/s 40km QSFP28 transmission module [ J ] based on PAM4 technology, 2019(02):51-54.
[3]Soenen W,Lambrecht J,Yin X,et al.PAM-4 VCSEL driver with selective falling-edge pre-emphasis[J].Electronics Letters,2018,54(3):155-157.
[4]Rito P,Lopez I G,Awny A,et al.High-efficiency 100-Gb/s 4-Vpp PAM-4 driver in SiGe:C BiCMOS for optical modulators[C]//2017 IEEE Asia Pacific Microwave Conference(APMC).Kuala Lumpar,Malaysia,2017:1-4.
Disclosure of Invention
NRZ formats have difficulty achieving higher transmission rate optical transmitters due to bandwidth limitations of conventional optical interconnects. In order to realize breakthrough of transmission rate under limited bandwidth, the invention provides a PAM4 transmitter driving circuit for high-speed optical interconnection based on SiGe BiCMOS process. The invention mainly utilizes the combination of sampling retiming and a 2:1 multiplexer to realize that the frequency of a required sampling clock is halved, breaks through the limit of sampling rate to transmission rate, realizes that four paths of NRZ signals are superposed into one path of PAM4 signals, greatly improves the transmission rate of single-path optical interconnection, is expected to be applied to the next generation of 100G/200G/400G Ethernet, and is described in detail as follows:
a PAM4 transmitter drive circuit for high speed optical interconnects, the circuit comprising:
four input buffer stages for providing input impedance matching;
the four D triggers are used for sampling and timing the input signals and eliminating phase difference;
two 2:1 multiplexers convert four paths of 25Gb/s NRZ signals into two paths of 50Gb/s NRZ signals;
two broadband amplifiers, which shape the output signal of the multiplexer and increase the bandwidth;
the CML adder is used for superposing the two paths of NRZ signals into a path of PAM4 signal to realize doubling of the single-path data transmission rate;
the broadband output buffer stage is used for providing output impedance matching, integrating two bandwidth expansion modes and improving the bandwidth of a transmission path.
Wherein the input buffer stage adopts a differential structure, and a feedback resistor R is indirectly arranged between the output node and the input nodeiA load resistor R connected between the output node and the power supply voltageoEnsuring output swing, RoAnd RiRealizing impedance matching; the input node and the differential pair transmitter stage are both connected to a tail current source.
Further, the D flip-flop is formed by cascading two stages of latches.
The CML adder is characterized in that a low-voltage cascode current mirror is introduced; the circuit halves the frequency of the required sampling clock by a combination of sample retiming and a 2:1 multiplexer.
Further, the wideband output buffer stage employs fTMultiplier structure for realizing same multiplicationThe reduction of the input capacitance of the differential pair is facilitated, and the active inductance structure is arranged, so that the bandwidth is increased in an inductance resonance mode.
The technical scheme provided by the invention has the beneficial effects that:
1. by using a PAM4 modulation mode, on the premise that the baud rate is not changed, the bit rate of transmission of each Unit Interval (UI) is doubled, and the circuit bandwidth is greatly saved at the same transmission rate;
2. through the combination of sampling retiming and a 2:1 multiplexer, the frequency of a required sampling clock is halved, the limitation of a sampling rate to a transmission rate is avoided, four paths of NRZ signals are superposed into one path of PAM4 signal, the maximum transmission rate of a single-path optical interconnection path is greatly improved, and the cost can be greatly reduced in an application scene of large data volume and long-distance transmission;
3. the design of a low-voltage cascode current mirror is introduced into a Current Mode Logic (CML) adder, so that the nonideal factors of current mirror image inaccuracy and output impedance change are avoided, and the output linearity of PAM4 superposition modulation is improved;
4. the invention adopts f in the broadband output buffer stageTThe structure of the multiplier realizes the reduction of the input capacitance of the differential pair under the same gain, and an active inductance structure is arranged to increase the bandwidth in an inductive resonance mode. Various bandwidth expansion modes are integrated in the circuit design, and a passive inductor occupying a large chip area is not introduced, so that the bandwidth of the whole transmission channel is improved, and better signal transmission quality is obtained.
In summary, the optical transmitter circuit provided by the invention has a good application prospect in practical application.
Drawings
Fig. 1 is an architecture diagram of a PAM4 transmitter driving circuit;
FIG. 2 is a circuit diagram of an input buffer stage;
FIG. 3 is a circuit diagram of a D flip-flop;
FIG. 4 is a circuit diagram of a 2:1 multiplexer;
FIG. 5 is a circuit diagram of a broadband amplifier;
FIG. 6 is a circuit diagram of a CML adder;
FIG. 7 is a circuit diagram of a broadband output buffer stage;
FIG. 8 is a schematic diagram of a 4-way 25Gb/s NRZ synthesis of 100Gb/s PAM 4.
(a) A 25Gb/s NRZ eye pattern for input data; (b) is a multiplexed 50Gb/s NRZ eye diagram; (c) is an output 100Gb/s PAM4 eye diagram.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below.
Example 1
An embodiment of the present invention provides a PAM4 transmitter driving circuit for high-speed optical interconnection, and referring to fig. 1, the circuit includes:
four input buffer stages providing input impedance matching of the circuit;
the four D triggers are used for sampling and timing the input signals and eliminating possible phase differences;
two 2:1 multiplexers convert four paths of 25Gb/s NRZ signals into two paths of 50Gb/s NRZ signals;
two broadband amplifiers, which shape the output signal of the multiplexer and increase the bandwidth;
and the CML adder is used for superposing the two paths of NRZ signals into one path of PAM4 signal to realize the doubling of the single-path data transmission rate.
The broadband output buffer stage integrates two bandwidth expansion modes while providing circuit output impedance matching, and improves the bandwidth of the whole transmission channel.
Example 2
Fig. 1 is an architecture diagram of a PAM4 transmitter drive circuit. Four paths of 25Gb/s NRZ signals are buffered by an input buffer stage, a D trigger is used for sampling and timing the signals, the signals after timing are multiplexed by two 2:1 multiplexers respectively to obtain two paths of 50Gb/s NRZ signals, the two paths of signals are amplified and shaped by a broadband amplifier, then signal superposition is carried out by a Current Mode Logic (CML) adder to obtain a path of PAM4 signals, and the PAM4 signals are buffered by a broadband output buffer stage and then output.
The following describes in detail the specific implementation of the key circuit blocks in the block diagram of fig. 1.
Fig. 2 is a circuit diagram of an input buffer stage. The whole structure adopts a differential structure, and the influence of noise on output is suppressed; input signal access differential pair Qa、QbRespectively, the collector is an output node VO-、VO+. Wherein, the feedback resistor R between the output node and the input nodeiA load resistor R connected between the output node and the power supply voltageoEnsuring output swing, RoAnd RiThe impedance matching is realized together, and the reflection of a high-frequency signal transmission line is reduced; the input node and the differential pair emitter are connected with a tail current source, so that the direct current working point of the circuit is ensured.
Fig. 3 is a circuit diagram of a D flip-flop, which is formed by cascading two stages of latches. For a single flip-flop, Q1a、Q1bThe base is connected with a differential input signal, the emitter is connected with the collector as an output node, and a load resistor R is connected between the collector and the power supply voltage1；Q2a、Q2bThe base electrode and the collector electrode are cross-coupled and connected with two output nodes, and the emitter electrode is connected; differential clock signals are respectively connected into Q3、Q4The collector electrodes of the clock differential pair are respectively connected with the emitter electrodes of the input differential pair and the emitter electrodes of the cross coupling pair, and the emitter electrodes of Q3 and Q4 are connected with the tail current tube Q0Is connected with the collector of the collector, the tail current base voltage is biased by a bias voltage VbAnd providing the emitter grounded. When CLK is positive, Q3On, Q4The latch is turned off and is in the sampling process; when CLK is negative, Q4On, Q3And turning off, and outputting a sampling signal when the latch outputs a positive clock to realize sampling and retiming of the signal.
FIG. 4 is a circuit diagram of a 2:1 multiplexer. It works in current-controlled mode, M1a、M1bAnd M2a、M2bInput pipes for two data paths respectively, and output nodes thereof are connected together, M3、M4Respectively their tail current tubes, R2As a load resistance, M3、M4The gate is connected to a resistor and is connected to a bias voltage VbiasA capacitor is connected between the grid and the clock signal to filter out direct current components; when the clock CLK is positive, M3Opening, M4Off, D in1 signal is outputted; when the clock CLK is negative, M4Opening, M3Off, DinThe 2 signal is output. Thus, the multiplexing of two paths of signals can be realized.
Fig. 5 is a circuit diagram of a wideband amplifier, which realizes waveform shaping of the output of the multiplexer and simultaneously obtains a larger bandwidth. Vi+And Vi-Accessing an input signal via Q2aAnd Q2bAmplified and provided at an output node VO+、VO-And (6) outputting. In the broadband extension method, a capacitance degeneration technology is used, and omega is introduced through a resistor Rs and a capacitor Csz＝-1/RSCSCompensating by a load resistor R3And CLThe bandwidth degradation caused by the low frequency pole formed.
FIG. 6 is a circuit diagram of a current-mode logic (CML) adder. Two taps are respectively connected with MSB (most significant bit) and LSB (least significant bit) signals, the tail current ratio is 2:1, namely the current of the output end of the MSB tap is 2 times of that of the LSB tap, and the MSB and LSB currents are at an output node VO-、VO+Is superposed, by means of a load resistor R4And converting the superposed current into a voltage signal and outputting the voltage signal. Wherein, the tail current adopts a low-voltage cascode structure, and M in MSB tap3a、M3bGrid electrode connected to bias voltage VbiasDrain electrodes are respectively connected with the reference current 2IrefAnd M1a、M1bThe source electrodes are connected with each other and M4a、M4bA drain electrode; m4a、M4bGrid and M3aThe drain electrodes are connected, and the source electrodes are connected to the ground potential; the LSB tap tail current is designed in accordance with the MSB structure and is distinguished by the reference current Iref. The introduction of the low-voltage cascode structure improves the mirror image precision, reduces the consumed voltage redundancy and also reduces the influence of the channel length modulation effect on the circuit.
Fig. 7 is a circuit diagram of a broadband output buffer stage and an equivalent circuit diagram of a part of the circuit thereof. Wholly adopt fTMultiplier knotStructure, Q5a、Q5bThe base of the differential input signal is connected with the differential input signal, and the collectors are respectively output nodes VO-、VO+，Q6a、Q6bIs connected to a bias voltage VbThe collector electrodes are respectively connected with VO-、VO+，Q5aAnd Q6bAre connected to the emitter of, Q5bAnd Q6aThe emitting electrodes are connected and are respectively connected with tail current tubes; introduced Q6a、Q6bThe tube reduces the equivalent input capacitance of the circuit to CπAnd 2, the total transconductance is unchanged, the reduction of the input capacitance of the differential pair under the same gain is realized, and the bandwidth is improved. M1a、M1bGrid electrode connecting resistor R5And an active inductance structure is formed and connected between the output node and the power voltage, the bandwidth is increased in an inductance resonance mode, and the size problem caused by inductance peaking is avoided.
FIG. 8 shows a schematic diagram of a 4-way 25Gb/s NRZ synthesis of 100Gb/s PAM 4. Fig. 8(a) shows a 25Gb/s NRZ eye pattern of input data, fig. 8(b) shows a 50Gb/s NRZ eye pattern after multiplexing, and fig. 8(c) shows an output 100Gb/s PAM4 eye pattern. The result shown in FIG. 8 proves that the circuit provided by the invention successfully realizes the synthesis of 4 paths of 25Gb/s NRZ signals into one path of 100Gb/s PAM4 signals.
In conclusion, the PAM4 signal transmitting circuit designed by the invention is expected to realize the transmission of single-channel 100Gb/s high-rate PAM4 signals. Compared with the traditional optical transmitter, the transmission with the same rate is realized, a multi-channel parallel circuit is not required to be introduced, the requirement on the sampling rate is reduced compared with a PAM4 transmitter realized abroad, and the linearity of a PAM4 signal is improved; and passive inductors occupying large-area chips are not used in the aspect of bandwidth expansion technology. The invention provides a new scheme for solving the problem of high-speed optical interconnection rate limitation.
In the embodiment of the present invention, except for the specific description of the model of each device, the model of other devices is not limited, as long as the device can perform the above functions.
Those skilled in the art will appreciate that the drawings are only schematic illustrations of preferred embodiments, and the above-described embodiments of the present invention are merely provided for description and do not represent the merits of the embodiments.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (5)

1. A PAM4 transmitter driver circuit for high speed optical interconnects, the circuit comprising:
four input buffer stages for providing input impedance matching;
the four D triggers are used for sampling and timing the input signals and eliminating phase difference;
two 2:1 multiplexers convert four paths of 25Gb/s NRZ signals into two paths of 50Gb/s NRZ signals;
two broadband amplifiers, shape the output signal of the multiplexer, and promote the bandwidth, the said broadband amplifier is: the capacitance degeneracy technology is used in the broadband extension, and omega is introduced through a resistor Rs and a capacitor Csz＝-1/RSCSCompensating by a load resistor R3And CLBandwidth degradation caused by the formed low frequency pole;
the CML adder is used for superposing the two paths of NRZ signals into one path of PAM4 signals to realize the doubling of the single-path data transmission rate, and comprises the following steps: the two taps are respectively connected with the most significant bit and the least significant bit signals, the tail current ratio is 2:1, namely the current of the output end of the most significant bit tap is 2 times of that of the least significant bit tap, and the two paths of currents of the most significant bit and the least significant bit are at an output node VO-、VO+Is superposed, by means of a load resistor R4Converting the superposed current into a voltage signal and outputting the voltage signal;
a broadband output buffer stage for providing output impedance matching, integrating two bandwidth expansion modes and increasing transmission channel bandwidth, wherein the broadband output buffer stage adopts fTThe multiplier structure realizes the reduction of the input capacitance of the differential pair under the same gain, and is provided with an active inductance structure to increase the bandwidth in an inductance resonance mode.
2. The PAM4 transmitter driver circuit for high-speed optical interconnect according to claim 1, wherein the input buffer stage has a differential structure with a feedback resistor R between the output node and the input nodeiA load resistor R connected between the output node and the power supply voltageoEnsuring output swing, RoAnd RiRealizing impedance matching; the input node and the differential pair transmitter stage are both connected to a tail current source.
3. The PAM4 transmitter driver circuit for high-speed optical interconnect according to claim 1, wherein the D flip-flop is cascaded with two stages of latches.
4. The PAM4 transmitter driver circuit for high-speed optical interconnect according to claim 1, wherein a low-voltage cascode current mirror is introduced into the CML adder.
5. The PAM4 transmitter driver circuit for high speed optical interconnects of claim 1, wherein the circuit halves the frequency of the required sampling clock by a combination of sample retiming and a 2:1 multiplexer.
CN202110181511.8A 2021-02-08 2021-02-08 PAM4 transmitter driving circuit for high-speed optical interconnection Active CN112994798B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110181511.8A CN112994798B (en) 2021-02-08 2021-02-08 PAM4 transmitter driving circuit for high-speed optical interconnection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110181511.8A CN112994798B (en) 2021-02-08 2021-02-08 PAM4 transmitter driving circuit for high-speed optical interconnection

Publications (2)

Publication Number Publication Date
CN112994798A CN112994798A (en) 2021-06-18
CN112994798B true CN112994798B (en) 2021-10-26

Family

ID=76393043

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110181511.8A Active CN112994798B (en) 2021-02-08 2021-02-08 PAM4 transmitter driving circuit for high-speed optical interconnection

Country Status (1)

Country Link
CN (1) CN112994798B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113702676B (en) * 2021-07-20 2024-04-12 中电科思仪科技股份有限公司 Broadband arbitrary waveform generation device and method based on CML interface
CN115296688B (en) * 2022-08-08 2023-10-13 慷智集成电路(上海)有限公司 Full duplex transmitting and receiving circuit, serial circuit chip, electronic equipment and vehicle

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109038212A (en) * 2018-08-20 2018-12-18 光梓信息科技（上海）有限公司 The laser drive circuit and light emission system of mixed mode
CN109217931A (en) * 2017-06-29 2019-01-15 瑞萨电子株式会社 Drive unit and optical communication system
CN109391249A (en) * 2017-08-07 2019-02-26 三星电子株式会社 Pulse amplitude modulation transmitter and pulse amplitude modulation receiver

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9674025B2 (en) * 2014-07-01 2017-06-06 International Business Machines Corporation 4-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phases

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109217931A (en) * 2017-06-29 2019-01-15 瑞萨电子株式会社 Drive unit and optical communication system
CN109391249A (en) * 2017-08-07 2019-02-26 三星电子株式会社 Pulse amplitude modulation transmitter and pulse amplitude modulation receiver
CN109038212A (en) * 2018-08-20 2018-12-18 光梓信息科技（上海）有限公司 The laser drive circuit and light emission system of mixed mode

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
25G NRZ或50G PAM-4双模式VCSEL激光器驱动电路研究设计;戴立鑫;《中国优秀博硕士学位论文全文数据库(硕士) 基础科学辑》;20210115(第01期);第4.1-4.3节 *
Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies;Jri Lee 等;《IEEE JOURNAL OF SOLID-STATE CIRCUITS》;20150930;第50卷(第9期);全文 *
High-efficiency 100-Gb/s 4-Vpp PAM-4 Driver in SiGe:C BiCMOS for Optical Modulators;P. Rito等;《Proceedings of 2017 Asia Pacific Microwave Conference》;20171231;全文 *
基于PAM4技术的50Gbit/s 40km QSFP28传输模块;肖蠡虎 等;《光通信研究》;20190430(第2期);全文 *

Also Published As

Publication number Publication date
CN112994798A (en) 2021-06-18

Similar Documents

Publication Publication Date Title
CN112994798B (en) PAM4 transmitter driving circuit for high-speed optical interconnection
Lee et al. Design and comparison of three 20-Gb/s backplane transceivers for duobinary, PAM4, and NRZ data
EP1911232B1 (en) Pre- and De-emphasis circuit.
CN106209709B (en) A kind of linear equalizer suitable for HSSI High-Speed Serial Interface
US8422591B2 (en) System and method for high speed communications using digital signal processing
CN110417480B (en) Optical transmitter driving circuit based on 3-tap feedforward equalization pre-emphasis
CN104135272A (en) Pre-emphasis LVDS (Low Voltage Differential Signaling) driver circuit capable of saving power consumption
Maruko et al. A 1.296-to-5.184 Gb/s transceiver with 2.4 mW/(Gb/s) burst-mode CDR using dual-edge injection-locked oscillator
CN111431618B (en) BiCMOS (Bipolar complementary Metal oxide semiconductor) optical transmitter driving circuit based on PAM4 modulation mode
CN112910565B (en) PAM4 signal receiving and demodulating circuit applied to high-speed optical interconnection
Lancheres et al. The MIPI C-PHY standard: A generalized multiconductor signaling scheme
JP3788945B2 (en) Multiplexed optical transmission equipment
CN102065039B (en) High-speed interface circuit adaptive equalization method and circuit therefor
CN113938144B (en) Duo-binary PAM4 transmitter and data transmission system
CN101714871A (en) Difference current type on-chip clock tree based on capacitance coupling mode
CN113904731A (en) Modulator and method for realizing PAM4 modulation
CN219875757U (en) Optical transceiver module, chip, circuit board, communication device and communication system
Yuminaka et al. A Bandwidth-Efficient Ternary Signaling Scheme for 1-D Partial-Response Channels.
US20240171209A1 (en) Magnetic coupling-based inter-chip wireless communication interface structure and method for three-dimensional stacked chips
Wang et al. A 16/32-Gb/s/pin Dual-Mode Single-Ended Transmitter with Pre-Emphasis FFE and RLM-Enhanced ZQ Calibration for Memory Interfaces
CN215452948U (en) Optical fiber trigger pulse transmission device
Mane et al. Power Optimized Transmitter for Future Switched Network
Wilson Single-Ended Signaling for Energy-Efficient Short-Reach Communication with High-Bandwidth Density
Wang et al. A 12 Gb/s chip-to-chip AC coupled transceiver
EP1423916B1 (en) Distributed multiplexer

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant