CN112909060A - Pixel structure and mask plate - Google Patents
Pixel structure and mask plate Download PDFInfo
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- CN112909060A CN112909060A CN202110143658.8A CN202110143658A CN112909060A CN 112909060 A CN112909060 A CN 112909060A CN 202110143658 A CN202110143658 A CN 202110143658A CN 112909060 A CN112909060 A CN 112909060A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
- H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/04—Coating on selected surface areas, e.g. using masks
- C23C14/042—Coating on selected surface areas, e.g. using masks using masks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
- H10K71/166—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using selective deposition, e.g. using a mask
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- Electroluminescent Light Sources (AREA)
Abstract
The invention provides a pixel structure and a mask plate. The pixel structure comprises a plurality of pixel units, wherein each pixel unit is provided with a first sub-pixel, a second sub-pixel and a third sub-pixel which are different in color; the pixel unit array is arranged into a plurality of rows and a plurality of columns, the pixel units of two adjacent columns are in a mirror symmetry structure, two adjacent third sub-pixels in the pixel units of two adjacent columns are in a mirror symmetry structure, and the arrangement mode of the first sub-pixels and the second sub-pixels of one pixel unit is the same as that of the first sub-pixels and the second sub-pixels of the other pixel unit. The invention greatly improves the pixel aperture opening ratio, reduces the manufacturing difficulty of the mask plate and improves the light-emitting area of the display device.
Description
Technical Field
The invention relates to the field of display, in particular to a pixel structure and a mask plate.
Background
The organic light emitting display device displays an image (OLED) by using a light emitting diode, and its display performance is excellent. The organic light emitting display device realizes differently displayed images by R, G, B three kinds of sub-pixel materials. Wherein the sub-pixel formation is realized by mask evaporation materials of a mask plate.
At present, Real pixel density (PPI) is the Real pixel density, and the display effect is good, and the current mainstream arrangement mode is as shown in fig. 1 and fig. 2. In the pixel arrangement shown in fig. 1, each pixel is opened by an independent mask plate, and in order to avoid color mixing, the distance between the pixels must be ensured to be larger than the distance between pixel-defined grooves, so that the aperture opening ratio is low. The arrangement in fig. 2 is slightly improved on the basis of fig. 1, and two adjacent B pixels can share one mask plate opening, so that the distance between the two B pixels can be smaller than the distance between one pixel defining groove, and the opening ratio is slightly increased but still lower. Both of the above arrangements are quite unsuitable when developing high pixel density products.
Disclosure of Invention
The invention aims to provide a pixel structure and a mask plate, and aims to solve the technical problem that the arrangement mode of the conventional pixel arrangement structure is not suitable for developing a high-pixel-density product.
In order to solve the above problems, the present invention provides a pixel structure, which includes a plurality of pixel units, each pixel unit having a first sub-pixel, a second sub-pixel and a third sub-pixel with different colors; the pixel unit array is arranged into a plurality of rows and a plurality of columns, the pixel units of two adjacent columns are in a mirror symmetry structure, two adjacent third sub-pixels in the pixel units of two adjacent columns are in a mirror symmetry structure, and the arrangement mode of the first sub-pixels and the second sub-pixels of one pixel unit is the same as that of the first sub-pixels and the second sub-pixels of the other pixel unit.
Further, in the pixel structure, the first sub-pixels are arranged in odd-numbered rows, the second sub-pixels are arranged in even-numbered rows, the first sub-pixels and the second sub-pixels are alternately arranged in a plurality of columns, the third sub-pixels are arranged between the columns where the first sub-pixels and the second sub-pixels are located, and the third sub-pixels are arranged corresponding to the rows where the first sub-pixels are located or the rows where the second sub-pixels are located.
Further, the area of the first sub-pixel and the area of the second sub-pixel are both smaller than the area of the third sub-pixel.
Further, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.
Further, the pixel units in any two adjacent rows and the four pixel units shared by the pixel units in any two adjacent columns form a repeating unit group.
Furthermore, in one repeating unit group, the four third sub-pixels are adjacently arranged and located at a position close to a central point of an area where the repeating unit group is located.
Furthermore, in the row direction, the distance between two columns of the first sub-pixels close to each other in two adjacent repeating unit groups ranges from 3 μm to 20 μm; in the row direction, the distance between two columns of the second sub-pixels close to each other in two adjacent repeating unit groups ranges from 3 μm to 20 μm.
Further, the distance between any two adjacent third sub-pixels in the same repeating unit group is in a range of 3 μm to 20 μm.
The invention also provides a mask plate which is used for manufacturing the pixel structure; the mask plate comprises a first sub-pixel mask plate, a second sub-pixel mask plate and a third sub-pixel mask plate; the first sub-pixel mask plate is used for manufacturing the first sub-pixel; two first sub-pixels in two adjacent repeating unit groups share one mask plate opening; the second sub-pixel mask plate is used for manufacturing the second sub-pixels; two second sub-pixels in two adjacent repeating unit groups share one mask plate opening; the third sub-pixel mask plate is used for manufacturing the third sub-pixel; and the four third sub-pixels in the same repeating unit group share one mask plate opening.
Furthermore, the mask plate opening of the first sub-pixel mask plate is in a rounded rectangle, the long side of the mask plate opening is in a linear shape, the four corners of the mask plate opening are in arc lines, and the short side of the mask plate opening is in an arc line or a linear shape; the mask plate opening of the second sub-pixel mask plate is in a round-corner rectangle, the long side of the second sub-pixel mask plate is in a linear type, the four corners of the second sub-pixel mask plate are in arc lines, and the short side of the second sub-pixel mask plate is in an arc line or a linear type; the mask plate hole of the third sub-pixel mask plate is in a round rectangle, the long edge of the mask plate is set to be a linear type, and the short edge of the mask plate can be set to be an arc line or a linear type.
Further, the mask plate is an alloy plate.
The pixel structure and the mask plate have the advantages that the pixel structure and the mask plate are provided by combining the pixel arrangement and the hole opening condition of the mask plate, the pixel aperture opening rate is greatly improved, the manufacturing difficulty of the mask plate is reduced, and the light emitting area of the display device is improved.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a current pixel arrangement;
FIG. 2 is a schematic view of another pixel arrangement in accordance with the present invention;
fig. 3A is a schematic structural diagram of a pixel structure according to an embodiment of the present invention, which mainly shows a region where the repeating unit group is located;
fig. 3B is a schematic structural diagram of another pixel structure in an embodiment of the present invention, which mainly shows a region where the repeating unit group is located;
fig. 4 is a schematic structural diagram of the first sub-pixel mask plate in the embodiment of the present disclosure;
fig. 5 is a schematic structural view of the second sub-pixel mask in the embodiment of the present disclosure;
fig. 6 is a schematic structural view of the third sub-pixel mask in the embodiment of the present disclosure;
fig. 7 is a schematic diagram of when the first sub-pixel, the second sub-pixel, and the third sub-pixel are correspondingly prepared by using the first sub-pixel mask plate, the second sub-pixel mask plate, and the third sub-pixel mask plate in the embodiment of the present invention.
The parts in the figures are numbered as follows:
a first sub-pixel mask plate 1, a second sub-pixel mask plate 2, a third sub-pixel mask plate 3,
the first opening 11, the second opening 21, the third opening 31,
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. Directional phrases used in connection with the present invention, such as, for example, rows, columns, etc., are used in the directional sense only with reference to the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
Referring to fig. 3A, a pixel structure 100 according to an embodiment of the present invention includes a plurality of pixel units 10, each pixel unit 10 having a first sub-pixel, a second sub-pixel and a third sub-pixel with different colors; in this embodiment, the first sub-pixel is a red sub-pixel (hereinafter referred to as an R sub-pixel), the second sub-pixel is a green sub-pixel (hereinafter referred to as a G sub-pixel), and the third sub-pixel is a blue sub-pixel (hereinafter referred to as a B sub-pixel). For simplicity, R, G, B is used to denote the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively, in the drawings.
The pixel units 10 are arranged in a plurality of rows and a plurality of columns in an array, the pixel units 10 in two adjacent columns are in a mirror symmetry structure, two adjacent third sub-pixels in the pixel units 10 in two adjacent columns are in a mirror symmetry structure, and the arrangement mode of the first sub-pixel and the second sub-pixel of one pixel unit 10 is the same as that of the first sub-pixel and the second sub-pixel of the other pixel unit 10.
In this embodiment, in the pixel structure 100, the first sub-pixels are arranged in odd-numbered rows, the second sub-pixels are arranged in even-numbered rows, the first sub-pixels and the second sub-pixels are alternately arranged in a plurality of columns, the third sub-pixels are disposed between the columns where the first sub-pixels and the second sub-pixels are located, and the third sub-pixels are disposed corresponding to the rows where the first sub-pixels are located or the rows where the second sub-pixels are located.
In this embodiment, the areas of the first sub-pixel and the second sub-pixel are smaller than the area of the third sub-pixel.
In this embodiment, the pixel units 10 in any two adjacent rows and the four pixel units 10 shared by the pixel units 10 in any two adjacent columns form a repeating unit group 20. That is, two adjacent pixel units 10 in the same row and two adjacent pixel units 10 in the row adjacent to the two pixel units 10 form a repeating unit group 20, and the repeating unit group 20 is arranged in an array.
In this embodiment, each repeating unit group 20 includes twelve sub-pixels, and the first sub-pixel, the second sub-pixel, and the third sub-pixel are four sub-pixels. The first sub-pixels of two adjacent repeating unit groups 20 on the same row are located on the same row, the second sub-pixels of two adjacent repeating unit groups 20 on the same row are located on the same row, and the third sub-pixels are arranged in a staggered manner with the first sub-pixels and the second sub-pixels. As shown in fig. 3A, in one repeating unit group, four of the third sub-pixels are adjacently disposed and located at a position close to the center point of the region (dashed box) where the repeating unit group is located.
In this embodiment, in the row direction, a range of a pitch L between two adjacent columns of the first sub-pixels in two adjacent repeating unit groups is 3 μm to 20 μm; in the row direction, the distance S between two adjacent columns of the second sub-pixels in two adjacent repeating unit groups ranges from 3 μm to 20 μm. The meaning of being close to each other is two columns of sub-pixels which are adjacently arranged at the side positions of two adjacent repeating unit groups. And the distance M between any two adjacent third sub-pixels in the same repeating unit group ranges from 3 micrometers to 20 micrometers.
As shown in fig. 3B, in another embodiment, in one repeating unit group 20, four second sub-pixels are disposed apart from each other and located on the left and right sides of the region (dashed line box) where the repeating unit group 20 is located.
The invention also provides a mask plate for manufacturing the pixel structure 100; the mask plate comprises a first sub-pixel mask plate 1, a second sub-pixel mask plate 2 and a third sub-pixel mask plate 3. As shown in fig. 4, fig. 4 is a schematic structural diagram of the first sub-pixel mask 1; as shown in fig. 5, fig. 5 is a schematic structural view of the second sub-pixel mask 2; as shown in fig. 6, fig. 6 is a schematic structural diagram of the third sub-pixel mask 3. The first sub-pixel mask 1 is used for manufacturing the first sub-pixel (R sub-pixel); two first sub-pixels in two adjacent repeating unit groups 20 share one mask plate opening; the second sub-pixel mask 2 is used for manufacturing the second sub-pixel (G sub-pixel); two second sub-pixels in two adjacent repeating unit groups 20 share one mask plate opening; the third sub-pixel mask 3 is used for manufacturing the third sub-pixel (B sub-pixel); the four third sub-pixels located in the same repeating unit group 20 share one mask opening.
Specifically, two R sub-pixels share one first opening 11, and the two sub-pixels have a pitch between 3 to 20 μm to increase the area ratio of the light emitting region. And the two sub-pixels adopt a linear design at the short edges which are close to each other, the long edges adopt a linear design, the four corners adopt an arc design, and the short edges which are not close to each other adopt a linear or arc design so as to better adapt to the opening of the mask plate.
Two sub-pixels of G share one second opening 21, and the distance between the two sub-pixels is 3-20 μm, so that the area ratio of a light-emitting region is increased. And the two sub-pixels adopt a linear design at the short edges which are close to each other, the long edges adopt a linear design, the four corners adopt an arc design, and the short edges which are not close to each other adopt a linear or arc design so as to better adapt to the opening of the mask plate.
The four B sub-pixels share one third opening 31 and are adjacent to each other at a pitch of 3-20 μm to increase the area ratio of the light emitting region. And the four sub-pixels adopt a linear design at the short edges which are close to each other, the long edges adopt a linear design, and the short edges which are not close to each other adopt a linear or arc design, so as to be better suitable for the open pore of the mask plate.
In this embodiment, the mask opening of the first sub-pixel mask 1 is a rounded rectangle, the long side of the mask opening is set to be a linear type, the four corners of the mask opening are set to be arc lines, and the short side of the mask opening is set to be an arc line or a linear type; the mask plate opening of the second sub-pixel mask plate 2 is in a round-corner rectangle, the long side of the second sub-pixel mask plate is in a linear type, the four corners of the second sub-pixel mask plate are in arc lines, and the short side of the second sub-pixel mask plate is in an arc line or a linear type; the mask plate hole of the third sub-pixel mask plate 3 is a rounded rectangle, the long edge of the mask plate is set to be linear, and the short edge of the mask plate can be set to be arc or linear.
In this embodiment, the mask is an alloy plate.
As shown in fig. 7, fig. 7 is a schematic diagram of when the first sub-pixel mask 1, the second sub-pixel mask 2, and the third sub-pixel mask 3 are adopted to correspondingly prepare the first sub-pixel, the second sub-pixel, and the third sub-pixel.
The pixel structure and the mask plate have the advantages that the pixel structure and the mask plate are provided by combining the pixel arrangement and the hole opening condition of the mask plate, the pixel aperture opening rate is greatly improved, the manufacturing difficulty of the mask plate is reduced, and the light emitting area of the display device is improved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A pixel structure is characterized by comprising a plurality of pixel units, wherein each pixel unit is provided with a first sub-pixel, a second sub-pixel and a third sub-pixel which are different in color; the pixel unit array is arranged into a plurality of rows and a plurality of columns, the pixel units of two adjacent columns are in a mirror symmetry structure, two adjacent third sub-pixels in the pixel units of two adjacent columns are in a mirror symmetry structure, and the arrangement mode of the first sub-pixels and the second sub-pixels of one pixel unit is the same as that of the first sub-pixels and the second sub-pixels of the other pixel unit.
2. The pixel structure according to claim 1, wherein the first sub-pixels are arranged in odd-numbered rows, the second sub-pixels are arranged in even-numbered rows, the first sub-pixels and the second sub-pixels are alternately arranged in a plurality of columns, the third sub-pixels are disposed between the columns where the first sub-pixels and the second sub-pixels are located, and the third sub-pixels are disposed corresponding to the rows where the first sub-pixels are located or the rows where the second sub-pixels are located.
3. The pixel structure according to claim 2, wherein the area of each of the first sub-pixel and the second sub-pixel is smaller than the area of the third sub-pixel.
4. The pixel structure of claim 2, wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.
5. The pixel structure according to claim 1, wherein four pixel units shared by two adjacent rows of pixel units and two adjacent columns of pixel units form a repeating unit group.
6. The pixel structure according to claim 5, wherein in one repeating unit group, four of the third sub-pixels are adjacently disposed and located at a position close to a central point of a region where the repeating unit group is located.
7. The pixel structure according to claim 6, wherein, in the row direction, the pitch of the first sub-pixels in two adjacent columns of the two adjacent repeating unit groups is in a range of 3 μm to 20 μm; in the row direction, the distance between two adjacent columns of the second sub-pixels in two adjacent repeating unit groups ranges from 3 μm to 20 μm.
8. The pixel structure according to claim 6, wherein the pitch of any two adjacent third sub-pixels in the same repeating unit group is in a range of 3 μm to 20 μm.
9. A mask for fabricating the pixel structure of any one of claims 1 to 8; the mask plate comprises a first sub-pixel mask plate, a second sub-pixel mask plate and a third sub-pixel mask plate;
the first sub-pixel mask plate is used for manufacturing the first sub-pixel; two first sub-pixels in two adjacent repeating unit groups share one mask plate opening;
the second sub-pixel mask plate is used for manufacturing the second sub-pixels; two second sub-pixels in two adjacent repeating unit groups share one mask plate opening;
the third sub-pixel mask plate is used for manufacturing the third sub-pixel; and the four third sub-pixels in the same repeating unit group share one mask plate opening.
10. A mask according to claim 9,
the mask plate opening of the first sub-pixel mask plate is in a round-corner rectangle, the long side of the first sub-pixel mask plate is in a linear type, the four corners of the first sub-pixel mask plate are in arc lines, and the short side of the first sub-pixel mask plate is in an arc line or a linear type;
the mask plate opening of the second sub-pixel mask plate is in a round-corner rectangle, the long side of the second sub-pixel mask plate is in a linear type, the four corners of the second sub-pixel mask plate are in arc lines, and the short side of the second sub-pixel mask plate is in an arc line or a linear type;
the mask plate hole of the third sub-pixel mask plate is in a round rectangle, the long edge of the mask plate is set to be a linear type, and the short edge of the mask plate can be set to be an arc line or a linear type.
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| CN202110143658.8A CN112909060A (en) | 2021-02-02 | 2021-02-02 | Pixel structure and mask plate |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110143658.8A CN112909060A (en) | 2021-02-02 | 2021-02-02 | Pixel structure and mask plate |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113921730B (en) * | 2021-09-29 | 2023-10-17 | 武汉华星光电半导体显示技术有限公司 | display panel |
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