CN112908387B

CN112908387B - Three-dimensional nonvolatile memory and control method thereof

Info

Publication number: CN112908387B
Application number: CN202110239612.6A
Authority: CN
Inventors: 赵利川
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-03-04
Filing date: 2021-03-04
Publication date: 2021-12-17
Anticipated expiration: 2041-03-04
Also published as: CN112908387A

Abstract

The present application provides a method of controlling a three-dimensional nonvolatile memory including a plurality of memory strings, a plurality of dummy memory strings, and a plurality of word lines electrically connected to channel layers of the memory strings, wherein at least some of the plurality of dummy memory strings are electrically connected to each other, wherein the method includes: applying an operating voltage to at least a portion of the word lines to perform a read operation, an erase operation, or a program operation; and applying a boosting voltage to the dummy memory strings electrically connected to each other during the applying of the operation voltage. The method can effectively reduce the setting time of the word line in the three-dimensional nonvolatile memory.

Description

Three-dimensional nonvolatile memory and control method thereof

Technical Field

The present application relates to the field of semiconductor technology. In particular, the present application relates to a three-dimensional nonvolatile memory and a control method thereof.

Background

To overcome the limitations of two-dimensional (2D) memory devices, integration density is currently increased by arranging memory cells three-dimensionally over a substrate. Taking 3D NAND memory as an example, it is a nonvolatile flash memory with memory cells stacked vertically in multiple layers. Existing 3D NAND memory cell architectures are typically designed for vertical channel, horizontal metal gate layers. Each metal gate layer is connected to a Word Line (Word Line) for receiving a signal for performing an operation on the memory cell array, wherein the operation includes an erase operation, a program operation, a read operation, or the like.

The word line setup time is an important factor affecting the read time and program time, which are important criteria for measuring the performance of the memory. Therefore, in order to reduce the read time and the program time as much as possible to achieve better performance, there have been various methods for reducing the word line setup time.

In the prior art, it is a common method to reduce the setup time by reducing the resistance and capacitance values of the word line itself, because the time for a signal to pass through the word line is affected by the RC time constant, which is proportional to the resistance and capacitance load values. This approach is limited by current fabrication techniques and processes for memory arrays. In addition, the word line setup time can be reduced by increasing the size of the switch and the voltage regulator, which has disadvantages in that not only the package area of the memory is increased but also a smaller amount of setup time reduction can be achieved. Further, by adding an over pulse to the output of the regulator, although the required word line setup time can be reduced, this approach is prone to overloading the memory array near the output of the regulator.

It should be appreciated that this background section is intended in part to provide a useful background for understanding the technology. This background section, however, may also include views, concepts or insights that are part of what is not known or understood by those of ordinary skill in the relevant art prior to the corresponding effective application date of the subject matter disclosed herein.

Disclosure of Invention

To solve or partially solve at least one of the above-mentioned problems occurring in the prior art, the present application provides a three-dimensional nonvolatile memory and a control method thereof to effectively reduce a setup time of a memory word line.

According to an aspect of the present application, there is provided a method of controlling a three-dimensional nonvolatile memory including a plurality of memory strings, a plurality of dummy memory strings, and a plurality of word lines electrically connected to channel layers of the memory strings, wherein at least some of the plurality of dummy memory strings are electrically connected to each other, wherein the method includes: applying an operating voltage to at least a portion of the word lines to perform a read operation, an erase operation, or a program operation; and applying an enhancement voltage to at least a portion of the dummy memory strings electrically connected to each other during the applying of the operating voltage.

In one embodiment of the present application, the applied boost voltage is either both a positive voltage or both a negative voltage with the applied operating voltage.

In one embodiment of the present application, the maximum value of the applied boost voltage is less than the maximum value of the applied operating voltage.

In one embodiment of the present application, the maximum value of the applied boosting voltage is 50% to 95% of the maximum value of the applied operating voltage.

In one embodiment of the present application, the application of the boosting voltage is started during a period in which the operating voltage is raised to a maximum value of the operating voltage and the voltage on the word line is smaller than the maximum value of the operating voltage.

In one embodiment of the present application, a three-dimensional nonvolatile memory includes a plurality of memory regions in a three-dimensional memory array, the memory regions including: a proximal region and a distal region, the distal region being a greater distance from a location at which the word line receives the operating voltage than the proximal region, wherein the step of applying the boosting voltage to at least a portion of the dummy memory strings electrically connected to each other includes applying the boosting voltage to at least a portion of the dummy memory strings electrically connected to each other located within the distal region.

In one embodiment of the present application, the three-dimensional nonvolatile memory further includes a switch unit, a driving module, and a control module, wherein the switch unit includes a plurality of switches and a plurality of sub-switch units, the plurality of sub-switch units are respectively connected to the driving module through the plurality of switches, each of the plurality of sub-switch units includes a plurality of sub-switches, the plurality of sub-switches are respectively connected to at least some of the dummy memory strings electrically connected to each other, wherein applying the boosting voltage to at least some of the dummy memory strings electrically connected to each other located in the distal end region includes: controlling the on-off states of the switches and the sub-switches by using the control module; generating an enhancement voltage with a drive module; and applying an enhancement voltage to at least a portion of the dummy memory strings within the distal region that are electrically connected to each other by selecting the switches and the sub-switches that are turned on.

In one embodiment of the present application, the three-dimensional nonvolatile memory further includes a plurality of dummy word lines electrically connected to the channel layer of the dummy memory string, and a bottom select gate electrically connected to the bottom of the dummy memory string, wherein the method further includes: a program voltage is applied to at least one of the plurality of dummy word lines adjacent to the bottom select gate to program memory cells of a dummy memory string connected to the at least one dummy word line to an off state.

According to another aspect of the present application, there is provided a three-dimensional nonvolatile memory including: a three-dimensional memory array including a plurality of memory strings, a plurality of dummy memory strings, and a plurality of word lines electrically connected to channel layers of the memory strings, wherein at least some of the plurality of dummy memory strings are electrically connected to each other; the control circuit is coupled with the three-dimensional storage array and is used for controlling the reading operation, the erasing operation or the programming operation of the three-dimensional storage array; wherein the control circuit is configured to: in response to applying an operating voltage to at least a portion of the word lines, an enhancement voltage is applied to at least a portion of the dummy memory strings electrically connected to each other during the application of the operating voltage, wherein the operating voltage is used to perform a read operation, an erase operation, or a program operation on the three-dimensional nonvolatile memory.

In one embodiment of the present application, the control circuit includes a driving module configured to apply an enhancement voltage to at least a portion of the dummy memory strings electrically connected to each other during application of the operating voltage.

In one embodiment of the present application, the boosting voltage applied by the driving module is either a positive voltage or a negative voltage.

In one embodiment of the present application, the maximum value of the boosting voltage applied by the driving module is smaller than the maximum value of the operating voltage.

In one embodiment of the present application, the maximum value of the boosting voltage applied by the driving module is 50% to 95% of the maximum value of the applied operating voltage.

In one embodiment of the present application, the driving module is further configured to start applying the boosting voltage during a period in which the operating voltage rises to a maximum value of the operating voltage and the voltage on the word line is less than the maximum value of the operating voltage.

In one embodiment of the present application, the control circuit further comprises: a switch unit including a plurality of switches and a plurality of sub-switch units, the plurality of sub-switch units being respectively connected to the driving module through the plurality of switches, each of the plurality of sub-switch units including a plurality of sub-switches, the plurality of sub-switches being respectively connected to at least a part of the dummy memory strings; and a control module controlling on-off states of the plurality of switches and the plurality of sub-switches, wherein the driving module is further configured to apply the boosting voltage to at least a part of the dummy memory strings by selecting the switches and sub-switches that are turned on.

In one embodiment of the present application, a three-dimensional memory array includes a plurality of memory regions, the memory regions including: a proximal region and a distal region, the distal region being spaced from a location at which the word line receives the operating voltage by a distance greater than a distance between the proximal region and the location at which the word line receives the operating voltage; the control circuit is further configured to: in response to applying an operating voltage to at least a portion of the word lines, an enhancement voltage is applied to at least a portion of dummy memory strings of the storage regions that are electrically connected to each other within a distal region during application of the operating voltage.

In one embodiment of the present application, the three-dimensional memory array comprises a three-dimensional NAND memory array.

In one embodiment of the present application, a plurality of top select gate cutouts are further included, the top select gate cutouts extending in a direction parallel to the substrate and penetrating an upper portion of the stacked structure of the three-dimensional nonvolatile memory in a direction perpendicular to the substrate.

In one embodiment of the present application, at least a portion of the plurality of dummy memory strings is disposed below the top select gate cut.

In one embodiment of the present application, each dummy memory string includes a dummy channel structure, and wherein a connection portion electrically connected to the dummy channel structure is formed on the dummy channel structure of at least a portion of the dummy memory string.

In one embodiment of the present application, at least some of the dummy memory strings are electrically connected to each other through a connection line by a connection portion.

In one embodiment of the present application, a plurality of sub-switch units respectively correspond to the plurality of storage areas, wherein each of the plurality of sub-switch units includes a plurality of sub-switches respectively electrically connected to at least some of the dummy memory strings located in the far-end area in the corresponding storage area and electrically connected to each other.

The three-dimensional nonvolatile memory provided by the application can effectively reduce the word line setting time in the memory without increasing the memory area.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. In the drawings:

fig. 1 is a schematic top view illustrating a partial storage region having a Top Select Gate (TSG) cut region of a 3D nonvolatile memory according to an embodiment of the present application.

Fig. 2 is a cross-sectional side view illustrating a portion of a storage area having a TSG cut-out region of a 3D nonvolatile memory according to an embodiment of the present application.

Fig. 3 is a schematic structural block diagram showing a 3D nonvolatile memory according to an embodiment of the present application.

Fig. 4 is a schematic diagram illustrating connection of a dummy memory string with a switch unit inside a memory area according to an embodiment of the present application.

Fig. 5 is a flowchart illustrating a control method of a 3D nonvolatile memory according to an embodiment of the present application.

Fig. 6A is a voltage timing diagram illustrating a word line of a 3D nonvolatile memory according to the related art.

Fig. 6B is a voltage timing diagram illustrating a word line of a 3D nonvolatile memory according to the related art.

Fig. 6C is a voltage timing diagram illustrating a word line of a 3D nonvolatile memory according to an embodiment of the present application.

Detailed Description

While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without parting from the spirit and scope of the disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in various other applications.

Note that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

In general, terms may be understood at least in part from the context of their use. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a" or "the" may also be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context. Moreover, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described, again depending at least in part on the context.

It should be readily understood that the meanings of "on", "above" and "over" in the present disclosure should be interpreted in the broadest manner, such that "on" not only means "directly on" but also includes the meaning of "on" and having intermediate features or layers therebetween, and "above" or "over" not only means "above" or "over" but also can include the meaning of "above" or "over" and having no intermediate features or layers therebetween (i.e., directly on something).

Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material to which a subsequent layer of material is added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is generally where the semiconductor devices are formed, and thus the semiconductor devices are formed at the top side of the substrate unless otherwise specified. The bottom surface is opposite the top surface and thus the bottom side of the substrate is opposite the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a number of semiconductor materials (such as silicon, germanium, gallium arsenide, indium phosphide, and the like). Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entire superstructure or understructure, or may have a smaller extent than the understructure or superstructure. Furthermore, the layer may be a region of a continuous structure, uniform or non-uniform, having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of levels at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. For example, as used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-wise terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that the terms "comprises," "comprising," "has," "having," "includes" and/or "including," when used in this specification, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Moreover, when a statement such as "at least one of" appears after a list of listed features, the entirety of the listed features is modified rather than modifying individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Three-dimensional (3D) memory refers to a semiconductor memory having vertically oriented strings of memory cell transistors (referred to herein as "memory strings") on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "stacking direction" refers to a direction nominally perpendicular to the substrate.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 and 2 show a top view schematic and a cross-sectional schematic, respectively, of a portion of a storage region 100 of a three-dimensional non-volatile memory having a TSG cut in accordance with an embodiment of the present application. Where the X direction is the word line direction and the Y direction is the bit line direction in fig. 2. In general, word lines and bit lines are arranged perpendicular to each other (e.g., in rows and columns, respectively), forming an "array" of three-dimensional non-volatile memory.

The three-dimensional nonvolatile memory includes a plurality of memory areas 100, each memory area 100 having a plurality of memory strings 111 and a plurality of dummy memory strings 112. According to one embodiment, as shown in fig. 1, the storage area 100 may be a minimum repeating unit of the three-dimensional nonvolatile memory, that is, the storage area 100 may be a storage block, but is not limited thereto.

The three-dimensional nonvolatile memory may further include a plurality of gate line slits (not shown) that separate the respective memory regions 100. The gate line slit laterally extends parallel to the TSG cut 121 and penetrates the stacked structure of the three-dimensional nonvolatile memory in a direction perpendicular to the substrate 11.

As shown in fig. 1, the three-dimensional nonvolatile memory includes a Top Select Gate (TSG) cut 121 extending laterally in an X direction (word line direction), the TSG cut 121 extending in a direction parallel to the substrate 11, which may divide the memory area 100 into two non-TSG cut regions 122, so as to allow a select voltage and/or a non-select voltage to be applied to the memory strings 111 in the above-mentioned different non-TSG cut regions 122, respectively, through a bit line logic circuit, thereby allowing the memory strings 111 in the different TSG cut regions 122 to be individually selected or deselected so as to perform various operations, for example, a read operation, an erase operation, or a program operation, in a desired region (e.g., non-TSG cut region) of the 3D NAND memory. According to an exemplary embodiment of the present application, a plurality of dummy storage strings 112 are disposed within the area of the TSG cut 121, e.g., at least a portion of the plurality of dummy storage strings 112 is located below the TSG cut of the storage area 100.

Each memory region 100 may be divided into a proximal region N adjacent to a location where the word line receives the external operating voltage, and a distal region F (shown in fig. 1) distant from the location where the word line receives the external operating voltage, the distal region F being spaced apart from the location where the word line receives the operating voltage by a distance greater than the proximal region N. At least a portion of the dummy memory strings 112 located in the region where the TSG cuts are located and located in the distal region are electrically connected to each other by the connection portion 114 and the connection line 113. In one embodiment, all dummy memory strings 112 located in the area where the TSG cut is located and located in the distal area (i.e., distal to the word line) are electrically connected to each other through the connection portion 114 and the connection line 113 (shown in fig. 2). The connection portion 114 may be made of metal, and the connection line 113 may be a metal wire.

It should be understood that the number of TSG cuts 121 and non-TSG cut regions 122 of storage area 100 is not limited thereto, and different numbers of TSG cuts 121 and non-TSG cut regions 122 may be provided according to actual needs.

FIG. 2 is a side view schematic of a cross section of the three-dimensional nonvolatile memory along the AA plane in FIG. 1. Note that the x-axis, y-axis, and z-axis are included in FIG. 2 to further illustrate the spatial relationship of storage area 100.

The memory region 100 includes a substrate 11 and conductive and dielectric layers 21 alternately stacked vertically on the substrate 11 in a z-direction to form a stacked structure. The TSG cut 121 penetrates the upper portion of the stacked structure in a direction perpendicular to the substrate 11. According to an exemplary embodiment, the TSG cut 121 vertically penetrates the uppermost conductive layer and the dielectric layer of the stacked structure, thereby separating the uppermost conductive layer into

TSG layers

131 and 132. TSG layers 131 and 132 are configured to control the drains of memory strings 111 in respective non-TSG cut regions 122. The conductive layer also includes a Bottom Select Gate (BSG) layer 133, the BSG layer 133 configured to control common sources of the dummy memory strings 112 and the memory strings 111 in the storage region 100. The material of the conductive layer may be a conductive material, such as metal tungsten, cobalt, copper, nickel, etc., and may also be polysilicon, doped silicon, or any combination thereof. The material of the dielectric layer 21 may be selected from the group consisting of and include at least one insulating dielectric such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and the like, and combinations thereof.

A plurality of dummy memory strings 112 are disposed below the TSG cut 121, and the gate of the memory cell of each dummy memory string 112 is connected to a dummy word line. Each dummy memory string 112 includes a dummy channel structure, wherein a connection portion 114 electrically connected to the dummy channel structure is formed above the dummy channel structure of at least some of the dummy memory strings 112, and the connection portion 114 is used to connect with a connection line 113 (e.g., a metal wire).

A plurality of memory strings 111 are disposed in the non-TSG cut region 122, and the gate of the memory cell of each memory string 111 is connected to a word line.

According to one embodiment, the stacked structure is composed of, from top to bottom, a TSG layer, a gate layer connected to a dummy word line, at least one gate layer connected to a word line, a gate layer connected to a dummy word line, and a BSG layer. Wherein, the number of the gate layers connected with the dummy word line and the number of the gate layers connected with the word line are set according to actual needs.

Since at least some of the dummy memory strings 112 located at the far end regions are electrically connected to each other, a boosting voltage may be applied to these at least some of the dummy memory strings 112 electrically connected to each other using a control circuit including a control module, a driving module, and a switching unit to reduce a setup time of word lines.

Fig. 3 shows a schematic block diagram of a three-dimensional nonvolatile memory with a control circuit according to an embodiment of the present disclosure. As shown in fig. 3, the three-dimensional nonvolatile memory includes a three-dimensional memory array 110, a control module 210, a driving module 220, a decoder 230, a switching unit 240, and a read/program/erase circuit 250. Among them, the three-dimensional memory array 110 may include a plurality of memory strings 111, a plurality of dummy memory strings 112, and a plurality of word lines WL electrically connected to channel layers of the memory strings 111.

The control module 210 is coupled to the driving module 220, the decoder 230, and the read/program/erase circuit 250. The control module 210 is configured to: based on different commands CMD (e.g., read command, program command, or erase command) and address information, the control module 210 may generate corresponding control signals, respectively. The driving module 220 may generate various voltages used in the three-dimensional nonvolatile memory, for example, an operation voltage applied to the word lines WL, an enhancement voltage applied to the dummy memory strings 112 located in the distal end region, which are electrically connected to each other, and a string selection voltage and a ground selection voltage (not shown) applied to the string selection lines SSL and the ground selection lines GSL, respectively. The decoder 230 may receive the conversion address CA from the control module 210 and decode the received address to generate a decoded address, and the decoder 230 may further select a corresponding word line WL according to the decoded address and apply the operating voltage generated by the driving module 220 to the selected word line WL. In addition, the decoder 230 may also control the on/off state of the switch unit 240 according to the control signal generated by the control module 210, thereby selecting the dummy memory string 112 electrically connected to the switch unit 240, and applying the boosting voltage generated by the driving module 220 to the selected dummy memory string 112. The read/program/erase circuit 250 may be coupled to the memory array 110 via the bit line BL and controlled by the control module 210.

According to one embodiment, the control module 210 may receive the read/program/erase command CMD and the physical address ADDR, generate the translation address CA, and control the driving module 220 to generate the corresponding operation voltage (e.g., read/program/erase voltage) and the enhancement voltage. The decoder 230 may select a corresponding word line WL based on the conversion address CA received from the control module 210 and apply the operation voltage generated by the driving module 220 to the selected word line WL. In addition, the decoder 230 may also control the on-off state of the switch unit 240 so as to select the dummy memory string 112 electrically connected to the switch unit 240, and apply the boosting voltage generated by the driving module 220 to the selected dummy memory string 112. According to one embodiment, the decoder 230 starts to apply the boosting voltage generated by the driving module 220 to the selected dummy memory string 112 during a period when the operating voltage applied to the word line WL in the three-dimensional nonvolatile memory rises to the maximum value and the voltage on the word line WL is less than the maximum value of the operating voltage. When the selected dummy memory string 112 receives the boosting voltage, the voltage variation rate of the far end of the word line WL can be significantly increased due to the overlapping effect of the boosting voltage and the operating voltage, thereby effectively reducing the setting time of the word line WL without affecting the voltage of the near end of the word line WL.

According to one embodiment, the control module may be a control logic unit, but is not limited thereto. According to one embodiment, the driving module may be a voltage generator, but is not limited thereto.

Fig. 4 shows a schematic structural circuit diagram of the switching unit 240 according to an embodiment of the present application.

As shown in fig. 4, each storage area of the three-dimensional nonvolatile memory has a plurality of dummy memory strings 112. The channels of the memory cells that make up the same dummy memory string 112 are physically connected. At least one transistor at the top of each dummy memory string 112 is connected to a dummy word line, and transistors at the bottom of the dummy memory strings 112 are connected to BSG lines formed of BSG layers.

The switch unit 240 of the three-dimensional nonvolatile memory includes a plurality of switches 2401 and a plurality of sub-switch units 2402, wherein each sub-switch unit 2402 includes a plurality of sub-switches 2403. According to one embodiment, the plurality of sub-switch units 2402 correspond to the plurality of storage areas 100, respectively, and each sub-switch 2403 of the sub-switch units 2402 is electrically connected to at least a part of the dummy storage strings 112 in the corresponding storage area 100, specifically, each dummy storage string 112 of the plurality of dummy storage strings electrically connected to each other through the connection line 113, while each sub-switch unit 2402 is electrically connected to each switch 2401 in one-to-one correspondence, respectively. After the control module controls the on-off states of the switch 2401 and the sub-switch 2403, the driving module 220 generates an enhanced voltage according to actual needs, and the generated enhanced voltage may be applied to at least a portion of the dummy memory strings 112 electrically connected to each other through the connection line 113 through the switching unit 240.

Fig. 5 is a flowchart illustrating a control method of a 3D nonvolatile memory according to an embodiment of the present application. Fig. 6A to 6C are timing charts of applied voltages according to the related art and according to the embodiment of the present application, respectively.

As shown in fig. 5, the control method for reducing the word line set time includes:

s501: an operating voltage is applied to at least a portion of the word lines to perform a read operation, an erase operation, or a program operation.

S502: during the application of the operating voltage, an enhancement voltage is applied to at least a portion of the dummy memory strings electrically connected to each other, thereby reducing a setup time of the word lines.

A control method S501-S502 of the 3D nonvolatile memory according to an embodiment will be described in detail with reference to fig. 3 to 6C. For ease of understanding, a 3D NAND memory is hereinafter described as an example, however, the present application is not limited thereto. It will be appreciated by those skilled in the art that the present application is also applicable to other non-volatile memories having a similar structure.

Step S501:

when a certain memory cell in the memory is subjected to a read operation, an erase operation, or a program operation, it is necessary to determine a memory string and a row in which the selected memory cell is located, where the memory string in which the selected memory cell is located is used as a selected memory string, and the row in which the selected memory cell is located is used as a selected row. After determining the memory string and the row of the selected memory cell, an operating voltage is applied to the word line corresponding to the selected memory cell by the word line source to perform a read operation, an erase operation or a program operation.

Step S502:

during a period in which the applied operating voltage rises to a maximum value of the operating voltage and a voltage on a word line corresponding to the selected memory cell is less than the maximum value of the operating voltage, a boosting voltage is applied to dummy memory strings located in the distal end region and electrically connected to each other. According to an exemplary embodiment, the boosting voltage may be directly applied to the connection lines 113 for electrically connecting the dummy memory strings 112 to each other through the driving module 220. According to another exemplary embodiment, the boosting voltage may be applied using the control module 210, the driving module 220, and the switching unit 240 (as shown in fig. 3).

In order to reduce the setup time of the word line as much as possible, an enhancement voltage in the same direction as the applied operation voltage, i.e., either the same positive voltage or the same negative voltage, is applied to the word line. Since the voltage change rate of the near end of the word line is faster than that of the far end of the word line, the voltage change rate of the far end of the word line is increased while the over-pulse phenomenon of the near end of the word line is avoided, and therefore the maximum value of the applied enhancement voltage is smaller than the maximum value of the applied operating voltage. For example, the applied boosting voltage is 50% to 95% of the maximum value of the applied operating voltage. Meanwhile, in order to ensure better voltage enhancement effect, the maximum value of the applied enhancement voltage should be as large as possible on the basis of being smaller than the maximum value of the applied operating voltage, so as to prevent the programming of the dummy memory cells in the dummy memory string 112 and ensure that the dummy memory cells have lower threshold voltages, and thus ensure the coupling effect between the dummy word lines and the channels corresponding to the dummy memory cells.

In one embodiment, for example, as shown in FIG. 6C, curve a is a voltage timing curve at the word line source that provides the read voltage or program voltage for the word line. Curve d1 (the solid curve portion) is a voltage timing curve at the near end of the word line. When the word line source applies an operating voltage to the word line to a predetermined value, that is, after the curve a reaches a maximum value, the control circuit starts to apply an enhancement voltage to at least a part of the dummy memory strings located at the far end of the word line and electrically connected to each other, as shown by a curve a', wherein the applied enhancement voltage is in the same direction as the read voltage and the program voltage and has a smaller magnitude than the read voltage and the program voltage, thereby obtaining a voltage timing curve d2 at the far end of the word line. As shown in fig. 6C, the slope of curve d2 (the dashed curve portion) becomes significantly larger after the dummy memory string is applied with the boosting voltage, i.e., applying the boosting voltage to at least a portion of the dummy memory strings located at the far end of the word line and electrically connected to each other increases the rate of change of the voltage at the far end of the word line.

In one embodiment, to ensure a better voltage boosting effect, a program voltage may be applied to at least one dummy word line adjacent to the bottom select gate among the plurality of dummy word lines to program memory cells of a dummy memory string connected to the at least one dummy word line to an off state.

Fig. 6A to 6C are timing charts of applied voltages according to the related art and according to the embodiment of the present application, respectively.

Curve a is the voltage timing curve at the word line source providing the voltage source for the word line, curve b1 is the voltage timing curve at the near end of the word line, and curve b2 is the voltage timing curve at the far end of the word line. It can be seen that the rate of change of the voltage at the far end of the word line is less than the rate of change of the voltage at the near end of the word line due to the resistive and capacitive loading of the word line, which results in longer setup time for the word line.

Fig. 6B is a voltage timing diagram illustrating a word line of a 3D nonvolatile memory according to another embodiment.

Curve a is the voltage timing curve at the word line source providing the voltage source for the word line, curve c1 is the voltage timing curve at the near end of the word line, and curve c2 is the voltage timing curve at the far end of the word line. Adding an over-pulse voltage signal to the voltage at the word line source can increase the rate of change of the voltage at the far end of the word line, thereby reducing the setup time for the word line, as compared to the case of fig. 6A where no over-pulse is added. However, due to the existence of the over-pulse signal, the phenomenon of over-pulse also occurs at the near end of the word line, and the situation easily causes overload of the memory array.

According to the embodiment of the present application, when a read operation and a program operation are required for a memory, a curve a is a voltage timing curve at a word line source providing a read voltage or a program voltage for a word line, and a curve a' is a curve of an enhanced voltage applied to a dummy memory string by a control circuit after the word line source provides the read voltage or the program voltage. Curve d1 is the voltage timing curve at the near end of the word line, while curve d2 is the voltage timing curve at the far end of the word line. As shown in fig. 6C, the control circuit starts to apply the boosting voltage during a period in which the voltage at the word line source rises to the maximum value and the voltage on the word line does not reach the maximum value. The applied enhancement voltage is in the same direction as the reading voltage and the programming voltage, and the amplitude of the applied enhancement voltage is smaller than the reading voltage and the programming voltage. Since the boosting voltage is applied only to the dummy memory string at the far end of the word line, it is possible to effectively increase the rate of voltage change at the far end of the word line without affecting the voltage at the near end of the word line, that is, to effectively reduce the setup time of the word line.

It should be noted that additional steps may be provided before, during, and after the manufacturing method, and that some of the steps described herein may be replaced, deleted, performed in a different order, or performed in parallel for additional embodiments of the manufacturing method.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A method of controlling a three-dimensional nonvolatile memory including a plurality of memory strings, a plurality of dummy memory strings, and a plurality of word lines electrically connected to channel layers of the memory strings, wherein at least some of the plurality of dummy memory strings are electrically connected to each other, wherein the method comprises:

applying an operating voltage to at least a portion of the word lines to perform a read operation, an erase operation, or a program operation; and

applying an enhancement voltage to the at least portions of dummy memory strings that are electrically connected to each other during the applying of the operating voltage.

2. The method of claim 1, wherein the applied boost voltage is either both a positive voltage or both a negative voltage with the applied operating voltage.

3. The method of claim 2, wherein a maximum value of the applied boost voltage is less than a maximum value of the applied operating voltage.

4. A method according to claim 3, wherein the maximum value of the applied boost voltage is 50-95% of the maximum value of the applied operating voltage.

5. The method of claim 1, wherein applying the boost voltage is initiated during a period when the operating voltage rises to a maximum value of the operating voltage and the voltage on the word line is less than the maximum value of the operating voltage.

6. The method of any of claims 1-5, wherein the three-dimensional non-volatile memory comprises a plurality of storage regions in a three-dimensional storage array, the storage regions comprising: a proximal region and a distal region, the distal region being a greater distance from a location at which the word line receives the operating voltage than the proximal region,

wherein applying the boosting voltage to the at least some dummy memory strings electrically connected to each other comprises applying the boosting voltage to the at least some dummy memory strings electrically connected to each other located within the distal region.

7. The method of claim 6, wherein the three-dimensional nonvolatile memory further comprises a switch unit, a driving module, and a control module, wherein the switch unit comprises a plurality of switches and a plurality of sub-switch units, the plurality of sub-switch units are respectively connected to the driving module through the plurality of switches, each of the plurality of sub-switch units comprises a plurality of sub-switches, the plurality of sub-switches are respectively connected to the at least part of the dummy memory strings electrically connected to each other,

wherein applying the boosting voltage to the at least some dummy memory strings located within the distal region that are electrically connected to each other comprises:

controlling the on-off states of the plurality of switches and the plurality of sub-switches by using the control module;

generating an enhancement voltage with the drive module; and

applying the boosting voltage to the at least part of the dummy memory strings within the distal end region that are electrically connected to each other by selecting the switch and the sub-switch that are turned on.

8. The method of claim 1, wherein the three-dimensional non-volatile memory further comprises a plurality of dummy word lines electrically connected to a channel layer of the dummy memory string, and a bottom select gate electrically connected to a bottom of the dummy memory string, wherein the method further comprises:

applying a programming voltage to at least one of the plurality of dummy word lines adjacent to the bottom select gate to program memory cells of a dummy memory string connected to the at least one dummy word line to an off state.

9. A three-dimensional non-volatile memory, the three-dimensional non-volatile memory comprising:

a three-dimensional memory array including a plurality of memory strings, a plurality of dummy memory strings, and a plurality of word lines electrically connected to channel layers of the memory strings, wherein at least some of the plurality of dummy memory strings are electrically connected to each other; and

control circuitry coupled to the three-dimensional memory array and configured to control a read operation, an erase operation, or a program operation on the three-dimensional memory array;

wherein the control circuit is configured to: applying an enhancement voltage to the at least a portion of the dummy memory strings electrically connected to each other during application of an operating voltage in response to application of the operating voltage to at least a portion of the word lines, wherein the operating voltage is used to perform a read operation, an erase operation, or a program operation on the three-dimensional nonvolatile memory.

10. The three-dimensional nonvolatile memory of claim 9 wherein the control circuit comprises: a driving module configured to apply an enhancement voltage to the at least part of the dummy memory strings electrically connected to each other during the application of the operation voltage.

11. The three-dimensional nonvolatile memory according to claim 10, wherein the boosting voltage applied by the driving module is either both a positive voltage or both a negative voltage with the operating voltage.

12. The three-dimensional nonvolatile memory according to claim 11, wherein a maximum value of the boosting voltage applied by the driving module is smaller than a maximum value of the operating voltage.

13. The three-dimensional nonvolatile memory according to claim 12, wherein the maximum value of the boosting voltage applied by the driving module is 50% to 95% of the maximum value of the applied operating voltage.

14. The three-dimensional nonvolatile memory of claim 10 wherein the drive module is further configured to begin applying the boost voltage during a period when the operating voltage rises to a maximum value of the operating voltage and the voltage on the word line is less than the maximum value of the operating voltage.

15. The three-dimensional nonvolatile memory of claim 10 wherein the control circuit further comprises:

a switching unit including a plurality of switches and a plurality of sub-switching units, the plurality of sub-switching units being respectively connected to the driving module through the plurality of switches, each of the plurality of sub-switching units including a plurality of sub-switches, the plurality of sub-switches being respectively connected to the at least part of the dummy storage strings; and

a control module controlling on-off states of the plurality of switches and the plurality of sub-switches,

wherein the drive module is further configured to apply the boosting voltage to the at least a portion of the dummy storage strings by selecting the switches and the sub-switches that are turned on.

16. The three-dimensional nonvolatile memory according to claim 15,

the three-dimensional memory array includes a plurality of memory regions, the memory regions including: a proximal region and a distal region, the distal region being a greater distance from a location at which the word line receives the operating voltage than the proximal region;

the control circuit is further configured to: in response to applying an operating voltage to at least a portion of the word lines, applying the boosting voltage to the at least a portion of the dummy memory strings located within the distal region that are electrically connected to each other during the application of the operating voltage.

17. The three-dimensional nonvolatile memory of claim 9 wherein the three-dimensional memory array comprises a three-dimensional NAND memory array.

18. The three-dimensional nonvolatile memory of claim 16 further comprising:

a plurality of top select gate cuts extending in a direction parallel to a substrate and penetrating an upper portion of a stacked structure of the three-dimensional non-volatile memory in a direction perpendicular to the substrate.

19. The three-dimensional non-volatile memory of claim 18, wherein the at least some of the plurality of dummy storage strings are disposed below the top select gate cut.

20. The three-dimensional non-volatile memory of claim 9, wherein each of the dummy storage strings comprises a dummy channel structure, an

Wherein a connection portion electrically connected to the dummy channel structure is formed on the dummy channel structure of the at least part of the dummy memory string.

21. The three-dimensional nonvolatile memory according to claim 20, wherein the at least part of the dummy memory strings are electrically connected to each other via a connection line through the connection portion.

22. The three-dimensional nonvolatile memory according to claim 16,

wherein the plurality of sub-switch units correspond to the plurality of storage areas, respectively,

wherein each of the plurality of sub-switch units includes a plurality of sub-switches electrically connected to the at least some of the dummy memory strings located in the distal end region in the corresponding memory region, respectively, which are electrically connected to each other.