CN112908230A

CN112908230A - Display panel and display device

Info

Publication number: CN112908230A
Application number: CN202110202764.9A
Authority: CN
Inventors: 谢正芳; 许传志
Original assignee: Kunshan New Flat Panel Display Technology Center Co Ltd
Current assignee: Kunshan New Flat Panel Display Technology Center Co Ltd
Priority date: 2021-02-23
Filing date: 2021-02-23
Publication date: 2021-06-04
Anticipated expiration: 2041-02-23
Also published as: CN112908230B

Abstract

The application provides a display panel and display device relates to and shows technical field. The display panel includes a display region, a wiring pad region, and a fan-out region. The display area comprises N × M sub-pixel units which form M pixel unit sequences, the M pixel unit sequences are divided into a plurality of pixel unit sequence groups, and each pixel unit sequence group comprises a first pixel unit sequence, a second pixel unit sequence, a third pixel unit sequence and a fourth pixel unit sequence. The fan-out lines in the fan-out area are connected with the pixel unit sequences and the wiring pads in the wiring pad area, the M fan-out lines are alternately arranged in the two layers of layered structures along the second direction, and for two adjacent fan-out lines in the same layered structure, one fan-out line is connected with the first pixel unit sequence or the third pixel unit sequence, and the other fan-out line is connected with the second pixel unit sequence or the fourth pixel unit sequence. Based on the method, the problem that the short circuit of the fan-out wire is difficult to effectively detect in the prior art can be solved.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel and display equipment.

Background

In the production process of the display panel, short circuit of a fanout line (fanoutline) in a fanout area belongs to a common problem, on one hand, yield of equipment production can be directly influenced, and on the other hand, material waste of subsequent processes can be caused. Therefore, the short circuit of the fan-out line needs to be detected so as to timely perform repair processing when the short circuit occurs. However, the inventors have found that it is difficult to effectively detect the short-circuit problem of the fan-out line in the conventional art.

Disclosure of Invention

In view of the above, an object of the present application is to provide a display panel and a display device to solve the problem in the prior art that it is difficult to effectively detect a short circuit of a fan-out line.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

a display panel, comprising:

a display region, wherein the display region includes N × M sub-pixel units, the N × M sub-pixel units form M pixel unit sequences, each pixel unit sequence extends along a first direction, the M pixel unit sequences are arranged along a second direction different from the first direction, the M pixel unit sequences are divided into a plurality of pixel unit sequence groups, each pixel unit sequence group includes a first pixel unit sequence, a second pixel unit sequence, a third pixel unit sequence and a fourth pixel unit sequence which are sequentially arranged, and in each pixel unit sequence group, after the sub-pixel units are lighted, any two adjacent pixel unit sequences display different colors;

a routing pad region including M routing pads disposed corresponding to the M pixel cell sequences;

the fan-out region, this fan-out region include M fan-out lines, and each fan-out line connects the corresponding setting respectively the pixel cell sequence with wiring pad, wherein:

the M fan-out lines are alternately arranged in two layers of insulating and isolating layered structures along the second direction, and for two adjacent fan-out lines in the same layered structure, one fan-out line of the two fan-out lines is connected with the first pixel unit sequence or the third pixel unit sequence, and the other fan-out line of the two fan-out lines is connected with the second pixel unit sequence or the fourth pixel unit sequence.

In a preferred option of the embodiment of the present application, in the display panel, the M fan-out lines include a plurality of fan-out line groups arranged corresponding to the plurality of pixel unit sequence groups;

each fan-out line group comprises a first fan-out line, a second fan-out line, a third fan-out line and a fourth fan-out line which are alternately arranged in the two-layer layered structure along the second direction, the first fan-out line, the second fan-out line, the third fan-out line and the fourth fan-out line are connected with a first pixel unit sequence, a second pixel unit sequence, a third pixel unit sequence and a fourth pixel unit sequence which are correspondingly arranged, and the first fan-out line, the second fan-out line, the third fan-out line and the fourth fan-out line which are arranged in the fan-out line group are arranged in the same mode.

In a preferred option of the embodiment of the present application, in the display panel, the layered structure includes a first layered structure and a second layered structure, the first fan-out line and the third fan-out line are disposed in the first layered structure, and the second fan-out line and the fourth fan-out line are disposed in the second layered structure;

the first fan-out line is connected with the first pixel unit sequence, the second fan-out line is connected with the third pixel unit sequence, the third fan-out line is connected with the second pixel unit sequence, and the fourth fan-out line is connected with the fourth pixel unit sequence.

In a preferred option of the embodiment of the present application, in the display panel, one end of each of the second fanout lines, which is close to the display area, is connected to the third pixel unit sequence through a first transition line, the first transition line is disposed in a third layer structure, and the first transition line extends along the second direction;

one end of each second fanout line, which is close to the wiring pad area, is connected with the wiring pad corresponding to the third pixel unit sequence through a second transition line, the second transition line is arranged on the third layer structure, and the second transition line extends along the second direction;

one end of each third fanout line, which is close to the display area, is connected with the second pixel unit sequence through a third transition line, the third transition line is arranged on the first layered structure, and the third transition line extends along the second direction;

and one end of each third fanout line, which is close to the wiring pad area, is connected with the wiring pad corresponding to the second pixel unit sequence through a fourth transition line, the fourth transition line is arranged in the first layered structure, and the fourth transition line extends along the second direction.

the first fan-out line is connected with the second pixel unit sequence, the second fan-out line is connected with the first pixel unit sequence, the third fan-out line is connected with the third pixel unit sequence, and the fourth fan-out line is connected with the fourth pixel unit sequence.

In a preferred option of the embodiment of the present application, in the display panel, one end of each of the first fanout lines, which is close to the display area, is connected to the second pixel unit sequence through a fifth transition line, the fifth transition line is disposed in a third layer structure, and the fifth transition line extends along the second direction;

one end of each first fanout line, which is close to the wiring pad area, is connected with the wiring pad corresponding to the second pixel unit sequence through a sixth transition line, the sixth transition line is arranged on the third layer structure, and the sixth transition line extends along the second direction;

one end of each second fanout line, which is close to the display area, is connected with the first pixel unit sequence through a seventh transition line, the seventh transition line is arranged on the second layered structure, and the seventh transition line extends along the second direction;

one end of each second fanout line, which is close to the wiring pad area, is connected with the wiring pad corresponding to the first pixel unit sequence through an eighth transition line, the eighth transition line is arranged in the second layered structure, and the eighth transition line extends along the second direction.

the first fan-out line is connected with the first pixel unit sequence, the second fan-out line is connected with the second pixel unit sequence, the third fan-out line is connected with the fourth pixel unit sequence, and the fourth fan-out line is connected with the third pixel unit sequence.

In a preferred option of the embodiment of the present application, in the display panel, one end of each of the third fanout lines, which is close to the display area, is connected to the fourth pixel unit sequence through a ninth transition line, the ninth transition line is disposed in a third layer structure, and the ninth transition line extends along the second direction;

one end of each third fanout line, which is close to the wiring pad area, is connected with the wiring pad corresponding to the fourth pixel unit sequence through a tenth transition line, the tenth transition line is arranged on the third layer structure, and the tenth transition line extends along the second direction;

one end of each fourth fanout line, which is close to the display area, is connected with the third pixel unit sequence through an eleventh transition line, the eleventh transition line is arranged on the second layered structure, and the eleventh transition line extends along the second direction;

one end of each fourth fanout line, which is close to the wiring pad area, is connected with the wiring pad corresponding to the third pixel unit sequence through a twelfth transition line, the twelfth transition line is arranged on the second layer structure, and the twelfth transition line extends along the second direction.

the first fan-out line is connected with the fourth pixel unit sequence, the second fan-out line is connected with the second pixel unit sequence, the third fan-out line is connected with the third pixel unit sequence, and the fourth fan-out line is connected with the first pixel unit sequence.

In a preferred option of the embodiment of the present application, in the display panel, one end of each of the first fanout lines, which is close to the display area, is connected to the fourth pixel unit sequence through a thirteenth transition line, the thirteenth transition line is disposed in a third layer structure, and the thirteenth transition line extends along the second direction;

one end of each first fanout line, which is close to the wiring pad area, is connected with the wiring pad corresponding to the fourth pixel unit sequence through a fourteenth transition line, the fourteenth transition line is arranged on the third layer structure, and the fourteenth transition line extends along the second direction;

one end of each fourth fanout line, which is close to the display area, is connected with the first pixel unit sequence through a fifteenth transition line, wherein a staggered part of the fifteenth transition line and the thirteenth transition line is arranged in the second layered structure, a non-staggered part of the fifteenth transition line and the thirteenth transition line is arranged in the third layered structure, and the fifteenth transition line extends along the second direction;

one end of each fourth fanout line, which is close to the wiring pad area, is connected with the wiring pad corresponding to the first pixel unit sequence through a sixteenth transition line, wherein a staggered part of the sixteenth transition line and the fourteenth transition line is arranged in the second layered structure, a non-staggered part of the sixteenth transition line and the fourteenth transition line is arranged in the third layered structure, and the sixteenth transition line extends along the second direction.

On the basis of the above embodiments, embodiments of the present application further provide a display device, including the above display panel.

In the display panel and the display device provided by the application, M fan-out lines included in the fan-out area are alternately arranged in an insulated and isolated two-layer laminated structure along a second direction, and for two adjacent fan-out lines in the same laminated structure, one fan-out line of the two fan-out lines is connected with a first pixel unit sequence or a third pixel unit sequence, and the other fan-out line is connected with a second pixel unit sequence or a fourth pixel unit sequence, on the basis, because in each pixel unit sequence group, sub-pixel units in any two adjacent pixel unit sequences display different colors after being lightened, when two adjacent fan-out lines in the same laminated structure are short-circuited, the display panel can display different colors than when the two adjacent fan-out lines are not short-circuited, so that the short-circuit problem of the fan-out lines can be effectively and conveniently detected, and the problem that the short-circuit of the fan-out lines is difficult to effectively detect in the prior art is solved, in addition, the problem that the frame (non-display area) of the display panel needs to occupy a large area due to the arrangement of a large number of detection circuits can be solved, and the method has high practical value.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application.

Fig. 2 is a schematic structural diagram of a pixel unit sequence group according to an embodiment of the present disclosure.

Fig. 3 is a schematic plane layout view of a fan-out line according to an embodiment of the present application.

Fig. 4 is a schematic perspective view of a fan-out line according to an embodiment of the present application.

Fig. 5 is a schematic perspective view of a fan-out line according to an embodiment of the present application.

Fig. 6 is a schematic connection diagram of a fan-out line and a pixel unit sequence according to an embodiment of the present disclosure.

Fig. 7 is a second schematic diagram illustrating connection between a fan-out line and a pixel unit sequence according to an embodiment of the present application.

Fig. 8 is a third schematic view illustrating connection between a fan-out line and a pixel unit sequence according to the present embodiment.

Fig. 9 is a fourth schematic view illustrating connection between a fan-out line and a pixel unit sequence according to an embodiment of the present application.

Fig. 10 is a schematic diagram illustrating an effect of the staggered wiring between the second fan-out line and the third fan-out line in fig. 6.

Fig. 11 is a schematic diagram illustrating an effect of the staggered wiring between the first fan-out line and the second fan-out line in fig. 7.

Fig. 12 is a schematic diagram illustrating an effect of the staggered wiring between the third fan-out line and the fourth fan-out line in fig. 8.

Fig. 13 is a schematic diagram illustrating an effect of the staggered wiring between the first fanout line and the fourth fanout line in fig. 9.

Icon: 100-a display panel; 110-a display area; 111-pixel element sequence group; 130-routing pad area; 131-a wiring pad; 150-a fan-out region; 151-fanout line; l1 — first fanout line; l2 — second fanout line; l3-third fan-out line; l4-fourth fanout line; g1 — first transition line; g2 — second transition line; g3 — third transition line; g4 — fourth transition line; g5-fifth transition line; g6-sixth transition line; g7-seventh transition line; g8 — eighth transition line; g9-ninth transition line; g10-tenth transition line; g11 — eleventh transition line; g12 — twelfth transition line; g13-thirteenth transition line; g14-fourteenth transition line; g15-fifteenth transition line; g16-sixteenth transition line.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

As shown in fig. 1, an embodiment of the present application provides a display panel 100. The display panel 100 may include a display region 110, a routing pad region 130, and a fan-out region 150, among others.

In detail, the display region 110 may include N × M sub-pixel units, the N × M sub-pixel units may form M pixel unit sequences, each pixel unit sequence extends along a first direction, and each pixel unit sequence may include N sub-pixel units. The M pixel unit sequences are arranged along a second direction different from the first direction, and are divided into a plurality of pixel unit sequence groups 111, and each pixel unit sequence group 111 includes a first pixel unit sequence, a second pixel unit sequence, a third pixel unit sequence, and a fourth pixel unit sequence, which are arranged in sequence. In each pixel unit sequence group 111, after the sub-pixel units are lit, any two adjacent pixel unit sequences display different colors. The routing pad region 130 may include M routing pads 131, and the M routing pads 131 are disposed corresponding to the M pixel cell sequences.

The fan-out region 150 may include M fan-out lines 151, and each fan-out line 151 is connected to the pixel unit sequence and the wiring pad 131. And, the M fan-out lines 151 are alternately arranged in an insulating and isolating two-layer layered structure along a direction different from the second direction (for example, a solid line and a dotted line corresponding to the fan-out line 151 of the fan-out region 150 in fig. 1, respectively indicate that the M fan-out lines 151 are located in different layered structures). For two adjacent fanout lines 151 in the same layer structure, one fanout line 151 of the two fanout lines 151 is connected to the first pixel unit sequence or the third pixel unit sequence, and the other fanout line 151 is connected to the second pixel unit sequence or the fourth pixel unit sequence.

Based on the above arrangement, when two adjacent fan-out lines 151 in the same layer structure are short-circuited, the display panel 100 may display a color different from that when the fan-out lines 151 are not short-circuited, so that the short-circuit problem of the fan-out lines 151 can be effectively and conveniently detected based on the displayed color, thereby improving the problem that the short-circuit of the fan-out lines 151 is difficult to effectively detect in the prior art, and also improving the problem that a frame (non-display area) of the display panel 100 needs to occupy a larger area due to the arrangement of more detection circuits.

In the first aspect, it should be noted that, for the display area 110, a specific number of sub-pixel units included in the display area 110 is not limited, and may be selected according to a practical application requirement.

For example, in an alternative example, the number of sub-pixel cells may be 1024 × 768. That is, 768 lines of pixel unit series extending in the first direction, 1024 lines of pixel unit series extending in the second direction may be formed; alternatively, 1024 lines of pixel unit sequences extending in the first direction and 768 lines of pixel unit sequences extending in the second direction may be formed.

For another example, in another alternative example, the number of sub-pixel cells may be 1280 by 1024. That is, 1024 pieces of the pixel unit sequence extending in the first direction and 1280 pieces of the pixel unit sequence extending in the second direction may be formed; alternatively, 1280 lines of pixel unit sequences extending along the first direction and 1024 lines of pixel unit sequences extending along the second direction may be formed.

Based on the above example, it should be further noted that, for the display area 110, in order to enable any two adjacent pixel unit sequences to display different colors after being lit, the sub-pixel units in the pixel unit sequences may be arranged correspondingly according to the actual application requirement.

For example, in each pixel unit sequence group 111, one of any two adjacent pixel unit sequences may be formed based on the first color sub-pixel unit and the second color sub-pixel unit, and the other may be formed based on the third color sub-pixel unit. It can be understood that the first color sub-unit, the second color sub-unit and the third color sub-unit can display different colors after being lighted up, and the specific color configurations of the first color sub-pixel unit, the second color sub-pixel unit and the third color sub-pixel unit are not limited and can be selected according to the practical application requirements.

For example, in an alternative example, the first color sub-pixel unit and the second color sub-pixel unit may be a red sub-pixel unit and a blue sub-pixel unit, respectively, and the third color sub-pixel unit may be a green sub-pixel unit (where, for convenience of description, in the following example, this example may be based on). It can be understood that, in other examples, other corresponding relationships between the first color sub-pixel unit, the second color sub-pixel unit, and the third color sub-pixel unit and the red sub-pixel unit, the blue sub-pixel unit, and the green sub-pixel unit may also be possible, and the first color sub-pixel unit, the second color sub-pixel unit, and the third color sub-pixel unit may be configured according to display requirements, and are not described herein again.

In detail, in a specific application example, the first pixel unit sequence and the third pixel unit sequence are formed based on that N red sub-pixel units and blue sub-pixel units are alternately arranged, and the alternate arrangement manner of the red sub-pixel units and the blue sub-pixel units in the first pixel unit sequence and the third pixel unit sequence is different. The second pixel unit sequence and the fourth pixel unit sequence are formed based on N green sub-pixel unit arrangements.

Based on the method, for any adjacent two paths of pixel unit sequences, one path is formed by alternately arranging red sub-pixel units and blue sub-pixel units, and the other path is formed by arranging green sub-pixel units.

Optionally, on the basis of the above example, the alternating arrangement manner of the red sub-pixel units and the blue sub-pixel units in the first pixel unit sequence and the third pixel unit sequence is not limited, and may be selected according to the actual application requirement.

For example, in an alternative example, in conjunction with fig. 2, in the first pixel unit sequence, the sub-pixel unit corresponding to the odd-numbered position may be a red sub-pixel unit, and the sub-pixel unit corresponding to the even-numbered position may be a blue sub-pixel unit, so that the red sub-pixel unit and the blue sub-pixel unit may be alternately arranged in the first pixel unit sequence. In the third pixel unit sequence, the sub-pixel units corresponding to odd-numbered positions may be blue sub-pixel units, and the sub-pixel units corresponding to even-numbered positions may be red sub-pixel units, so that the blue sub-pixel units and the red sub-pixel units may be alternately arranged in the third pixel unit sequence.

For another example, in another alternative example, in the first pixel unit sequence, the sub-pixel unit at the position corresponding to the odd number may be a blue sub-pixel unit, and the sub-pixel unit at the position corresponding to the even number may be a red sub-pixel unit, so that the blue sub-pixel unit and the red sub-pixel unit may be alternately arranged in the first pixel unit sequence. In the third pixel unit sequence, the sub-pixel units corresponding to odd-numbered positions may be red sub-pixel units, and the sub-pixel units corresponding to even-numbered positions may be blue sub-pixel units, so that the red sub-pixel units and the blue sub-pixel units may be alternately arranged in the third pixel unit sequence.

On the basis of the above example, it should be further explained for the display area 110 that the specific directions of the first direction and the second direction are not limited.

For example, in normal use of the display panel 100, in an alternative example, the first direction may refer to a column direction of the sub-pixel units, and the second direction may refer to a row direction of the sub-pixel units. In another alternative example, the first direction may refer to a row direction of the sub-pixel units, and the second direction may refer to a row direction of the sub-pixel units.

It is to be understood that, in the above example, the pixel unit sequence extending along the first direction may refer to N sub-pixel units included in each of the M pixel unit sequences, and the N sub-pixel units are sequentially arranged along the first direction. In this way, the M pixel unit sequences may be sequentially arranged along the second direction.

When the first direction is a column direction and the second direction is a row direction, 4 sub-pixel units belonging to the first pixel unit sequence, the second pixel unit sequence, the third pixel unit sequence, and the fourth pixel unit sequence in the same row and belonging to the same pixel unit sequence group 111 may constitute one pixel unit. Thus, a pixel unit may include a blue sub-pixel unit, a red sub-pixel unit and two green sub-pixel units, and the two green sub-pixel units may be separated by the blue sub-pixel unit and the red sub-pixel unit.

In the second aspect, it should be noted that, for the routing pad region 130, the number of routing pads 131 included in the routing pad region 130 is not limited.

For example, in an alternative example, the number of pixel unit sequences extending along the first direction may be 1024, and correspondingly, the number of the routing pads 131 may be 1024, and thus, the routing pads 131 may form a one-to-one correspondence relationship with the pixel unit sequences, so that a control signal, such as a data signal, may be transmitted to the pixel unit sequence corresponding to each routing pad 131 in the 1024 pixel unit sequences through each routing pad 131 in the 1024 routing pads 131.

For another example, in another alternative example, the number of the pixel unit sequences extending along the first direction may be 1280, and correspondingly, the number of the routing pads 131 may be 1280, and thus, the routing pads 131 may form a one-to-one correspondence relationship with the pixel unit sequences, so that a control signal, such as a data signal, may be transmitted to the pixel unit sequence corresponding to each routing pad 131 in the 1280 pixel unit sequences through each routing pad 131 in the 1280 routing pads 131.

It is to be understood that the M routing pads 131 may be divided into a plurality of routing pad groups, and the plurality of routing pad groups may be in one-to-one correspondence with the plurality of pixel unit sequence groups 111. Wherein each routing pad group may include 4 routing pads 131, which are a first routing pad, a second routing pad, a third routing pad, and a fourth routing pad, respectively. The first routing pad, the second routing pad, the third routing pad, and the fourth routing pad included in each routing pad group may be sequentially arranged along the second direction to transmit the control signal to the first pixel cell sequence, the second pixel cell sequence, the third pixel cell sequence, and the fourth pixel cell sequence, respectively, in the corresponding pixel cell sequence group 111.

Based on this, for one wiring pad group and one pixel cell sequence group 111 that are correspondingly arranged, the first wiring pad in the wiring pad group may be used to transmit the control signal to the first pixel cell sequence in the pixel cell sequence group 111, the second wiring pad in the wiring pad group may be used to transmit the control signal to the second pixel cell sequence in the pixel cell sequence group 111, the third wiring pad in the wiring pad group may be used to transmit the control signal to the third pixel cell sequence in the pixel cell sequence group 111, and the fourth wiring pad in the wiring pad group may be used to transmit the control signal to the fourth pixel cell sequence in the pixel cell sequence group 111.

The control signal transmitted by the wiring pad 131 may be from a driving circuit connected to the display panel 100. The driving circuit may be integrated in a circuit board, which may be attached to the wiring pad 131 through a conductive film, and a lead on the circuit board may be electrically connected to the wiring pad 131, thereby realizing transmission of a control signal. The Circuit Board may be a Flexible Printed Circuit Board (FPCB), a Printed Circuit Board (PCB), or a Flexible Film such as a Chip On Film (COF).

In the third aspect, it should be noted that, for the fan-out region 150, the position of the fan-out region 150 on the display panel 100 is not limited, and may be selected according to the actual application requirements.

For example, in an alternative example, the fan-out region 150 may be located between the display region 110 and the wiring pad region 130 (please refer to fig. 1), so that when the wiring pad 131 in the wiring pad region 130 is connected to the pixel unit sequence in the display region 110 through the fan-out lines 151 in the fan-out region 150, the arrangement of the fan-out lines 151 may be simpler and simpler, and the problem of complicated wiring process due to complicated wiring of the fan-out lines 151 (for example, more interleaving needs to be performed between different fan-out lines 151, and the fan-out lines 151 have more meandering extension) is avoided, on one hand, the problem of easy short circuit may be improved, and on the other hand, the manufacturing efficiency and the manufacturing cost of the display panel 100 may be improved.

On the basis of the above example, it should be further explained for the fan-out area 150 that the number of the fan-out lines 151 included in the fan-out area 150 is not limited.

For example, in an alternative example, the number of the pixel unit sequences extending along the first direction may be 1024, and correspondingly, the number of the fan-out lines 151 may be 1024, so that the fan-out lines 151 may form a one-to-one correspondence relationship with the pixel unit sequences, so that the wiring pad 131 may transmit a control signal, such as a data signal, to the pixel unit sequence connected to each of the 1024 fan-out lines 151 through each of the 1024 fan-out lines 151.

For another example, in another alternative example, the number of the pixel unit sequences extending along the first direction may be 1280, and correspondingly, the number of the fanout lines 151 may be 1280, so that the fanout lines 151 may form a one-to-one correspondence relationship with the pixel unit sequences, so that the wiring pad 131 respectively transmits a control signal, such as a data signal, to the pixel unit sequence corresponding to each fanout line 151 in the 1280 pixel unit sequences through each fanout line 151 in the 1280 fanout lines 151.

It is understood that the number of the fanout lines 151 may also be different from the number of the pixel unit sequences, for example, the number of the fanout lines 151 may be more than the number of the pixel unit sequences as a spare.

It is to be understood that, on the basis of the above example, the M fan-out lines 151 may form a plurality of fan-out line groups, that is, the M fan-out lines 151 include a plurality of fan-out line groups. The plurality of fan-out line groups may be arranged corresponding to the plurality of pixel unit sequence groups 111, so that a one-to-one correspondence relationship between the fan-out line groups and the pixel line groups may be formed.

Also, referring to fig. 3, each of the fan-out line groups may include a first fanout line L1, a second fanout line L2, a third fanout line L3, and a fourth fanout line L4 alternately arranged in the two-layered structure in sequence along the second direction. The first fanout line L1, the second fanout line L2, the third fanout line L3, and the fourth fanout line L4 are respectively connected to the first pixel unit sequence, the second pixel unit sequence, the third pixel unit sequence, and the fourth pixel unit sequence included in the pixel unit sequence group 111.

On the basis of the above example, it should be further explained for the fan-out region 150 that, in a plurality of fan-out line groups included in the fan-out region 150, whether the setting manners of the fan-out lines 151 included in each of the fan-out line groups are the same or not is not limited, and the setting manners may be selected according to actual application requirements.

For example, in an alternative example, in the plurality of fan-out line groups, each of the fan-out line groups includes a first fan-out line L1, a second fan-out line L2, a third fan-out line L3, and a fourth fan-out line L4, which are arranged differently, and may be adaptively adjusted in accordance with a specific arrangement position, or the like.

For another example, in another alternative example, in the plurality of fan-out line groups, the first fan-out line L1, the second fan-out line L2, the third fan-out line L3, and the fourth fan-out line L4 included in each fan-out line group may be arranged in the same manner, so that the wiring process may be more concise.

Alternatively, on the basis of the above example, a specific manner in which the 4 fan-out lines 151 included in the fan-out line group are sequentially and alternately arranged in the two-layer layered structure is not limited.

In detail, the two-layer layered structure may include a first layered structure and a second layered structure, and the first layered structure and the second layered structure may be disposed in an insulating isolation, e.g., at least one insulating film layer may be disposed between the first layered structure and the second layered structure.

Based on this, in an alternative example, referring to fig. 4, the first and third fanout lines L1 and L3 may be disposed in the first layered structure, and the second and fourth fanout lines L2 and L4 may be disposed in the second layered structure. As such, the adjacent fanout lines 151 may be respectively located in different layered structures, for example, assuming that a plurality of fanout lines arranged in sequence are included in total, the 2N-1 (e.g., odd) fanout lines may be located in the first layered structure, and the 2N fanout lines are located in the second layered structure.

In another alternative example, referring to fig. 5, the first fanout line L1 and the third fanout line L3 may be disposed in the second layered structure, and the second fanout line L2 and the fourth fanout line L4 may be disposed in the first layered structure. As such, the adjacent fanout lines 151 may be respectively located in different layered structures, for example, assuming that a plurality of fanout lines arranged in sequence are included in total, the 2N-1 (e.g., odd) fanout lines may be located in the second layered structure, and the 2N fanout lines are located in the first layered structure.

Alternatively, on the basis of the above example, the specific connection correspondence relationship between the 4 fan-out lines 151 included in the fan-out line group and the 4 pixel unit sequences included in the pixel unit sequence group 111 is not limited.

In order to explain a specific connection correspondence relationship between the 4 fan-out lines 151 included in the fan-out line group and the 4 pixel unit sequences included in the pixel unit sequence group 111, in the present embodiment, the following 4 examples are provided respectively to satisfy a wiring requirement of "for two adjacent fan-out lines 151 in the same layer structure, one fan-out line 151 of the two fan-out lines 151 is connected to the first pixel unit sequence or the third pixel unit sequence, and the other fan-out line 151 is connected to the second pixel unit sequence or the fourth pixel unit sequence".

The above-mentioned 4 examples are explained based on the "the first and third fanout lines L1 and L3 are provided in the first layered structure, the second and fourth fanout lines L2 and L4 are provided in the second layered structure", and the color sub-cell arrangement shown in fig. 2, and the specific contents are as follows.

In a first example, referring to fig. 6, the first fan-out line L1 may be connected to the first pixel cell series, the second fan-out line L2 may be connected to the third pixel cell series, the third fan-out line L3 may be connected to the second pixel cell series, and the fourth fan-out line L4 may be connected to the fourth pixel cell series.

Based on this, if the first fan-out line L1 and the third fan-out line L3 are short-circuited in the same layer of the layered structure, a short circuit may be caused between the first pixel cell sequence and the second pixel cell sequence. In this way, since the first pixel unit sequence and the second pixel unit sequence are respectively composed of the red-blue mixed color sub-pixel unit and the green sub-pixel unit, that is, belong to pixel unit sequences of different colors, so that different colors can be presented when short circuit and short circuit do not occur, whether a short circuit condition exists between the first fan-out line L1 and the third fan-out line L3 can be detected based on the displayed colors.

Similarly, if the second fanout line L2 and the fourth fanout line L4 are shorted in the same layer of the layered structure, the third pixel unit sequence and the fourth pixel unit sequence may be shorted. In this way, since the third pixel unit sequence and the fourth pixel unit sequence are respectively composed of the red-blue mixed color sub-pixel unit and the green sub-pixel unit, that is, belong to pixel unit sequences of different colors, different colors can be presented when short circuit and short circuit do not occur, and therefore, whether a short circuit condition exists between the first fan-out line L1 and the third fan-out line L3 can be detected based on the displayed colors.

As a comparative example, it is assumed that the first fanning-out line L1 is connected to the first pixel cell sequence, the second fanning-out line L2 is connected to the second pixel cell sequence, the third fanning-out line L3 is connected to the third pixel cell sequence, and the fourth fanning-out line L4 is connected to the fourth pixel cell sequence.

Based on this, if the first fan-out line L1 and the third fan-out line L3 are short-circuited in the same layer of the layered structure, a short circuit may be caused between the first pixel unit sequence and the third pixel unit sequence. In this way, since the first pixel unit sequence and the third pixel unit sequence are both composed of red and blue mixed-color sub-pixel units, that is, belong to the same color pixel unit sequence, so that the same color is presented when short-circuited and when not short-circuited, it is difficult to detect whether there is a short-circuit condition between the first fan-out line L1 and the third fan-out line L3 based on the displayed color.

Similarly, if the second fanout line L2 and the fourth fanout line L4 are shorted in the same layer of the layered structure, the second pixel unit sequence and the fourth pixel unit sequence may be shorted. In this manner, since the second pixel cell line and the fourth pixel cell line are both composed of green sub-pixel cells, i.e., pixel cell lines of the same color, so that the same color is presented when short-circuited and when not short-circuited, it is difficult to detect whether a short-circuit condition exists between the second fanning-out line L2 and the fourth fanning-out line L4 based on the displayed color.

In a second example, referring to fig. 7, the first fanout line L1 may be connected to the second pixel cell series, the second fanout line L2 may be connected to the first pixel cell series, the third fanout line L3 may be connected to the third pixel cell series, and the fourth fanout line L4 may be connected to the fourth pixel cell series.

Based on this, if the first fan-out line L1 and the third fan-out line L3 are short-circuited in the same layer of the layered structure, a short circuit may be caused between the second pixel cell sequence and the third pixel cell sequence. In this way, since the second pixel unit sequence and the third pixel unit sequence are respectively composed of the green sub-pixel unit and the red-blue mixed sub-pixel unit, that is, belong to pixel unit sequences of different colors, so that different colors can be presented when short circuit and short circuit do not occur, whether a short circuit condition exists between the first fan-out line L1 and the third fan-out line L3 can be detected based on the displayed colors.

Similarly, if the second fanout line L2 and the fourth fanout line L4 are shorted in the same layer of the layered structure, the first pixel unit sequence and the fourth pixel unit sequence may be shorted. In this way, since the first pixel unit sequence and the fourth pixel unit sequence are respectively composed of the red-blue mixed color sub-pixel unit and the green sub-pixel unit, that is, belong to pixel unit sequences of different colors, so that different colors can be presented when short circuit and short circuit do not occur, whether a short circuit condition exists between the first fan-out line L1 and the third fan-out line L3 can be detected based on the displayed colors.

In a third example, referring to fig. 8, the first fanout line L1 may be connected to the first pixel cell series, the second fanout line L2 may be connected to the second pixel cell series, the third fanout line L3 may be connected to the fourth pixel cell series, and the fourth fanout line L4 may be connected to the third pixel cell series.

Based on this, if the first fan-out line L1 and the third fan-out line L3 are short-circuited in the same layer of the layered structure, a short circuit may be caused between the first pixel unit sequence and the fourth pixel unit sequence. In this way, since the first pixel unit sequence and the fourth pixel unit sequence are respectively composed of the red-blue mixed color sub-pixel unit and the green sub-pixel unit, that is, belong to pixel unit sequences of different colors, so that different colors can be presented when short circuit and short circuit do not occur, whether a short circuit condition exists between the first fan-out line L1 and the third fan-out line L3 can be detected based on the displayed colors.

Similarly, if the second fanout line L2 and the fourth fanout line L4 are shorted in the same layer of the layered structure, the second pixel unit sequence and the third pixel unit sequence may be shorted. In this way, since the second pixel unit sequence and the third pixel unit sequence are respectively composed of the green sub-pixel unit and the red-blue mixed sub-pixel unit, that is, belong to pixel unit sequences of different colors, so that different colors can be presented when short circuit and short circuit do not occur, whether a short circuit condition exists between the first fan-out line L1 and the third fan-out line L3 can be detected based on the displayed colors.

In a fourth example, referring to fig. 9, the first fanout line L1 may be connected to the fourth pixel cell series, the second fanout line L2 may be connected to the second pixel cell series, the third fanout line L3 may be connected to the third pixel cell series, and the fourth fanout line L4 may be connected to the first pixel cell series.

Based on this, if the first fan-out line L1 and the third fan-out line L3 are short-circuited in the same layer of the layered structure, a short circuit may be caused between the fourth pixel cell sequence and the third pixel cell sequence. In this way, since the fourth pixel unit sequence and the third pixel unit sequence are respectively composed of the green sub-pixel unit and the red-blue mixed sub-pixel unit, that is, the pixel unit sequences with different colors, so that different colors can be presented when short circuit and short circuit do not occur, whether a short circuit condition exists between the first fan-out line L1 and the third fan-out line L3 can be detected based on the displayed colors.

Similarly, if the second fanout line L2 and the fourth fanout line L4 are shorted in the same layer of the layered structure, the second pixel cell sequence and the first pixel cell sequence may be shorted. In this way, since the second pixel unit sequence and the first pixel unit sequence are respectively composed of the green sub-pixel unit and the red-blue mixed sub-pixel unit, that is, the pixel unit sequences with different colors, so that different colors can be presented when short circuit and short circuit do not occur, whether a short circuit condition exists between the first fan-out line L1 and the third fan-out line L3 can be detected based on the displayed colors.

In the above four examples, it can be understood that the staggered wiring is formed between the partial fanout lines 151, for example, in the above first example, the staggered wiring is formed between the second fanout line L2 and the third fanout line L3. In the second example described above, the first fanout line L1 and the second fanout line L2 form a staggered wiring therebetween. In the third example described above, the third fanout line L3 and the fourth fanout line L4 form a staggered wiring therebetween. In the fourth example described above, the first fanout line L1 and the fourth fanout line L4 form a staggered wiring therebetween.

Alternatively, in the first example described above, a specific manner of forming the staggered wiring between the second fanout line L2 and the third fanout line L3 is not limited.

For example, in an alternative example, referring to fig. 10, one end of each of the second fanning-out lines L2 near the display area 110 is connected to the third sequence of pixel units by a first transition line G1, the first transition line G1 is disposed on the third layer structure, and the first transition line G1 extends along the second direction. Each of the second fanout lines L2 is connected to the wiring pad 131 corresponding to the third pixel unit sequence through a second transition line G2 at an end close to the wiring pad region 130, the second transition line G2 is disposed on the third layer structure, and the second transition line G2 extends along the second direction. As such, the first transition line G1 and the second transition line G2 are disposed in different layered structures from the second fanout line L2, respectively.

Each of the third fan-out lines L3, which is close to one end of the display region 110, is connected to the second pixel unit sequence by a third transition line G3, the third transition line G3 is disposed on the first layered structure, and the third transition line G3 extends along the second direction. Each of the third fanout lines L3 is connected to the wiring pad 131 corresponding to the second pixel unit sequence through a fourth transition line G4 at an end close to the wiring pad region 130, the fourth transition line G4 is disposed in the first layered structure, and the fourth transition line G4 extends along the second direction. As such, the third transition line G3 and the fourth transition line G4 are disposed in the same layered structure as the third fanout line L3.

For another example, in another alternative example, the staggered routing manner between the second fanout line L2 and the third fanout line L3 is opposite to that of the above example, that is, the first transition line G1 and the second transition line G2 corresponding to the second fanout line L2 in this example are the same as the third transition line G3 and the fourth transition line G4 corresponding to the third fanout line L3 in the above example, and the third transition line G3 and the fourth transition line G4 corresponding to the third fanout line L3 in this example are the same as the first transition line G1 and the second transition line G2 corresponding to the second fanout line L2 in the above example.

In detail, one end of each of the second fanning-out lines L2, which is close to the display region 110, is connected to the third sequence of pixel units by a first transition line G1, the first transition line G1 is disposed in the second layer structure, and the first transition line G1 extends along the second direction. Each of the second fanout lines L2 is connected to the wiring pad 131 corresponding to the third pixel unit sequence through a second transition line G2 at an end close to the wiring pad region 130, the second transition line G2 is disposed on the third layer structure, and the second transition line G2 extends along the second direction. Each of the third fan-out lines L3, which is close to one end of the display region 110, is connected to the second pixel unit sequence by a third transition line G3, the third transition line G3 is disposed on the third layer structure, and the third transition line G3 extends along the second direction. Each of the third fanout lines L3 is connected to the wiring pad 131 corresponding to the second pixel unit sequence through a fourth transition line G4 at an end close to the wiring pad region 130, the fourth transition line G4 is disposed in the third layer structure, and the fourth transition line G4 extends along the second direction.

Alternatively, in the second example described above, a specific manner of forming the staggered wiring between the first fanout line L1 and the second fanout line L2 is not limited.

For example, in an alternative example, referring to fig. 11, each of the first fanning-out lines L1 near one end of the display area 110 is connected to the second pixel cell sequence by a fifth transition line G5, the fifth transition line G5 is disposed on the third layer structure, and the fifth transition line G5 extends along the second direction. Each of the first fanout lines L1 is connected to the wiring pad 131 corresponding to the second pixel unit sequence through a sixth transition line G6 at an end close to the wiring pad region 130, the sixth transition line G6 is disposed on the third layer structure, and the sixth transition line G6 extends along the second direction.

And, one end of each of the second fanout lines L2, which is close to the display region 110, is connected to the first sequence of pixel units by a seventh transition line G7, the seventh transition line G7 is disposed in the second layer structure, and the seventh transition line G7 extends along the second direction. Each of the second fanout lines L2 is connected to the corresponding wiring pad 131 of the first pixel unit sequence through an eighth transition line G8 at an end close to the wiring pad region 130, the eighth transition line G8 is disposed on the second layer structure, and the eighth transition line G8 extends along the second direction.

For another example, in another alternative example, the staggered routing manner between the first fanout line L1 and the second fanout line L2 may be opposite to the above example, that is, the fifth transition line G5 and the sixth transition line G6 corresponding to the first fanout line L1 in this example are the same as the seventh transition line G7 and the eighth transition line G8 corresponding to the second fanout line L2 in the above example, and the seventh transition line G7 and the eighth transition line G8 corresponding to the second fanout line L2 in this example are the same as the fifth transition line G5 and the sixth transition line G6 corresponding to the first fanout line L1 in the above example. For specific content, reference may be made to the related examples in the foregoing, and details are not repeated here.

Alternatively, in the above-described third example, a specific manner of forming the staggered wiring between the third fanout line L3 and the fourth fanout line L4 is not limited.

For example, in an alternative example, referring to fig. 12, each of the third fan-out lines L3 near one end of the display area 110 is connected to the fourth pixel cell sequence by a ninth transition line G9, the ninth transition line G9 is disposed in the third layered structure, and the ninth transition line G9 extends along the second direction. Each of the third fanout lines L3 is connected to the routing pad 131 corresponding to the fourth pixel unit sequence through a tenth transition line G10 at an end close to the routing pad region 130, the tenth transition line G10 is disposed in the third layer structure, and the tenth transition line G10 extends along the second direction.

And, one end of each of the fourth fanout lines L4, which is close to the display region 110, is connected to the third sequence of pixel units by an eleventh transition line G11, the eleventh transition line G11 is disposed in the second layer structure, and the eleventh transition line G11 extends along the second direction. One end of each of the fourth fanout lines L4, which is close to the wire pad region 130, is connected to the wire pad 131 corresponding to the third pixel unit sequence through a twelfth transition line G12, the twelfth transition line G12 is disposed in the second layer structure, and the twelfth transition line G12 extends along the second direction.

For another example, in another alternative example, the staggered routing manner between the third fan-out line L3 and the fourth fan-out line L4 is opposite to that of the above example, that is, the ninth transition line G9 and the tenth transition line G10 corresponding to the third fan-out line L3 in this example are the same as the eleventh transition line G11 and the twelfth transition line G12 corresponding to the fourth fan-out line L4 in the above example, and the eleventh transition line G11 and the twelfth transition line G12 corresponding to the fourth fan-out line L4 in this example are the same as the ninth transition line G9 and the tenth transition line G10 corresponding to the third fan-out line L3 in the above example. For specific content, reference may be made to the related examples in the foregoing, and details are not repeated here.

Alternatively, in the above fourth example, a specific manner of forming the staggered wiring between the first fanout line L1 and the fourth fanout line L4 is not limited.

For example, in an alternative example, referring to fig. 13, each of the first fanning-out lines L1 near one end of the display region 110 is connected to the fourth pixel cell sequence by a thirteenth transition line G13, the thirteenth transition line G13 is disposed in the third layered structure, and the thirteenth transition line G13 extends along the second direction. Each of the first fanout lines L1 is connected to the corresponding wiring pad 131 of the fourth pixel unit sequence through a fourteenth transition line G14 at an end close to the wiring pad region 130, the fourteenth transition line G14 is disposed on the third layer structure, and the fourteenth transition line G14 extends along the second direction.

Each of the fourth fanout lines L4, which is close to one end of the display region 110, is connected to the first pixel unit sequence by a fifteenth transition line G15, an interlaced portion of the fifteenth transition line G15 and the thirteenth transition line G13 is disposed in the second layer structure, a non-interlaced portion is disposed in the third layer structure, and the fifteenth transition line G15 extends along the second direction. Each of the fourth fanout lines L4 is connected to the routing pad 131 corresponding to the first pixel unit sequence through a sixteenth transition line G16 at an end close to the routing pad region 130, where a staggered portion of the sixteenth transition line G16 and the fourteenth transition line G14 is disposed in the second layer structure, a non-staggered portion is disposed in the third layer structure, and the sixteenth transition line G16 extends along the second direction.

For another example, in another alternative example, the staggered routing manner between the first fanout line L1 and the fourth fanout line L4 may be opposite to the above example, that is, the thirteenth transition line G13 and the fourteenth transition line G14 corresponding to the first fanout line L1 in this example are the same as the fifteenth transition line G15 and the sixteenth transition line G16 corresponding to the fourth fanout line L4 in the above example, and the fifteenth transition line G15 and the sixteenth transition line G16 corresponding to the fourth fanout line L4 in this example are the same as the thirteenth transition line G13 and the fourteenth transition line G14 corresponding to the first fanout line L1 in the above example. In particular, reference may be made to the foregoing, related examples.

It is understood that, in the above examples, for the lines belonging to different layered structures to be connected, such as the fanout line 151 and the transition line, the lines may be connected by a via penetrating through the different layered structures and a conductive material filled in the via. For lines belonging to the same layer structure that need to be connected, they can be directly connected in the same layer structure.

In the above example, the fanout line 151 and the transition line are connected to the pixel cell series may mean that the fanout line 151 and the transition line are connected to the signal line of the pixel cell series. As an alternative example, the signal line may be provided in the third layered structure.

In the above example, the third layered structure may be different from the first layered structure and the second layered structure, and may be disposed in an insulating and isolating manner from the first layered structure and the second layered structure, for example, an insulating film layer may be formed on a side of the second layered structure away from the first layered structure, and the third layered structure may be formed on a side of the insulating film layer away from the second layered structure.

In the above examples, the transition line extending in the second direction may mean that the transition line is parallel to the second direction, or that the transition line is non-perpendicular to the second direction, i.e. has an angle of less than 90 °.

The embodiment of the present application further provides a display device, which may include the display panel 100 and a driving circuit. The display panel 100 may be connected to a driving circuit, for example, a wiring pad included in the display panel 100 may be connected to the driving circuit for obtaining a control signal.

To sum up, in the display panel 100 and the display device provided by the present application, M fan-out lines 151 included in the fan-out region 150 are alternately disposed in the two insulating and isolating layer structures along the second direction, and for two adjacent fan-out lines 151 in the same layer structure, one fan-out line 151 of the two fan-out lines 151 is connected to the first pixel unit sequence or the third pixel unit sequence, and the other fan-out line 151 is connected to the second pixel unit sequence or the fourth pixel unit sequence, on this basis, because in each pixel unit sequence group, sub-pixel units in any two adjacent pixel unit sequences are lighted and then display different colors, when two adjacent fan-out lines 151 in the same layer structure are short-circuited, the display panel 100 will display different colors than when the two adjacent fan-out lines 151 are not short-circuited, so that the short-circuit problem of the fan-out lines 151 can be detected more effectively and conveniently, therefore, the problem that the short circuit of the fanout line 151 is difficult to be effectively detected in the prior art is solved, and the problem that the frame (non-display area) of the display panel 100 needs to occupy a larger area due to the arrangement of more detection circuits is also solved, so that the method has higher practical value.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, comprising:

2. The display panel according to claim 1, wherein the M fan-out lines include a plurality of fan-out line groups provided corresponding to the plurality of pixel cell sequence groups;

3. The display panel according to claim 2, wherein the layered structure includes a first layered structure and a second layered structure, the first and third fanout lines are disposed in the first layered structure, and the second and fourth fanout lines are disposed in the second layered structure;

4. The display panel according to claim 3, wherein one end of each of the second fanout lines, which is close to the display area, is connected to the third sequence of pixel units through a first transition line, the first transition line is disposed on a third layer structure, and the first transition line extends along the second direction;

5. The display panel according to claim 2, wherein the layered structure includes a first layered structure and a second layered structure, the first and third fanout lines are disposed in the first layered structure, and the second and fourth fanout lines are disposed in the second layered structure;

6. The display panel according to claim 5, wherein one end of each of the first fanout lines, which is close to the display area, is connected to the second sequence of pixel units through a fifth transition line, the fifth transition line being disposed on a third layer structure, the fifth transition line extending along the second direction;

7. The display panel according to claim 2, wherein the layered structure includes a first layered structure and a second layered structure, the first and third fanout lines are disposed in the first layered structure, and the second and fourth fanout lines are disposed in the second layered structure;

8. The display panel according to claim 7, wherein one end of each of the third fan-out lines, which is close to the display area, is connected to the fourth sequence of pixel units through a ninth transition line, the ninth transition line being disposed in a third layered structure, the ninth transition line extending along the second direction;

9. The display panel according to claim 2, wherein the layered structure includes a first layered structure and a second layered structure, the first and third fanout lines are disposed in the first layered structure, and the second and fourth fanout lines are disposed in the second layered structure;

10. A display device characterized by comprising the display panel of any one of claims 1 to 9.