CN112906175A - Semiconductor device comprehensive evaluation method oriented to ultra-low power consumption application scene - Google Patents

Semiconductor device comprehensive evaluation method oriented to ultra-low power consumption application scene Download PDF

Info

Publication number
CN112906175A
CN112906175A CN201911225817.8A CN201911225817A CN112906175A CN 112906175 A CN112906175 A CN 112906175A CN 201911225817 A CN201911225817 A CN 201911225817A CN 112906175 A CN112906175 A CN 112906175A
Authority
CN
China
Prior art keywords
power consumption
circuit
frequency
minimum
low power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201911225817.8A
Other languages
Chinese (zh)
Other versions
CN112906175B (en
Inventor
叶乐
王志轩
黄芊芊
王阳元
黄如
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Peking University
Original Assignee
Peking University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Peking University filed Critical Peking University
Priority to CN201911225817.8A priority Critical patent/CN112906175B/en
Publication of CN112906175A publication Critical patent/CN112906175A/en
Application granted granted Critical
Publication of CN112906175B publication Critical patent/CN112906175B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2637—Circuits therefor for testing other individual devices
    • G01R31/2639—Circuits therefor for testing other individual devices for testing field-effect devices, e.g. of MOS-capacitors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
    • G01R31/275—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements for testing individual semiconductor components within integrated circuits

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The invention discloses a comprehensive evaluation method of a semiconductor device for an ultra-low power consumption application scene, which considers the low power consumption capability of the device and the influence of the device on the circuit performance (speed). The method takes the working frequency requirement of a specific circuit as a performance standard to obtain the minimum working voltage of the semiconductor device which just meets the working frequency; by taking the minimum power consumption of the comparison device under the minimum working voltage corresponding to the given working frequency as a power consumption standard, the conclusion that whether the device to be evaluated has the advantage of low power consumption compared with the comparison device can be obtained, and the advantage 'working frequency-working voltage' range of the device to be evaluated can also be obtained.

Description

Semiconductor device comprehensive evaluation method oriented to ultra-low power consumption application scene
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a comprehensive evaluation method for a semiconductor device oriented to an ultra-low power consumption application scene.
Background
In the past decades, the metal-oxide-semiconductor field effect transistor (MOSFET), which is a component of a mainstream chip, has been increasingly powered while its feature size has been continuously reduced in compliance with moore's law and device performance has been continuously improved, and is now a bottleneck limiting further development of semiconductor technology. With the continuous development of semiconductor technology, transistors with other structures, such as fin field effect transistors (finfets), nanowires (nanowires), and novel ultra-low power semiconductor devices based on other physical mechanisms, such as Tunneling Field Effect Transistors (TFETs), nano electromechanical relays (NEM relays), and negative capacitance field effect transistors (NC-FETs), are emerging. The technology of the semiconductor device is advanced with the current technology, and the semiconductor device also has emerging application scenes such as internet of things, implantation type, wearable medical treatment and the like, wherein the application scenes have strict requirements on the power consumption of an integrated circuit chip, and the requirements on the working speed of the chip are far less than the requirements on the power consumption. For these emerging application scenarios, it is necessary to evaluate various existing semiconductor devices to select the device most suitable for the application scenario with ultra-low power consumption, and therefore, a fair and accurate evaluation method is very important.
At present, the Energy efficiency method, namely Energy per Switch, is often used for evaluating a semiconductor device in an ultra-low power consumption application scene in domestic and foreign research to obtain the Energy consumption of a logic unit circuit consisting of the semiconductor device in a logic turning process, and the Energy consumption is used as a standard for judging the low power consumption capability of the semiconductor device, however, the standard ignores a large amount of static power consumption wasted in waiting time in an emerging application scene triggered by random sparse events. In addition, the power consumption delay product method (PDP) used in some domestic and foreign research simply considers that the importance of power consumption and performance is the same, and obviously, it is not suitable for an ultra-low power consumption application scenario in which power consumption is prioritized over speed. Therefore, a new evaluation standard is needed to accurately and fairly evaluate the comprehensive capability of the device in the context of ultra-low power applications.
Disclosure of Invention
Aiming at the problems and challenges in the conventional evaluation method, the invention aims to provide a fair and accurate evaluation method of a semiconductor device under the background of ultra-low power consumption so as to screen out the semiconductor device suitable for the ultra-low power consumption fields of the Internet of things and the like.
The comprehensive evaluation is to consider both the low power consumption capability of the device and the influence of the device on the circuit performance (speed), that is, to evaluate the power consumption and the logic circuit switching speed at the same time.
For the background of ultra-low power consumption, the important degree of power consumption is higher than the performance, so the influence of the semiconductor device on the power consumption of the circuit is considered in the process of comprehensive evaluation, the power consumption is taken as the main standard, and the performance only needs to meet the lowest frequency requirement of the integrated circuit under specific application.
The technical scheme of the invention is as follows:
a comprehensive evaluation method for a semiconductor device oriented to an ultra-low power consumption application scene is disclosed, and referring to FIG. 1, the comprehensive evaluation method comprises the following steps:
1. knowing the working frequency f of the chip circuit under specific application scenes, obtaining the respective minimum working voltage V of the device A to be evaluated and the device B of the comparison group through simulation, experiment or calculationDD,min,AAnd VDD,min,B；
2. According to the minimum operating voltage VDD,min,AAnd VDD,min,BObtaining the power consumption P of the device A and the device B through simulation, experiment or calculationmin,AAnd Pmin,BThey represent the minimum power consumption of the device at this frequency f;
3. judgment of Pmin,AWhether or not less than Pmin,BIf yes, the device A has the advantage of low power consumption compared with the device B under the frequency application, and the step 4 is carried out; on the contrary, the device A has no advantages and the step 5 is carried out;
4. the power consumption is synchronously increased by continuously increasing the working voltage of the device A until the power consumption of the device A is equal to the minimum power consumption of the device B, namely PAIs equal to Pmin,BAt this time, the operating voltage V of the device ADD,max,ANamely the maximum working voltage of the device A which has the advantage of low power consumption compared with the device B under the frequency application;
5. traversing different working frequencies, obtaining a conclusion whether the device A has low power consumption advantage under each frequency according to the methods of the steps 1 to 4, and if the device A has the advantage under certain frequencies, further obtaining a corresponding advantageous working voltage range V defined by a minimum working voltage and a maximum working voltageDD,min,A～VDD,max,AThe advantageous "frequency-operating voltage" range of device A compared to device B, i.e. "f-V", is finally obtainedDD,min,A～VDD,max,A”。
In the step 1, the minimum operating voltage of the device at the specific operating frequency can be calculated according to the formula (1):
Figure BDA0002302177540000021
knowing the operating frequency f of the circuit, the delay τ of the circuit is requiredcircuitMust not exceed
Figure BDA0002302177540000022
The LD in formula (1) represents the logic depth of the circuit, i.e., the number of logic gates included in the longest logic link in the circuit; cLA load capacitance that is a logic gate; i iseffThe effective current for charging and discharging the load capacitor for the logic gate is determined by the characteristics of the semiconductor device; vDD,minIs the minimum operating voltage to be required.
The minimum working voltage of the device under a specific working frequency can also be obtained by a circuit simulation-based method through SPICE software.
In the step 2, the power consumption of the device under the minimum operating voltage can be calculated according to the formula (2):
Figure BDA0002302177540000023
p in formula (2)circuitPower consumption is to be solved; n is the total number of logic gates contained in the circuit; α is the activity factor of the circuit, i.e. the average probability of each logic gate flipping; i isleakFor static leakage of each logic gateFlow, which is determined by the semiconductor device characteristics.
The power consumption of the device under the minimum working voltage can also be obtained by a circuit simulation-based method through SPICE software.
Compared with the traditional evaluation method, the comprehensive evaluation method for the semiconductor device facing the ultra-low power consumption application scene not only considers the low power consumption capability of the device, but also considers the influence of the device on the circuit performance. The method takes the working frequency requirement of a specific circuit as a performance standard to obtain the minimum working voltage of the semiconductor device which just meets the working frequency; and taking the minimum power consumption of the comparison device under the minimum working voltage corresponding to the given working frequency as a power consumption standard to obtain a conclusion whether the device to be evaluated has the advantage of low power consumption compared with the comparison device, and obtaining an advantage working voltage range of the power consumption of the device to be evaluated which is less than or equal to the power consumption standard. In summary, the evaluation method provided by the invention can not only obtain the conclusion that whether the device to be evaluated has the advantage of low power consumption compared with the comparison device, but also further obtain the advantage of the device to be evaluated, namely the range of the working frequency-the working voltage.
Drawings
Fig. 1 is a schematic flow chart of a comprehensive evaluation method for a semiconductor device oriented to an ultra-low power consumption application scenario in the present invention.
Fig. 2 is a schematic diagram of the current-voltage characteristics of the MOSFET of the device under evaluation and the MOSFET of the comparison device in the embodiment of the present invention.
Fig. 3 is an evaluation result of a TFET of a device to be evaluated according to an embodiment of the present invention, where: (a) power consumption of devices TFET and MOSFET obtained by simulation under the frequency of 1MHz under each power supply voltage; (b) power consumption of devices TFET and MOSFET obtained by simulation under frequency of 10MHz under each power supply voltage, (c) operating frequency and minimum operating voltage V of circuit composed of devices TFET and MOSFET obtained by simulationDD,min(d) minimum operating voltage V at each frequency at which the device TFET has a low power consumption advantageDD,minAnd a maximum operating voltage VDD,maxAnd (5) a relational graph.
Detailed Description
The technical solutions of the present invention are further clearly and completely described below with reference to the accompanying drawings by way of embodiments, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
The performance of the semiconductor device TFET is evaluated by circuit simulation with the device TFET as the device to be evaluated and the device MOSFET as the reference device, and the current-voltage characteristics of the two devices are shown in fig. 2. The larger the current of a semiconductor device, the faster the speed of the circuit formed by the semiconductor device, and the higher the operable frequency of the circuit formed by the semiconductor device, and conversely, the lower the supply voltage required by the circuit given the operating frequency requirement, which means that the device has higher current and better performance. Simulating the working Frequency (Frequency) and the minimum working voltage V of a circuit consisting of the TFET and the MOSFET respectivelyDD,minThe relationship (c) is shown in FIG. 3 (c).
Taking the frequency of 1MHz and 10MHz as an example, the power consumption of the two devices under each power supply voltage is simulated (fig. 3(a), (b)).
When the frequency is 1MHz, the minimum working voltage of TFET is 0.34V, the minimum working voltage of MOSFET is 0.25V, corresponding to the respective minimum power consumption Pmin,TFETAnd Pmin，MOSAs can be seen from fig. 3(a), the minimum power consumption of the TFET is smaller than that of the MOSFET, so the TFET has the advantage of low power consumption at this frequency, and it can be seen from the figure that when V isDDAt 0.73V, the power consumption of the TFET is equal to the minimum power consumption P of the MOSFETmin，MOSThis V isDDNamely the maximum operating voltage V of the TFET with the advantage of low power consumptionDD,max。
When the frequency is 10MHz, it can be seen from fig. 3(b) that the minimum power consumption of the TFET is greater than that of the MOSFET, i.e., the TFET does not have the advantage of low power consumption at this frequency.
According to the method, the conclusion that whether the TFET has the advantage of low power consumption under each frequency can be obtained, and if the TFET has the advantage, the corresponding maximum working voltage can be further obtained. Minimum operation at various frequencies with advantage of low power consumption for TFETVoltage VDD,minAnd a maximum operating voltage VDD,maxPlotted together, as shown in fig. 3(d), the intersection of the two curves is the maximum operating frequency f at which the TFET has an advantage*The shaded portion is the low power consumption advantageous "operating frequency-operating voltage" range of the TFET.
For the application background of ultra-low power consumption, the method provided by the invention takes the condition of meeting the circuit speed requirement as a performance standard, takes the lowest power consumption of a device used for comparison in a circuit as a power consumption standard, and carries out comprehensive evaluation on the semiconductor device, thereby not only obtaining the conclusion whether the semiconductor device to be evaluated has the advantage of low power consumption compared with the comparison device, but also obtaining the range of working frequency-working voltage with the advantage of low power consumption.
It is noted that the disclosed embodiments are intended to aid in further understanding of the invention, but those skilled in the art will appreciate that: various substitutions and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the embodiments disclosed, but the scope of the invention is defined by the appended claims.

Claims (5)

1. A comprehensive evaluation method for a semiconductor device oriented to an ultra-low power consumption application scene comprises the following steps:
1) knowing the working frequency f of the chip circuit under specific application scenes, obtaining the respective minimum working voltage V of the device A to be evaluated and the device B of the comparison group through simulation, experiment or calculationDD,min,AAnd VDD,min,B；
2) According to the minimum operating voltage VDD,min,AAnd VDD,min,BObtaining the power consumption P of the device A and the device B through simulation, experiment or calculationmin,AAnd Pmin,BThey represent the minimum power consumption of the device at this frequency f;
3) judgment of Pmin,AWhether or not less than Pmin,BIf yes, the device A has the advantage of low power consumption compared with the device B under the frequency application, and the step 4) is carried out; otherwise, the device A has no advantages, and the step 5) is carried out;
4) the power consumption is synchronously increased by continuously increasing the working voltage of the device A until the power consumption of the device A is equal to the minimum power consumption of the device B, namely PAIs equal to Pmin,BAt this time, the operating voltage V of the device ADD,max,ANamely the maximum working voltage of the device A which has the advantage of low power consumption compared with the device B under the frequency application;
5) traversing different working frequencies, obtaining a conclusion whether the device A has low power consumption advantage under each frequency according to the steps 1) to 4), and further obtaining a corresponding advantageous working voltage range V defined by a minimum working voltage and a maximum working voltage if the device A has advantages under certain frequenciesDD,min,A～VDD,max,AThe advantageous "frequency-operating voltage" range of device A compared to device B, i.e. "f-V", is finally obtainedDD,min,A～VDD,max,A”。
2. The method of claim 1, wherein step 1) calculates the minimum operating voltage of the device at a particular operating frequency according to equation (1):
Figure FDA0002302177530000011
knowing the operating frequency f of the circuit, the delay τ of the circuit is requiredcircuitMust not exceed
Figure FDA0002302177530000012
The LD in formula (1) represents the logic depth of the circuit, i.e., the number of logic gates included in the longest logic link in the circuit; cLA load capacitance that is a logic gate; i iseffThe effective current for charging and discharging the load capacitor for the logic gate is determined by the characteristics of the semiconductor device; vDD,minIs the minimum operating voltage to be required.
3. The method of claim 1, wherein step 1) obtains the minimum operating voltage of the device at a specific operating frequency by a circuit simulation-based method through SPICE software.
4. The method of claim 1, wherein step 2) calculates the power consumption of the device at the minimum operating voltage according to equation (2):
Figure FDA0002302177530000013
p in formula (2)circuitPower consumption is to be solved; n is the total number of logic gates contained in the circuit; α is the activity factor of the circuit, i.e. the average probability of each logic gate flipping; i isleakWhich is the static leakage current of each logic gate, is determined by the semiconductor device characteristics.
5. The method of claim 1, wherein step 2) derives the power consumption of the device at the minimum operating voltage by a circuit simulation-based method of SPICE software.
CN201911225817.8A 2019-12-04 2019-12-04 Comprehensive evaluation method for semiconductor device oriented to ultra-low power consumption application scene Active CN112906175B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911225817.8A CN112906175B (en) 2019-12-04 2019-12-04 Comprehensive evaluation method for semiconductor device oriented to ultra-low power consumption application scene

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911225817.8A CN112906175B (en) 2019-12-04 2019-12-04 Comprehensive evaluation method for semiconductor device oriented to ultra-low power consumption application scene

Publications (2)

Publication Number Publication Date
CN112906175A true CN112906175A (en) 2021-06-04
CN112906175B CN112906175B (en) 2022-05-20

Family

ID=76104351

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911225817.8A Active CN112906175B (en) 2019-12-04 2019-12-04 Comprehensive evaluation method for semiconductor device oriented to ultra-low power consumption application scene

Country Status (1)

Country Link
CN (1) CN112906175B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115390610A (en) * 2022-08-22 2022-11-25 哲库科技(北京)有限公司 Power utilization system, frequency control method, chip and storage medium

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080104552A1 (en) * 2006-10-31 2008-05-01 Jun Yamada Power consumption optimizing method for semiconductor integrated circuit and semiconductor designing apparatus
CN102314525A (en) * 2010-06-30 2012-01-11 中国科学院微电子研究所 Low-power-consumption circuit design optimization method
US20140312932A1 (en) * 2013-04-19 2014-10-23 Semiconductor Energy Laboratory Co., Ltd. Storage device and semiconductor device
CN104122493A (en) * 2014-07-25 2014-10-29 北京大学 Method for evaluating working voltage of semiconductor device service life
CN109948173A (en) * 2019-01-04 2019-06-28 上海亿算科技有限公司 A kind of chip system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080104552A1 (en) * 2006-10-31 2008-05-01 Jun Yamada Power consumption optimizing method for semiconductor integrated circuit and semiconductor designing apparatus
CN102314525A (en) * 2010-06-30 2012-01-11 中国科学院微电子研究所 Low-power-consumption circuit design optimization method
US20140312932A1 (en) * 2013-04-19 2014-10-23 Semiconductor Energy Laboratory Co., Ltd. Storage device and semiconductor device
CN104122493A (en) * 2014-07-25 2014-10-29 北京大学 Method for evaluating working voltage of semiconductor device service life
CN109948173A (en) * 2019-01-04 2019-06-28 上海亿算科技有限公司 A kind of chip system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115390610A (en) * 2022-08-22 2022-11-25 哲库科技(北京)有限公司 Power utilization system, frequency control method, chip and storage medium

Also Published As

Publication number Publication date
CN112906175B (en) 2022-05-20

Similar Documents

Publication Publication Date Title
Avci et al. Energy efficiency comparison of nanowire heterojunction TFET and Si MOSFET at L g= 13nm, including P-TFET and variation considerations
Kim et al. A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations
Abbas et al. Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells
Nikoubin Hybrid logical effort for hybrid logic style full adders in multistage structures
Asenov et al. Nanowire transistor solutions for 5nm and beyond
CN105897254B (en) A kind of exclusive or gate logic and its implementation method based on memristor and metal-oxide-semiconductor
CN102082561A (en) SOI (silicon on insulator) clock double-edge static D type trigger
CN112906175B (en) Comprehensive evaluation method for semiconductor device oriented to ultra-low power consumption application scene
CN106385250A (en) FinFET (Fin Field-Effect Transistor) split gate structure complementary symmetric logic-based Inclusive OR-exclusive OR circuit
US20030200071A1 (en) Simulation method
Mushtaq et al. Performance analysis for reliable nanoscaled FinFET logic circuits
Vijay et al. Design and Performance Evaluation of Energy Efficient 8-Bit ALU at Ultra-Low Supply Voltages Using FinFET with 20 nm Technology
Wang et al. Design technology co-optimization for 3 nm gate-all-around nanosheet FETs
Dadoria et al. A novel approach for leakage power reduction techniques in 65nm technologies
Dadoria et al. A novel approach for leakage power reduction in deep submicron technologies in CMOS VLSI circuits
CN203911880U (en) D flip flop controlled by substrate
Vo et al. Dual-switch power gating revisited for small sleep energy loss and fast wake-up time in sub-45-nm nodes
CN102571071B (en) Single electron transistor (SET)/metal oxide semiconductor (MOS) mixed structure multiplier unit based on threshold logic
Tripathi et al. Performance evaluation of low power carry save adder for vlsi applications
Gao et al. A LUT-based model of tri-input TFET
Ryu et al. Transistor layout optimization for leakage saving
Gupta et al. MOSFET sub-threshold current reduction by varying substrate doping
Kundu et al. A 10 nm FINFET and its application
Su et al. Design of digital standard cell based on silicon tunnel field-effect transistor
Zhong et al. Current degradation and delay analysis of series-connected circuits based on novel TFET design

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant