CN112905507B - Hard disk conversion controller - Google Patents

Hard disk conversion controller Download PDF

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Publication number
CN112905507B
CN112905507B CN202110295457.XA CN202110295457A CN112905507B CN 112905507 B CN112905507 B CN 112905507B CN 202110295457 A CN202110295457 A CN 202110295457A CN 112905507 B CN112905507 B CN 112905507B
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module
interface
hard disk
connection module
controller
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CN112905507A (en
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刘海銮
沈叶江
张廷锴
成晓雄
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Sage Microelectronics Corp
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Sage Microelectronics Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2035—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant without idle spare hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2046—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share persistent storage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Hardware Redundancy (AREA)
  • Bus Control (AREA)

Abstract

The embodiment of the invention provides a hard disk conversion controller, which comprises the following components: the controller chip comprises a first connection module, a second connection module, a third connection module, a memory module and a processor; the first connecting module and the second connecting module are pcieh modules connected with the first interface, the third connecting module is pcieh modules connected with the second interface, and the first connecting module, the second connecting module and the third connecting module are respectively connected with the memory module and the processor. By the embodiment of the application, the common hard disk is converted into the hard disk with the dual-activity function, and the high reliability and the transmission efficiency of data transmission are improved.

Description

Hard disk conversion controller
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a hard disk conversion controller.
Background
At present, the main stream interface of a common solid state disk is M.2. The m.2 interface can support both high-speed serial computer expansion bus standard (peripheral component interconnect express, PCI-E) channels and serial advanced technology attachment (Serial Advanced Technology Attachment, SATA), where the former is easier in terms of speed improvement, theoretical bandwidth of 10Gbps, which can be said to break through the theoretical transmission bottleneck of SATA interfaces. The current M.2 interface is comprehensively turned to a PCI-E3.0x4 channel, the theoretical bandwidth reaches 32Gbps, and the current level is greatly improved compared with the current level, so that the performance potential of a Solid State Disk (SSD) is greatly improved. In addition, the interface solid state disk also supports a Non-volatile memory system (Non-Volatile Memory Host Controller Interface Specification, NVMe) standard, and compared with the existing advanced host controller interface (Advanced Host Controller Interface, AHCI), the SSD accessed by the new NVMe standard is quite obvious in performance improvement.
With the popularity of the current large data transmission, the reliability of the data transmission is increasingly important. The traditional hard disk adopting the M.2 interface cannot realize the continuity of data transmission after the data transmission is interrupted, and directly influences the efficiency of the data transmission.
Disclosure of Invention
The embodiment of the invention aims to provide a hard disk conversion controller so as to solve the problem that the continuity of data transmission cannot be realized and the efficiency of the data transmission is directly affected after the data transmission of a traditional hard disk is interrupted.
In a first aspect, an embodiment of the present invention provides a hard disk conversion controller, including:
the controller comprises a controller chip, a first interface and a second interface, wherein the first interface is used for connecting at least two hosts, the second interface is used for connecting a hard disk, and the controller chip comprises a first connection module, a second connection module, a third connection module, a memory module and a processor; the first connecting module and the second connecting module are pcieh modules connected with the first interface, the third connecting module is pcieh modules connected with the second interface, and the first connecting module, the second connecting module and the third connecting module are respectively connected with the memory module and the processor.
As can be seen from the technical solution provided by the above embodiment of the present invention, in the embodiment of the present invention, a first interface and a second interface are provided at two ends of a conversion controller, where the first interface is used to connect at least two hosts, and the second interface is used to connect to a hard disk, and a controller chip includes a first connection module, a second connection module, a third connection module, a memory module and a processor; the first connecting module and the second connecting module are pcieh modules connected with the first interface, the third connecting module is pcieh modules connected with the second interface, and the first connecting module, the second connecting module and the third connecting module are respectively connected with the memory module and the processor. By the embodiment of the application, the common hard disk is converted into the hard disk with the dual-activity function, and the high reliability and the transmission efficiency of data transmission are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a hard disk conversion controller according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a hard disk conversion system according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another structure of a hard disk conversion system according to an embodiment of the present invention;
fig. 4 is a schematic diagram of another structure of a hard disk conversion system according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a hard disk conversion controller.
In order to make the technical solution of the present invention better understood by those skilled in the art, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, shall fall within the scope of the invention.
A small computer system interface (Small Computer System Interface, SCSI) device is the first device to implement dual active functions using two physical connections. With the advent of Serial Attached SCSI (SAS), it has become possible to implement dual port connection through one physical connection. This technique can provide fault tolerance for either data path, since dual ports allow independent transmission of data from both ports.
Along with the rapid development of the NVMe SSD technology, the application of the U.2 dual-activity technology in an enterprise-level storage system becomes necessary, and the method has wider prospect and market due to the advantages of the method in high performance and high reliability.
U.2 interface technology allows two host systems to access the same storage system simultaneously using dual ports. If a system failure or power loss occurs when one data path is lost, the available data path will continue to operate with no impact on traffic continuity and minimal impact on QoS. However, the U.2 interface hard disk is too expensive, and the main stream hard disk still adopts an m.2 hard disk.
As shown in fig. 1, an embodiment of the present invention provides a hard disk conversion controller 100, which includes:
the controller comprises a controller chip 101, a first interface 102 and a second interface 103, wherein the first interface 102 is used for connecting at least two hosts, the second interface 103 is used for connecting a hard disk, and the controller chip 101 comprises a first connection module 1011, a second connection module 1012, a third connection module 1013, a memory module 1014 and a processor 1015; the first connection module 1011 and the second connection module 1012 are pcieh modules connected to the first interface 102, the third connection module 1013 is a pcieh module connected to the second interface 103, and the first connection module 1011, the second connection module 1012 and the third connection module 1013 are respectively connected to the memory module 1014 and the processor 1015.
Further, the first interface 102 is a U.2 interface, and may specifically be a U.2 golden finger interface. Two hosts can be connected simultaneously through the U.2 interface, so that two host systems are allowed to access the hard disk connected by the second interface 103 simultaneously, and the loss of a data path caused by system failure of a single host is avoided.
Further, the second interface 103 is an m.2 interface, an SAS interface, or a SATA interface. The second interface 103 may be used to connect an m.2 hard disk, a SATA hard disk, an SAS hard disk, and the like, respectively, according to the types of interfaces.
Further, the first connection module 1011 and the second connection module 1012 are a two-channel pciedx module (pciedx 2) and a four-channel pciedx module (pciedx 4), respectively. Two module substrates are connected to the first interface.
Further, the third connection module 1013 is a four-channel pcieh module (pciehx 4).
Because there is a data conversion between the interfaces at both ends, a data channel needs to be established between the first connection module 1011, the second connection module 1012, and the third connection module 1013, which in this embodiment is built by the memory module 1014 and the processor (CPU) 1015. The memory module 1014 may be a static random access memory (Static Random Access Memory, SRAM). The data and command parsing conversion between the connection modules of the interfaces at both ends is operated by firmware (fw). In particular, it is to be understood that the controller is driven. When a hard disk is connected to a host through the switching controller 100, a host-side drive is required, and a firmware drive is also required. Both ends are consistent, and data storage can be performed after mutual authentication. The host side is driven in the host system, and the firmware is driven in the hard disk.
Because the pcie module uses a high-speed interface, the data channel needs to be connected by a high-speed bus. Further, the first connection module 1011, the second connection module 1012 and the third connection module 1013 are all connected with the memory module by using an AXI4 bus to ensure high-speed data transmission.
As can be seen from the technical solution provided by the above embodiment of the present invention, in the embodiment of the present invention, a first interface and a second interface are provided at two ends of a conversion controller, where the first interface is used to connect at least two hosts, and the second interface is used to connect to a hard disk, and a controller chip includes a first connection module, a second connection module, a third connection module, a memory module and a processor; the first connecting module and the second connecting module are pcieh modules connected with the first interface, the third connecting module is pcieh modules connected with the second interface, and the first connecting module, the second connecting module and the third connecting module are respectively connected with the memory module and the processor. By the embodiment of the application, the common hard disk is converted into the hard disk with the dual-activity function, and the high reliability and the transmission efficiency of data transmission are improved.
Based on the above embodiments, when a common hard disk is connected through the conversion controller of the embodiment of the present application, the hard disk may implement at least the following functions.
In one embodiment, as shown in fig. 2, in the case that two hosts connected to the first interface 102 access at the same time, the first connection module 1011 and the second connection module 1012 are opened at the same time, wherein the second connection module 1012 opens two channels. Specifically, in the case that the U.2 interface is simultaneously connected to the first host 104 and the second host 105, and the m.2 interface is connected to the hard disk 106, the second connection module 1012pciedx4 opens two channels therein, and connects the first connection module 1011pciedx2 with the two first hosts 104 and the second host 105 respectively. The processor analyzes the data command, and the integrated command is sent to the third connection module 1013pciehx4. Thereby realizing the performance of the two ends pcie 4 channel (lane).
In another embodiment, as shown in fig. 3, when one end of two hosts connected to the first interface 1011 fails, that is, the first host 104 fails, the pcied module connected to the second host 105 may still work normally, so as to ensure that the data link is connected continuously. In this case, the host side can only use a single 2-lane.
In another embodiment, as shown in fig. 4, in the case of connecting to a host with the first interface 102, a four-channel second connection module 1012 is turned on. Since the first interface 102 is connected to only one host, i.e. the first host 104, the first host is connected to the second connection module 1012pciedx4. Therefore, the performance of the host end is unchanged, and the high-speed operation of the pcie 4lane is maintained.
The technical scheme provided by the embodiment of the invention can realize multiple functions including double functions according to actual needs by the conversion controller, so that the flexibility of the hard disk in use is improved.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, the electronic device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
It will be apparent to those skilled in the art that embodiments of the present application may be provided as a method, apparatus, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and changes may be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. which are within the spirit and principles of the present application are intended to be included within the scope of the claims of the present application.

Claims (8)

1. A hard disk conversion controller, the conversion controller comprising:
the controller comprises a controller chip, a first interface and a second interface, wherein the first interface is used for connecting two hosts, the second interface is used for connecting a hard disk, and the controller chip comprises a first connection module, a second connection module, a third connection module, a memory module and a processor; the first connecting module and the second connecting module are pcieh modules connected with the first interface, the third connecting module is pcieh modules connected with the second interface, and the first connecting module, the second connecting module and the third connecting module are respectively connected with the memory module and the processor;
the first connecting module and the second connecting module are respectively a two-channel PC (personal communication interface) module and a four-channel PC;
when one of the hosts fails, the pcied module connected with the other host works normally;
the host is internally provided with a host end driver, and the hard disk is internally provided with a firmware driver.
2. The conversion controller of claim 1, wherein the first interface is a U.2 interface.
3. The conversion controller of claim 1, wherein the second interface is an m.2 interface, a SAS interface, or a SATA interface.
4. The conversion controller according to claim 1, wherein the third connection module is a four-channel pmieh module.
5. The conversion controller according to claim 1, wherein in case of simultaneous access of two hosts connected to the first interface, a first connection module and a second connection module are opened simultaneously, wherein the second connection module opens two channels.
6. The switch controller of claim 1, wherein a four-channel second connection module is turned on when a host is connected to the first interface.
7. The switch controller of claim 1, wherein the first connection module, the second connection module, and the third connection module are each coupled to the memory module using an AXI4 bus.
8. The switch controller of claim 1, wherein the memory module is a static random access memory.
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Citations (2)

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CN107943730A (en) * 2017-12-06 2018-04-20 郑州云海信息技术有限公司 A kind of system for supporting NVMe agreement PCIE signals

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