CN112905055A

CN112905055A - Display substrate, manufacturing method thereof and display device

Info

Publication number: CN112905055A
Application number: CN202110265127.6A
Authority: CN
Inventors: 颜俊
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-03-11
Filing date: 2021-03-11
Publication date: 2021-06-04
Also published as: US11782547B2; US20230161428A1; WO2022188413A1

Abstract

The disclosure provides a display substrate, a manufacturing method thereof and a display device. The display substrate includes: a substrate base plate including a first region and a second region; a plurality of sub-pixels, at least one of the plurality of sub-pixels including: a light-emitting element including a first electrode, a light-emitting layer, and a second electrode; a plurality of first power lines electrically connected to the first electrodes; the first power bus is electrically connected with the plurality of first power lines; a second power line electrically connected to the second electrode and including a first portion and a second portion, a gap being present between the second portion of the second power line and the first power bus line; a first insulating layer covering the first power bus line, the second power line, and the gap; a conductive layer on the first insulating layer, an orthographic projection of the conductive layer on the substrate base at least partially overlapping an orthographic projection of the gap on the substrate base; and the touch electrode wires comprise first wires and second wires, and the first wires and the conducting layer are positioned in the same layer and isolated from the conducting layer.

Description

Display substrate, manufacturing method thereof and display device

Technical Field

The disclosure relates to the field of display technologies, and in particular, to a display substrate, a manufacturing method thereof, and a display device.

Background

With the rapid development of AMOLED (Active Matrix Organic Light Emitting Diode), the development of smart terminals such as mobile phones has entered the era of full-screen and narrow-frame. In order to bring a better use experience to users, the characteristics of a full-screen, a narrow frame, high resolution, curling, wearing and/or folding and the like must become an important development direction of future AMOLEDs.

In the related art, in order to make the display panel lighter and thinner to accommodate the later folding and rolling products, a touch technology has been developed. For example, the touch technology may be fmloc (flexible Multi Layer On cell) technology. In the FMLOC technology, touch electrodes are fabricated on an encapsulation layer.

Disclosure of Invention

The inventors of the present disclosure found that, in the related art, signal interference may occur between the touch electrode line and the data line or the GOA signal line, resulting in poor display.

In view of this, embodiments of the present disclosure provide a display substrate to reduce signal interference.

According to an aspect of an embodiment of the present disclosure, there is provided a display substrate including: a substrate base plate including a first region and a second region surrounding the first region, the first region including a first boundary, a second boundary, a third boundary, and a fourth boundary; a plurality of sub-pixels located in the first region, at least one of the plurality of sub-pixels including: a light emitting element including a first electrode on the substrate base, a light emitting layer on a side of the first electrode away from the substrate base, and a second electrode on a side of the light emitting layer away from the substrate base; a plurality of first power lines in the first region and electrically connected to the first electrodes of the plurality of sub-pixels; the first power bus is positioned in a second area on one side, far away from the first area, of the first boundary, and the first power bus is electrically connected with the plurality of first power lines; a second power supply line located in the second region and electrically connected to the second electrode, the second power supply line including a first portion and a second portion, the first portion surrounding the second boundary, the third boundary, and the fourth boundary of the first region, the second portion being located on a side of the first power supply bus line away from the first region, wherein a gap exists between the second portion of the second power supply line and the first power supply bus line; a first insulating layer covering the first power bus line, the second power supply line, and the gap; a conductive layer on a side of the first insulating layer remote from the gap, the conductive layer configured to receive a fixed signal, an orthographic projection of the conductive layer on the substrate base at least partially overlapping an orthographic projection of the gap on the substrate base; and the touch control electrode wires are positioned in the second area, the touch control electrode wires comprise first wires on the first insulating layer and second wires on one side of the first wires, which is far away from the substrate base plate, the first wires and the second wires are separated by a second insulating layer, the first wires are electrically connected with the second wires through conductive vias penetrating through the second insulating layer, the first wires and the conductive layer are positioned in the same layer and are separated from the conductive layer, and the orthographic projection of the second wires on the substrate base plate is at least partially overlapped with the orthographic projection of the conductive layer on the substrate base plate.

In some embodiments, the material of the conductive layer is the same as the material of the first conductive line.

In some embodiments, the plurality of touch electrode lines includes a plurality of first touch electrode lines and a plurality of second touch electrode lines, the first touch electrode lines surrounding a portion of the first boundary, the second boundary, and the third boundary; the second touch electrode line surrounds the other portion of the first boundary and the fourth boundary.

In some embodiments, the first touch electrode line is a signal transmission line, and the second touch electrode line is a signal reception line.

In some embodiments, the display substrate further comprises: the first touch electrode block and the second touch electrode block are located in the first area, wherein the first touch electrode block is electrically connected with the first touch electrode wire, the second touch electrode block is electrically connected with the second touch electrode wire, the first touch electrode block and the second touch electrode block are located in the same layer as the second wire, or the first touch electrode block and the second touch electrode block are located in the same layer as the first wire.

In some embodiments, the display substrate further comprises: a flexible circuit board electrically connected with the conductive layer, the flexible circuit board configured to provide the fixed signal to the conductive layer.

In some embodiments, the fixed signal is a ground signal.

In some embodiments, an orthographic projection of the gap on the substrate base is located inward of an orthographic projection of the conductive layer on the substrate base.

In some embodiments, the gap has a width extending in a direction perpendicular to the first boundary in a range of 40 to 60 microns; the conductive layer has a width extending in a direction perpendicular to the first boundary in a range of 50 to 70 micrometers.

In some embodiments, the display substrate further comprises: a bending region between the conductive layer and the flexible circuit board; wherein the conductive layer is connected to the flexible circuit board via a fixed signal line passing through the bending region.

In some embodiments, the conductive layer is in the same layer as the fixed signal line, and the material of the conductive layer is the same as the material of the fixed signal line.

In some embodiments, the second portion includes a first sub-portion and a second sub-portion, the first and second sub-portions being spaced apart and disposed opposite each other, the first sub-portion being proximate to the second boundary, the second sub-portion being proximate to the fourth boundary; a first gap exists between the first sub-portion and the first power bus bar, a second gap exists between the second sub-portion and the first power bus bar, and an orthographic projection of at least one of the first gap and the second gap on the substrate base at least partially overlaps with an orthographic projection of the conductive layer on the substrate base.

In some embodiments, the first power bus is configured to receive a first voltage signal; the second power line is configured to receive a second voltage signal; wherein the first voltage signal is higher than the second voltage signal.

In some embodiments, the first insulating layer comprises: a planarization layer covering the first power bus line and the second power supply line; a pixel defining layer on the planarization layer; an encapsulation layer on a side of the pixel defining layer remote from the planarization layer; and a barrier layer on a side of the encapsulation layer remote from the pixel defining layer.

In some embodiments, the display substrate further comprises: the third insulating layer covers the substrate base plate; wherein the first power bus and the second power line are located on one side of the third insulating layer away from the substrate base plate.

In some embodiments, the display substrate further comprises: a plurality of first signal lines and a plurality of second signal lines embedded in the third insulating layer, wherein orthographic projections of the plurality of first signal lines on the substrate base plate and orthographic projections of the plurality of second signal lines on the substrate base plate are alternately arranged.

According to another aspect of the embodiments of the present disclosure, there is provided a display device including: a display substrate as hereinbefore described.

According to another aspect of the embodiments of the present disclosure, there is provided a method of manufacturing a display substrate, including: providing a substrate base plate, wherein the substrate base plate comprises a first area and a second area surrounding the first area, and the first area comprises a first boundary, a second boundary, a third boundary and a fourth boundary; forming a plurality of sub-pixels located in the first region, at least one of the plurality of sub-pixels including: a light emitting element including a first electrode on the substrate base, a light emitting layer on a side of the first electrode away from the substrate base, and a second electrode on a side of the light emitting layer away from the substrate base; forming a plurality of first power lines in the first region, the plurality of first power lines being electrically connected to the first electrodes of the plurality of sub-pixels; forming a first power bus of a second area on one side of the first boundary, which is far away from the first area, wherein the first power bus is electrically connected with the plurality of first power lines; forming a second power supply line that is located in the second region and electrically connected to the second electrode, the second power supply line including a first portion and a second portion, the first portion surrounding the second boundary, the third boundary, and the fourth boundary of the first region, the second portion being located on a side of the first power supply bus line away from the first region, wherein a gap exists between the second portion of the second power supply line and the first power supply bus line; forming a first insulating layer covering the first power bus line, the second power supply line, and the gap; a conductive layer formed on a side of the first insulating layer away from the gap, the conductive layer configured to receive a fixed signal, an orthographic projection of the conductive layer on the substrate base at least partially overlapping an orthographic projection of the gap on the substrate base; and forming a plurality of touch electrode lines in the second area, wherein the touch electrode lines comprise first lead wires on the first insulating layer and second lead wires on one side of the first lead wires far away from the substrate base plate, the first lead wires and the second lead wires are separated by a second insulating layer, and the first lead wires are electrically connected with the second lead wires through conductive vias penetrating through the second insulating layer; the first conducting wire and the conducting layer are in the same layer and are separated from the conducting layer, the first conducting wire and the conducting layer are formed through the same composition process, and the orthographic projection of the second conducting wire on the substrate is at least partially overlapped with the orthographic projection of the conducting layer on the substrate.

In the above display substrate, the base substrate includes a first region and a second region surrounding the first region. A plurality of sub-pixels are located in the first region, each sub-pixel including a light emitting element including a first electrode, a light emitting layer, and a second electrode. The plurality of first power lines are electrically connected with the first electrodes of the plurality of sub-pixels. The first power bus is electrically connected with a plurality of first power lines. The second power line is electrically connected to the second electrode. The second power line includes a first portion and a second portion. The first portion surrounds a second boundary, a third boundary, and a fourth boundary of the first region. The second portion is located on a side of the first power bus away from the first region. A gap exists between the second portion of the second power line and the first power bus. The first insulating layer covers the first power bus line, the second power line, and the gap. The conducting layer is arranged on one side of the first insulating layer far away from the gap. The conductive layer is configured to receive a fixed signal. The orthographic projection of the conducting layer on the substrate base plate is at least partially overlapped with the orthographic projection of the gap on the substrate base plate. The touch electrode lines are located in the second area. The touch electrode line comprises a first lead on the first insulating layer and a second lead on one side of the first lead, which is far away from the substrate base plate. The first conductive line is spaced apart from the second conductive line by a second insulating layer, and the first conductive line is electrically connected to the second conductive line through a conductive via passing through the second insulating layer. The first conductive line is in the same layer as the conductive layer and is isolated from the conductive layer. The orthographic projection of the second lead on the substrate base plate is at least partially overlapped with the orthographic projection of the conductive layer on the substrate base plate. The conductive layer can play a role in signal shielding, so that signal interference between the signal line above the gap and the signal line below the gap can be reduced, and the display effect of the display substrate can be improved.

Other features of the present disclosure and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:

fig. 1 is a top view illustrating a display substrate according to one embodiment of the present disclosure;

fig. 2 is an enlarged schematic view illustrating a partial structure within the first dotted frame 141 in fig. 1, which omits a conductive layer and a second wire of a touch electrode line;

fig. 3 is an enlarged schematic view illustrating a partial structure of a display substrate within a first dotted frame 141 in fig. 1, the partial structure omitting a second wire of a touch electrode line, according to an embodiment of the present disclosure;

fig. 4 is an enlarged schematic view illustrating a partial structure of a display substrate within a first dotted frame 141 in fig. 1 according to an embodiment of the present disclosure;

FIG. 5 is a schematic cross-sectional view showing a structure taken along line B-B' in FIG. 4;

FIG. 6 is a schematic cross-sectional view showing a structure taken along line C-C' in FIG. 4;

fig. 7 is a plan view illustrating a partial structure of a display substrate according to another embodiment of the present disclosure;

fig. 8 is an enlarged schematic view showing a partial structure within the second dashed-line box 142 in fig. 1;

FIG. 9 is a schematic cross-sectional view showing a structure taken along line D-D' in FIG. 8;

FIG. 10 is a schematic cross-sectional view showing a structure taken along line A-A' in FIG. 1;

fig. 11 is a flowchart illustrating a method of manufacturing a display substrate according to one embodiment of the present disclosure.

It should be understood that the dimensions of the various parts shown in the figures are not drawn to scale. Further, the same or similar reference numerals denote the same or similar components.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the disclosure, its application, or uses. The present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that: the relative arrangement of parts and steps, the composition of materials, numerical expressions and numerical values set forth in these embodiments are to be construed as merely illustrative, and not as limitative, unless specifically stated otherwise.

The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element preceding the word covers the element listed after the word, and does not exclude the possibility that other elements are also covered. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In the present disclosure, when a specific device is described as being located between a first device and a second device, there may or may not be intervening devices between the specific device and the first device or the second device. When a particular device is described as being coupled to other devices, that particular device may be directly coupled to the other devices without intervening devices or may be directly coupled to the other devices with intervening devices.

All terms (including technical or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs unless specifically defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In the related art, a gap exists between the power voltage line and the common connection line at a corner region of the display substrate. A portion of the touch electrode line is located above the gap, and other signal lines (e.g., data lines and/or GOA (Gate Driver on Array, i.e., Gate Driver on Array) signal lines) are located below the gap. Therefore, signal interference may occur between the Touch electrode lines and the data lines or the GOA signal lines, resulting in poor display or poor Touch (Touch).

In view of this, embodiments of the present disclosure provide a display substrate to reduce signal interference. The structure of a display substrate according to one embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

Fig. 1 is a top view illustrating a display substrate according to one embodiment of the present disclosure. Fig. 4 is an enlarged schematic view illustrating a partial structure of a display substrate within the first dashed box 141 in fig. 1 according to an embodiment of the present disclosure. Fig. 5 is a schematic sectional view showing a structure taken along a line B-B' in fig. 4. Fig. 8 is an enlarged schematic view showing a partial structure within the second dashed-line box 142 in fig. 1. Fig. 9 is a schematic sectional view showing a structure taken along a line D-D' in fig. 8.

As shown in fig. 1, 8 and 9, the display substrate includes a substrate 100, a plurality of sub-pixels 200, a plurality of first power lines 311, a first power bus 310 and a second power line 320.

The substrate base plate 100 includes a first region 110 and a second region 120 surrounding the first region 110. For example, the first region 110 is used to form a display region, and the second region 120 is a peripheral region. The first region 110 includes a first boundary 111, a second boundary 112, a third boundary 113, and a fourth boundary 114. Here, the first boundary 111 is opposite to the third boundary 113, and the second boundary 112 is opposite to the fourth boundary 114.

The plurality of sub-pixels 200 are located in the first region 110. At least one of the plurality of sub-pixels 200 includes a light emitting element 220, as shown in fig. 9. The light emitting element 220 may include a first electrode 221 on the substrate 100, a light emitting layer 223 on a side of the first electrode 221 away from the substrate 100, and a second electrode 222 on a side of the light emitting layer 223 away from the substrate 100. For example, the first electrode 221 is an anode, and the second electrode 222 is a cathode. For example, the second electrode 222 may receive a common connection line voltage signal VSS.

It should be noted that, in the embodiments of the present disclosure, when a structure is described as being on another structure, the structure may be in direct contact with the another structure, or may not be in direct contact with the another structure. For example, when describing the first electrode 221 as being located on the substrate base 100, the first electrode 221 may be above the substrate base 100 without being in direct contact therewith.

As shown in fig. 1, a plurality of first power lines 311 are located in the first region 110. The plurality of first power lines 311 are electrically connected to the first electrodes 221 of the plurality of sub-pixels. It is to be noted that when it is described that one component is electrically connected to another component, the one component may be directly or indirectly electrically connected to the other component. For example, the first power line 311 may be electrically connected to the first electrode 221 of the sub-pixel through several thin film transistors.

As shown in fig. 1, the first power bus 310 is located in the second region 120 on the side of the first boundary 111 away from the first region 110. The first power bus 310 is closer to the first boundary 111 than the boundaries of the other first regions. The first power bus 310 is electrically connected to the plurality of first power lines 311.

The second power line 320 is located in the second region 120 and electrically connected to the second electrode 222. The second power line 320 may include a first portion 321 and a second portion 322. The first portion 321 surrounds the second boundary 112, the third boundary 113, and the fourth boundary 114 of the first region 110. The second portion 322 is located on a side of the first power bus 310 away from the first region 110.

In some embodiments, the first power bus 310 is configured to receive a first voltage signal and the second power line 320 is configured to receive a second voltage signal. The first voltage signal is higher than the second voltage signal. For example, the first voltage signal is a power voltage signal VDD, and the second voltage signal is a common connection line voltage signal VSS.

A

gap

331 or 332 exists between the second portion 322 of the second power line 320 and the first power bus 310.

As shown in fig. 1, 4 and 5, the display substrate further includes a first insulating layer 920 covering the first power bus line 310, the second power line 320 and the gap 331 (or 332).

As shown in fig. 1, 4 and 5, the display substrate further includes a conductive layer 910 on a side of the first insulating layer 920 away from the gap 331 (or 332). The conductive layer 910 is configured to receive a fixed signal. In some embodiments, the fixed signal is a ground signal. For example, the ground signal is a voltage signal of 0V. Of course, those skilled in the art will understand that the fixed signal may be a fixed signal with other voltage values, and is not limited to the ground signal of 0V here. The orthographic projection of the conductive layer 910 on the substrate 100 at least partially overlaps the orthographic projection of the gap 331 (or 332) on the substrate 100. For example, the orthogonal projection of gap 331 (or 332) on substrate base 100 is located inside the orthogonal projection of conductive layer 910 on substrate base 100. For example, the material of the conductive layer 910 includes a metal or alloy material such as titanium and/or aluminum.

As shown in fig. 1, the display substrate further includes a plurality of touch electrode lines 410 located in the second area 120. The plurality of touch electrode lines 410 include a plurality of first touch electrode lines 411 and a plurality of second touch electrode lines 412. The first touch electrode line 411 surrounds a portion of the first boundary 111, the second boundary 112, and the third boundary 113 of the first area 110. The second touch electrode line 412 surrounds the fourth boundary 114 and another portion of the first boundary 111 of the first area 110. For example, the first touch electrode line 411 is a signal transmitting line, and the second touch electrode line 412 is a signal receiving line; or the first touch electrode line 411 is a signal receiving line and the second touch electrode line 412 is a signal transmitting line.

In some embodiments, the touch electrode line 410 includes a first conductive line 541 (as shown in fig. 10 later) on the first insulating layer and a second conductive line 542 (as shown in fig. 4 and 10 for example) on a side of the first conductive line away from the substrate 100. The first and second

conductive lines

541 and 542 are separated by a second insulating layer 536 (as shown in fig. 10, for example), and the first conductive line 541 is electrically connected to the second conductive line 542 through a conductive via (which may be referred to as a first conductive via) passing through the second insulating layer 536. The first conductive line 541 is at the same level as the conductive layer 910 and is isolated from the conductive layer 910. An orthogonal projection of the second conductive line 542 on the base substrate 100 at least partially overlaps an orthogonal projection of the conductive layer 910 on the base substrate 100. For example, the first wire 541 may include a Ti/Al/Ti (titanium/aluminum/titanium) triple structure, and the second wire 542 may include a Ti/Al/Ti (titanium/aluminum/titanium) triple structure. In some embodiments, the material of the conductive layer 910 is the same as the material of the first conductive line 541.

The term "same layer" refers to a layer structure formed by forming a film layer for forming a specific pattern by the same film formation process and then patterning the film layer by one patterning process using the same mask. Two structural layers in the same layer may be on the same structural layer. Two structural layers at the same level may be at different heights or have different thicknesses. Thus, a display substrate according to some embodiments of the present disclosure is provided. In the display substrate, the substrate includes a first region and a second region surrounding the first region. A plurality of sub-pixels are located in the first region, each sub-pixel including a light emitting element including a first electrode, a light emitting layer, and a second electrode. The plurality of first power lines are electrically connected with the first electrodes of the plurality of sub-pixels. The first power bus is electrically connected with a plurality of first power lines. The second power line is electrically connected to the second electrode. The second power line includes a first portion and a second portion. The first portion surrounds a second boundary, a third boundary, and a fourth boundary of the first region. The second portion is located on a side of the first power bus away from the first region. A gap exists between the second portion of the second power line and the first power bus. The first insulating layer covers the first power bus line, the second power line, and the gap. The conducting layer is arranged on one side of the first insulating layer far away from the gap. The conductive layer is configured to receive a fixed signal. The orthographic projection of the conducting layer on the substrate base plate is at least partially overlapped with the orthographic projection of the gap on the substrate base plate. The touch electrode lines are located in the second area. The touch electrode line comprises a first lead on the first insulating layer and a second lead on one side of the first lead, which is far away from the substrate base plate. The first conductive line is spaced apart from the second conductive line by a second insulating layer, and the first conductive line is electrically connected to the second conductive line through a conductive via passing through the second insulating layer. The first conductive line is in the same layer as the conductive layer and is isolated from the conductive layer. The orthographic projection of the second lead on the substrate base plate is at least partially overlapped with the orthographic projection of the conductive layer on the substrate base plate. In this embodiment, the conductive layer may serve as a signal shield, so that signal interference between the signal line above the gap and the signal line below the gap may be reduced, and the display effect of the display substrate may be improved.

In some embodiments, by making the conductive layer in the same layer as the first conductive lines and the material of the conductive layer is the same as that of the first conductive lines, the conductive layer can be formed at the same time when the first conductive lines are formed through the same patterning process, which facilitates the manufacturing of the display substrate.

In addition, the conductive layer arranged on the same layer as the first wire can reduce the interference between different signal lines, and can also solve the problem of width reduction of the first power bus (namely, a VDD line) caused by frame narrowing, thereby being beneficial to the frame narrowing design.

In other embodiments, the conductive layer may be at the same layer as the first conductive line or the second conductive line. For example, the conductive layer may be located below the first conductive line and separated from the first conductive line by an insulating layer. In this case, an orthographic projection of at least one of the first conductive line and the second conductive line on the base substrate at least partially overlaps with an orthographic projection of the conductive layer on the base substrate.

In other embodiments, the conductive layer may include at least a portion that does not overlap an orthographic projection of the first and second conductive lines on the substrate base. Here, the at least part of the conductive layer may be in the same layer as at least one of the first conductive line and the second conductive line. That is, the at least part of the conductive layer may be in the same layer as the first conductive line; alternatively, the at least part of the conductive layer may be in the same layer as the second conductive line; still alternatively, the at least part of the conductive layer may include a first subsection at the same layer as the first conductive line and a second subsection at the same layer as the second conductive line, the first subsection and the second subsection being separated by a second insulating layer, the first subsection being electrically connected to the second subsection through a conductive via passing through the second insulating layer.

In some embodiments, as shown in fig. 1, the second portion 322 of the second power line 320 includes a first sub-section 3221 and a second sub-section 3222. The first sub-portion 3221 and the second sub-portion 3222 are spaced apart and disposed opposite to each other. For example, the first sub-portion 3221 is adjacent to the second boundary 112, and the second sub-portion 3222 is adjacent to the fourth boundary 114. A first gap 331 exists between the first sub-section 3221 and the first power bus 310. A second gap 332 exists between the second sub-section 3222 and the first power bus 310. An orthogonal projection of at least one of the first gap 331 and the second gap 332 on the substrate base 100 at least partially overlaps an orthogonal projection of the conductive layer 910 on the substrate base 100.

In some embodiments, the orthographic projections of the first and

second gaps

331 and 332 on the substrate base 100 are located inside the orthographic projection of the conductive layer 910 on the substrate base 100. Therefore, the conducting layer can completely cover the two gaps, so that the signal interference between different signal lines can be further reduced, and the display effect of the display substrate is improved.

In some embodiments, as shown in fig. 1, the display substrate further includes a flexible circuit board 421 electrically connected to the conductive layer 910. The flexible circuit board 421 is configured to supply a fixed signal (for example, a ground signal GND) to the conductive layer 910. Here, in the case where the fixed signal is a ground signal, it is convenient to directly supply the fixed signal to the conductive layer by the flexible circuit board without providing an additional fixed signal source.

As shown in fig. 1, the flexible circuit board 421 is also electrically connected to the plurality of touch electrode lines 410, the first power bus 310 and the second power line 320. The flexible circuit board 421 is also configured to provide electrical signals to the plurality of touch electrode lines 410, the first power bus 310, and the second power line 320.

In some embodiments, as shown in fig. 1, the display substrate further includes a signal connection region 422 and an integrated circuit region 423. The integrated circuit region 423 is electrically connected to the first region 110 through the signal connection region 422. A plurality of data line leads are located at the signal connection region 422.

In some embodiments, as shown in fig. 1, the display substrate further includes a first touch electrode block 341 and a second touch electrode block 342 located in the first region. The first touch electrode block 341 is electrically connected to the first touch electrode line 411, and the second touch electrode block 342 is electrically connected to the second touch electrode line 412. The touch signals between the first touch electrode block 341 and the second touch electrode block 342 are different. In some embodiments, the first touch electrode block 341 and the second touch electrode block 342 are in the same layer as the second conductive line 542 (see fig. 9 and 10). In other embodiments, the first touch electrode block 341 and the second touch electrode block 342 are in the same layer as the first conductive line 541.

In some embodiments, the different first touch electrode blocks 341 are connected by an electrode bridge, and the different second touch electrode blocks 342 are directly connected. In other embodiments, the different second touch electrode blocks 342 are connected by an electrode bridge, and the different first touch electrode blocks 341 are directly connected.

Fig. 2 is an enlarged schematic view illustrating a partial structure within the first dashed box 141 in fig. 1, and the partial structure illustrated in fig. 2 omits a conductive layer and a second wire of a touch electrode line.

In some embodiments, as shown in fig. 2, the width W1 of the gap 331 (or 332) extending along a direction perpendicular to the first boundary 111 ranges from 40 microns to 60 microns. For example, the gap may have a width of 50 microns.

Fig. 3 is an enlarged schematic view illustrating a partial structure of a display substrate within a first dotted frame 141 in fig. 1 according to an embodiment of the present disclosure, and the partial structure illustrated in fig. 3 omits a second wire of a touch electrode line.

In some embodiments, as shown in fig. 3, the width W2 of the conductive layer 910 extending along the direction perpendicular to the first boundary 111 ranges from 50 microns to 70 microns. For example, the width of the conductive layer 910 is 60 μm. For example, the conductive layer may extend several microns (e.g., 5 microns) beyond the edges of the gap, which may substantially cover the gap, further reducing signal interference between different signal lines. As shown in fig. 3, the conductive layer 910 is connected to the flexible circuit board 421 (not shown in fig. 3) via a fixed signal line 930. For example, the fixed signal line is a ground signal line. For example, the conductive layer 910 is in the same layer as the fixed signal line 930, and the material of the conductive layer 910 is the same as that of the fixed signal line 930. Thus, the conductive layer and the fixed signal line can be formed by the same patterning process, thereby facilitating the manufacture of the display substrate.

The structure taken along the line B-B' in fig. 4 is described in detail below in conjunction with fig. 5.

As shown in fig. 5, the display substrate includes a base substrate 100 and a third insulating layer 950 covering the base substrate 100. The first power bus line 310 and the second power line 320 are located on a side of the third insulating layer 950 away from the substrate base plate 100. That is, the first power bus line 310 and the second power supply line 320 are located on the third insulating layer 950.

In some embodiments, the display substrate may further include a buffer layer 151 between the base substrate 100 and the third insulating layer 950. Thus, the third insulating layer 950 indirectly covers the substrate base plate 100. Of course, it can be understood by those skilled in the art that the display substrate may not include the buffer layer 151, and thus, the third insulating layer 950 may directly cover the substrate 100.

In some embodiments, as shown in fig. 5, the third insulating layer 950 includes: the first sub-insulating layer 231 on the substrate base plate 100, the second sub-insulating layer 242 on the first sub-insulating layer 231, and the third sub-insulating layer 243 on the second sub-insulating layer 242 are directly or indirectly covered. For example, the material of the first sub-insulating layer 231, the second sub-insulating layer 242, and the third sub-insulating layer 243 includes silicon dioxide, silicon nitride, or the like.

In some embodiments, as shown in fig. 5, the display substrate further includes: a plurality of first signal lines 501 and a plurality of second signal lines 502 embedded in the third insulating layer 950. The orthographic projections of the plurality of first signal lines 501 on the substrate 100 are alternately arranged with the orthographic projections of the plurality of second signal lines 502 on the substrate 100. The plurality of first signal lines 501 and the plurality of second signal lines 502 are provided in different layers. By thus arranging the

signal lines

501 and 502, space can be saved. As shown in fig. 5, the plurality of first signal lines 501 and the plurality of second signal lines 502 are on the side of the first sub-insulating layer 231 remote from the substrate board 100. For example, the first signal line 501 and the second signal line 502 may be data signal lines.

Since the orthographic projections of a portion of the first signal lines 501 and a portion of the second signal lines 502 on the substrate at least partially overlap with the orthographic projections of the

gaps

331 or 332 on the substrate, the conductive layer 910 can reduce signal interference between the

signal lines

501 or 502 and the touch electrode lines.

As shown in fig. 5, the second sub-insulating layer 242 is located between the plurality of first signal lines 501 and the plurality of second signal lines 502. The third sub-insulating layer 243 covers the plurality of second signal lines 502.

As shown in fig. 5, a first insulating layer 920 covers the first power bus line 310, the second power line 320, and the gap 331 (or 332).

In some embodiments, the first insulating layer 920 includes a planarization layer covering the first power bus line 310 and the second power line 320. For example, the planarization layer includes: a first planarizing layer 521 covering at least the second power supply line 320, and a second planarizing layer 522 covering the first power supply bus 310 and the first planarizing layer 521. For example, the materials of the first and second planarization layers 521 and 522 may include organic insulating materials such as polyimide, respectively.

In some embodiments, as shown in fig. 5, the first insulating layer 920 further includes a pixel defining layer 523 on a planarization layer (e.g., the second planarization layer 522).

In some embodiments, as shown in fig. 5, the first insulating layer 920 further includes an encapsulation layer 530 on a side of the pixel defining layer 523 remote from the planarization layer (e.g., the second planarization layer 522). For example, the encapsulation layer 530 includes: a first inorganic encapsulation layer 531 on a side of the pixel defining layer 523 away from the planarization layer, an organic encapsulation layer 532 on a side of the first inorganic encapsulation layer 531 away from the pixel defining layer 523, and a second inorganic encapsulation layer 533 on a side of the organic encapsulation layer 532 away from the first inorganic encapsulation layer 531. For example, the material of the first inorganic encapsulation layer 531 includes silicon nitride, etc., the material of the organic encapsulation layer 532 includes PMMA (poly methacrylate), etc., and the material of the second inorganic encapsulation layer 533 includes silicon nitride, etc.

For example, the first inorganic encapsulation layer 531 may be formed on the pixel defining layer 523 by a CVD (Chemical Vapor Deposition) process, and then the organic encapsulation layer 532 is formed on the first inorganic encapsulation layer 531 by an inkjet printing process, and then the second inorganic encapsulation layer 533 is formed on the organic encapsulation layer 532 by a CVD process.

In some embodiments, as shown in fig. 5, the first insulating layer 920 further includes a blocking layer 535 on a side of the encapsulation layer 530 remote from the pixel defining layer 523. For example, the material of the barrier layer 535 includes an inorganic insulating material. As another example, the material of the barrier layer 535 includes an organic insulating material. As shown in fig. 5, the conductive layer 910 is on the side of the barrier layer 535 away from the base substrate 100. In practice, the first conductive line 541 of the touch electrode line 410 is also on the blocking layer 535 (refer to fig. 10 later). This indicates that the conductive layer 910 is in the same layer as the first conductive line 541 of the touch electrode line 410.

In some embodiments, as shown in fig. 5, the display substrate further includes a second insulating layer 536 covering the conductive layer 910 and the first conductive lines 541. For example, the material of the second insulating layer 536 includes silicon nitride, silicon oxide, silicon oxynitride, or the like. As another example, the material of the second insulating layer 536 includes an organic insulating material. As shown in fig. 5, the second conductive line 542 of the touch electrode line 410 is disposed on the second insulating layer 536.

In some embodiments, as shown in fig. 5, the display substrate further includes a cover layer 550 covering the second conductive line 542. The material of the capping layer 550 includes, for example, an organic insulating material.

Fig. 6 is a schematic sectional view showing a structure taken along a line C-C' in fig. 4.

Here, the structural layers in fig. 6 similar to those shown in fig. 5 will not be described in detail. As shown in fig. 6, a fixed signal line 930 is located on the barrier layer 535. The fixed signal line 930 is spaced apart from the second conductive line 542 by the second insulating layer 536. The fixed signal line 930 is in the same layer as the conductive layer 910 and is connected to the conductive layer 910. Therefore, the fixed signal line and the conductive layer are conveniently formed through the same composition process, and the manufacturing of the display substrate is convenient.

Fig. 7 is a plan view illustrating a partial structure of a display substrate according to another embodiment of the present disclosure. Here, a structure similar to that shown in fig. 1 in fig. 7 will not be described in detail.

In some embodiments, as shown in fig. 7, the display substrate further includes a bending region 940. The bending region 940 is between the conductive layer 910 and the flexible circuit board 421. The conductive layer 910 is connected to the flexible circuit board 421 via a fixed signal line 930, and the fixed signal line 930 passes through the bending region 940.

Fig. 8 is an enlarged schematic view showing a partial structure within the second dashed-line box 142 in fig. 1.

Fig. 8 shows the first touch electrode block 341 (or the second touch electrode block 342). As described above, the first touch electrode block 341 is electrically connected to the first touch electrode line 411, and the second touch electrode block 342 is electrically connected to the second touch electrode line 412. In addition, the opening 211 of the sub-pixel is also shown in fig. 8.

Fig. 9 is a schematic sectional view showing a structure taken along a line D-D' in fig. 8.

As shown in fig. 9, the sub-pixel 200 includes a thin film transistor 230 and a connection electrode 260 in addition to the light emitting element 220.

The thin film transistor 230 includes an active layer 232 on the substrate base plate 100, a gate electrode 233 on a side of the active layer 232 away from the substrate base plate 100, and a source electrode 234 and a drain electrode 235 on a side of the gate electrode 233 away from the substrate base plate 100. For example, the active layer 232 may be positioned on the buffer layer 151. The first sub-insulating layer 231 is located between the active layer 232 and the gate electrode 233. The second and third

sub-insulating layers

242 and 243 are between the gate 233 and the source 234/drain 235. The source electrode 234 is electrically connected to the active layer 232 through a second conductive via. The second conductive via passes through the third sub-insulating layer 243, the second sub-insulating layer 242, and the first sub-insulating layer 231. The drain electrode 235 is electrically connected to the active layer 232 through a third conductive via. The third conductive via passes through the third sub-insulating layer 243, the second sub-insulating layer 242, and the first sub-insulating layer 231.

As shown in fig. 9, the connection electrode 260 is located on the side of the thin film transistor 230 remote from the substrate 100. The source electrode 234 or the drain electrode 235 is electrically connected to the connection electrode 260. The connection electrode 260 is electrically connected to the first electrode 221 of the light emitting element 220. For example, the connection electrode 260 is electrically connected to the drain electrode 235 through a fourth conductive via. The fourth conductive via passes through the first planarization layer 521. The first electrode 221 is electrically connected to the connection electrode 260 through a fifth conductive via. The fifth conductive via passes through the second planarization layer 522.

In other embodiments, the display substrate may not be provided with the connection electrode 260. Thus, the first planarizing layer 521 and the second planarizing layer 522 are the same planarizing layer. The first electrode 221 is electrically connected to the drain electrode 235 through a conductive via that passes through the planarization layer.

In some embodiments, as shown in fig. 9, the display substrate further includes a capacitor between the third sub-insulating layer 243 and the base substrate 100. The capacitor includes a first capacitive electrode 611 on a side of the first sub-insulating layer 231 remote from the base substrate 100 and a second capacitive electrode 612 on a side of the second sub-insulating layer 242 remote from the first capacitive electrode 611. The first capacitor electrode 611 is at the same level as the gate 233 and is isolated from the gate 233. The second capacitor electrode 612 is located at the same layer as the second signal line 502, and is fabricated by the same patterning process as the second signal line. The second sub-insulating layer 242 covers the first capacitor electrode 611, and the third sub-insulating layer 243 covers the second capacitor electrode 612.

The same patterning process described above refers to forming a film layer for forming a specific pattern by using the same film forming process, and then forming a layer structure by using the same mask plate through a single patterning process. It should be noted that, depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and the specific patterns may be at different heights or have different thicknesses.

In some embodiments, as shown in fig. 9, the display substrate further comprises a spacer layer 630 on a side of the pixel defining layer 523 remote from the substrate 100. The second electrode 222 of the light emitting device 220 covers the spacer layer 630. For example, the material of the spacer layer 630 may include an inorganic insulating material, an organic insulating material, or the like.

In some embodiments, as shown in fig. 9, the first touch electrode block 341 and the second touch electrode block 342 are located on a side of the second insulating layer 536 away from the substrate base plate 100. The cover layer 550 covers the first touch electrode 341 and the second touch electrode 342.

In other embodiments, the display substrate may further include a passivation layer (not shown in fig. 9) between the third sub insulating layer 243 and the first planarization layer 521.

Fig. 10 is a schematic sectional view showing a structure taken along line a-a' in fig. 1.

In some embodiments, as shown in fig. 10, the first portion 321 of the second power line 320 includes a first conductive portion 711, a second conductive portion 712, and a third conductive portion 713. The second conductive portion 712 is located on a side of the first conductive portion 711 remote from the substrate base plate 100. The third conductive portion 713 is located on a side of the second conductive portion 712 remote from the substrate base plate 100. The first conductive portion 711, the second conductive portion 712, and the third conductive portion 713 are electrically connected. The first conductive portion 711 is located at the same layer as the source electrode 234 or the drain electrode 235. The second conductive part 712 is located at the same layer as the connection electrode 260. The third conductive portion 713 is located at the same layer as the first electrode 221. The first conductive portion 711 is the same material as the source electrode 234 or the drain electrode 235, and is formed through the same patterning process as the source electrode and the drain electrode. The second conductive part 712 is formed of the same material as the connection electrode 260 and is formed through the same patterning process as the connection electrode. The third conductive portion 713 is made of the same material as the first electrode 221 and is formed through the same patterning process as the first electrode 221. As shown in fig. 10, the third conductive portion 713 is spaced apart from the first electrode 221, and the third conductive portion 713 is electrically connected to the second electrode 222.

In some embodiments, as shown in fig. 10, the display substrate may further include a first dam (dam) 810. The first bank 810 may include a portion 811 at the same layer as the second planarization layer 522 and a portion 812 at the same layer as the pixel defining layer 523. The display substrate may further include a second bank 820. The second bank 820 may include a portion 821 in the same layer as the second planarization layer 522, a portion 822 in the same layer as the pixel defining layer 523, and a portion 823 in the same layer as the spacer layer 630.

In addition, as shown in fig. 10, in each touch electrode line 410, the first conductive line 541 is electrically connected to the second conductive line 542 through the first conductive via 961, which may reduce the resistance of the touch electrode line 410. The first conductive via 961 includes a via passing through the second insulating layer 536 and a conductive material layer within the via. The first conductive line 541 is in the same layer as the conductive layer 910 and the fixed signal line 930, so that the first conductive line, the conductive layer and the fixed signal line can be formed through the same patterning process, thereby facilitating the manufacture of the display substrate.

Thus far, a display substrate according to some embodiments of the present disclosure is described in detail.

In some embodiments of the present disclosure, a display device is also provided. The display device may comprise a display substrate as described previously (e.g. the display substrate shown in fig. 1). For example, the display device may be: any product or component with a display function, such as a display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Fig. 11 is a flowchart illustrating a method of manufacturing a display substrate according to one embodiment of the present disclosure. As shown in fig. 11, the manufacturing method includes steps S1102 to S1116.

In step S1102, a substrate base plate is provided, the substrate base plate including a first region and a second region surrounding the first region, the first region including a first boundary, a second boundary, a third boundary, and a fourth boundary.

In step S1104, a plurality of sub-pixels located in the first region are formed, at least one of the plurality of sub-pixels including: the light-emitting element comprises a first electrode positioned on the substrate, a light-emitting layer positioned on one side of the first electrode, which is far away from the substrate, and a second electrode positioned on one side of the light-emitting layer, which is far away from the substrate.

In step S1106, a plurality of first power lines in the first region are formed, and the plurality of first power lines are electrically connected to the first electrodes of the plurality of sub-pixels.

In step S1108, a first power bus located in a second region of the first boundary, the second region being away from the first region, is formed, and the first power bus is electrically connected to the plurality of first power lines.

In step S1110, a second power line located in the second region and electrically connected to the second electrode is formed, where the second power line includes a first portion and a second portion, the first portion surrounds a second boundary, a third boundary and a fourth boundary of the first region, and the second portion is located on a side of the first power bus line away from the first region, where a gap exists between the second portion of the second power line and the first power bus line.

In step S1112, a first insulating layer covering the first power bus line, the second power line, and the gap is formed.

In step S1114, a conductive layer is formed on a side of the first insulating layer away from the gap, the conductive layer configured to receive a fixed signal (e.g., a ground signal), and an orthogonal projection of the conductive layer on the substrate base at least partially overlaps an orthogonal projection of the gap on the substrate base.

In step S1116, a plurality of touch electrode lines in the second region are formed, where the touch electrode lines include first conductive lines on the first insulating layer and second conductive lines on a side of the first conductive lines away from the substrate, the first conductive lines and the second conductive lines are separated by the second insulating layer, and the first conductive lines are electrically connected to the second conductive lines through conductive vias passing through the second insulating layer. The first conductive line is in the same layer as the conductive layer and is isolated from the conductive layer. The first conductive line and the conductive layer are formed by the same patterning process. The orthographic projection of the second lead on the substrate is at least partially overlapped with the orthographic projection of the conductive layer on the substrate.

Thus, a method of manufacturing a display substrate according to one embodiment of the present disclosure is provided. In the manufacturing method, the formed conducting layer can play a role in signal shielding, so that signal interference between the signal line above the gap and the signal line below the gap can be reduced, and the display effect of the display substrate can be improved. In addition, the first conductive line and the conductive layer are formed through the same patterning process, so that the display substrate can be conveniently manufactured.

Thus, various embodiments of the present disclosure have been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concepts of the present disclosure. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. It will be understood by those skilled in the art that various changes may be made in the above embodiments or equivalents may be substituted for elements thereof without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A display substrate, comprising:

a substrate base plate including a first region and a second region surrounding the first region, the first region including a first boundary, a second boundary, a third boundary, and a fourth boundary;

a plurality of sub-pixels located in the first region, at least one of the plurality of sub-pixels including: a light emitting element including a first electrode on the substrate base, a light emitting layer on a side of the first electrode away from the substrate base, and a second electrode on a side of the light emitting layer away from the substrate base;

a plurality of first power lines in the first region and electrically connected to the first electrodes of the plurality of sub-pixels;

the first power bus is positioned in a second area on one side, far away from the first area, of the first boundary, and the first power bus is electrically connected with the plurality of first power lines;

a second power supply line located in the second region and electrically connected to the second electrode, the second power supply line including a first portion and a second portion, the first portion surrounding the second boundary, the third boundary, and the fourth boundary of the first region, the second portion being located on a side of the first power supply bus line away from the first region, wherein a gap exists between the second portion of the second power supply line and the first power supply bus line;

a first insulating layer covering the first power bus line, the second power supply line, and the gap;

a conductive layer on a side of the first insulating layer remote from the gap, the conductive layer configured to receive a fixed signal, an orthographic projection of the conductive layer on the substrate base at least partially overlapping an orthographic projection of the gap on the substrate base; and

the touch control electrode wires are positioned in the second area and comprise first wires on the first insulating layer and second wires on one side, far away from the substrate base plate, of the first wires, the first wires and the second wires are separated by a second insulating layer, the first wires are electrically connected with the second wires through conductive vias penetrating through the second insulating layer, the first wires and the conductive layer are positioned in the same layer and are separated from the conductive layer, and the orthographic projection of the second wires on the substrate base plate is at least partially overlapped with the orthographic projection of the conductive layer on the substrate base plate.

2. The display substrate of claim 1,

the material of the conductive layer is the same as that of the first conductive line.

3. The display substrate of claim 1,

the plurality of touch electrode lines include a plurality of first touch electrode lines and a plurality of second touch electrode lines, the first touch electrode lines surrounding a portion of the first boundary, the second boundary, and the third boundary;

the second touch electrode line surrounds the other portion of the first boundary and the fourth boundary.

4. The display substrate of claim 3,

the first touch electrode line is a signal sending line, and the second touch electrode line is a signal receiving line.

5. The display substrate of claim 3, further comprising:

the first touch electrode block and the second touch electrode block are located in the first area, wherein the first touch electrode block is electrically connected with the first touch electrode wire, the second touch electrode block is electrically connected with the second touch electrode wire, the first touch electrode block and the second touch electrode block are located in the same layer as the second wire, or the first touch electrode block and the second touch electrode block are located in the same layer as the first wire.

6. The display substrate of claim 1, further comprising:

a flexible circuit board electrically connected with the conductive layer, the flexible circuit board configured to provide the fixed signal to the conductive layer.

7. The display substrate of claim 1,

the fixed signal is a ground signal.

8. The display substrate of claim 1,

the orthographic projection of the gap on the substrate base plate is positioned inside the orthographic projection of the conducting layer on the substrate base plate.

9. The display substrate of claim 1,

a width of the gap extending in a direction perpendicular to the first boundary is in a range of 40 to 60 micrometers;

the conductive layer has a width extending in a direction perpendicular to the first boundary in a range of 50 to 70 micrometers.

10. The display substrate of claim 6, further comprising:

a bending region between the conductive layer and the flexible circuit board;

wherein the conductive layer is connected to the flexible circuit board via a fixed signal line passing through the bending region.

11. The display substrate of claim 10,

the conducting layer and the fixed signal line are located in the same layer, and the conducting layer and the fixed signal line are made of the same material.

12. The display substrate of claim 1, wherein the second portion comprises a first sub-portion and a second sub-portion, the first and second sub-portions being spaced apart and disposed opposite each other, the first sub-portion being proximate to the second boundary, the second sub-portion being proximate to the fourth boundary;

a first gap exists between the first sub-portion and the first power bus bar, a second gap exists between the second sub-portion and the first power bus bar, and an orthographic projection of at least one of the first gap and the second gap on the substrate base at least partially overlaps with an orthographic projection of the conductive layer on the substrate base.

13. The display substrate of any one of claims 1 to 12,

the first power bus is configured to receive a first voltage signal;

the second power line is configured to receive a second voltage signal;

wherein the first voltage signal is higher than the second voltage signal.

14. The display substrate of claim 1, wherein the first insulating layer comprises:

a planarization layer covering the first power bus line and the second power supply line;

a pixel defining layer on the planarization layer;

an encapsulation layer on a side of the pixel defining layer remote from the planarization layer; and

a barrier layer on a side of the encapsulation layer distal from the pixel defining layer.

15. The display substrate of claim 1, further comprising:

the third insulating layer covers the substrate base plate;

wherein the first power bus and the second power line are located on one side of the third insulating layer away from the substrate base plate.

16. The display substrate of claim 15, further comprising:

a plurality of first signal lines and a plurality of second signal lines embedded in the third insulating layer, wherein orthographic projections of the plurality of first signal lines on the substrate base plate and orthographic projections of the plurality of second signal lines on the substrate base plate are alternately arranged.

17. A display device, comprising: a display substrate according to any one of claims 1 to 16.

18. A method of manufacturing a display substrate, comprising:

providing a substrate base plate, wherein the substrate base plate comprises a first area and a second area surrounding the first area, and the first area comprises a first boundary, a second boundary, a third boundary and a fourth boundary;

forming a plurality of sub-pixels located in the first region, at least one of the plurality of sub-pixels including: a light emitting element including a first electrode on the substrate base, a light emitting layer on a side of the first electrode away from the substrate base, and a second electrode on a side of the light emitting layer away from the substrate base;

forming a plurality of first power lines in the first region, the plurality of first power lines being electrically connected to the first electrodes of the plurality of sub-pixels;

forming a first power bus of a second area on one side of the first boundary, which is far away from the first area, wherein the first power bus is electrically connected with the plurality of first power lines;

forming a second power supply line that is located in the second region and electrically connected to the second electrode, the second power supply line including a first portion and a second portion, the first portion surrounding the second boundary, the third boundary, and the fourth boundary of the first region, the second portion being located on a side of the first power supply bus line away from the first region, wherein a gap exists between the second portion of the second power supply line and the first power supply bus line;

forming a first insulating layer covering the first power bus line, the second power supply line, and the gap;

a conductive layer formed on a side of the first insulating layer away from the gap, the conductive layer configured to receive a fixed signal, an orthographic projection of the conductive layer on the substrate base at least partially overlapping an orthographic projection of the gap on the substrate base; and

forming a plurality of touch electrode lines in the second area, wherein the touch electrode lines comprise first lead wires on the first insulating layer and second lead wires on one side of the first lead wires far away from the substrate base plate, the first lead wires and the second lead wires are separated by a second insulating layer, and the first lead wires are electrically connected with the second lead wires through conductive vias penetrating through the second insulating layer;

the first conducting wire and the conducting layer are in the same layer and are separated from the conducting layer, the first conducting wire and the conducting layer are formed through the same composition process, and the orthographic projection of the second conducting wire on the substrate is at least partially overlapped with the orthographic projection of the conducting layer on the substrate.