CN112887047B - System and method for transmitting clock signal in computer cluster - Google Patents

System and method for transmitting clock signal in computer cluster Download PDF

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CN112887047B
CN112887047B CN202110040008.0A CN202110040008A CN112887047B CN 112887047 B CN112887047 B CN 112887047B CN 202110040008 A CN202110040008 A CN 202110040008A CN 112887047 B CN112887047 B CN 112887047B
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CN112887047A (en
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张营
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation

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  • Computer Networks & Wireless Communication (AREA)
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  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The invention discloses a system and a method for transmitting clock signals in a computer cluster, wherein an access device, 0 or a plurality of tapping devices, 0 or a plurality of through sensors, a terminal card and a circuit form a tree-shaped clock signal transmission network; the access device is used as a root node; a plurality of terminal cards are used as leaf nodes; taking 0 or a plurality of tapping devices and 0 or a plurality of penetrating sensors as intermediate nodes; the clock signal output by the clock source is accessed to the clock signal transmission network by the access device and is transmitted to the terminal card of the leaf node through 0 or a plurality of tapping devices and 0 or a plurality of sensor intermediate nodes. The invention measures the path delay in the low level period of the time signal, and a plurality of slave ends divide different time slots to measure if necessary; the tapping device and the penetrating sensor are adopted, so that the method is suitable for being expanded to large-scale computer clusters; the invention encodes the path delay value, transmits the path delay value together with the code at any time, does not need to compensate time signals through delay, simplifies the system and improves the stability of the system.

Description

System and method for transmitting clock signal in computer cluster
Technical Field
The invention relates to a system and a method for transmitting clock signals in a computer cluster, belonging to the technical field of time synchronization.
Background
A computer cluster is a group of systems of computers, such as interconnected servers in a data center, connected by a data transmission network, and arranged in relatively close proximity. If each computer in the cluster can obtain a precisely synchronized clock signal, software running on each computer marks an event (i.e. a timestamp) by using the time indicated by the local clock, so that the sequence of a series of events can be agreed, and global consistency is realized.
Computer clusters currently typically employ NTP technology (NTPv 4, RFC 5905 standard) that uses a data transmission network (e.g., ethernet) to transfer clock signals. The NTP technology can only reach the millisecond-level clock signal transmission precision, and is difficult to meet the requirements.
PTP technology (PTPv 2, IEEE 1588-2008 standard) can realize clock signal transfer accuracy on the order of microseconds; the DTP technology proposed by 'Vishal Shrivastav, ki-Suh Lee, han Wang, hakim Weatherspoon: globally Synchronized Time via Datacenter networks IEEE/ACM Transaction on networks.27 (4): 1401-1416, 2019' can achieve clock signal transmission accuracy of about several hundred nanoseconds in a data center network; the Sundial technique proposed by "Yuliang Li, gautam Kumar, hema Hariharan, hassan Wassel, peter Hochsschill, et al Sundial: fault-tolerant Clock Synchronization for datacenters.14th USENIX Symposium on Operating Systems Design, implementation (OSDI 20), 1171-1186,2020" can achieve clock signal transfer accuracy of about one hundred nanoseconds in a data center network; the White Rabbit (White Rabbit) technology developed by European Nuclear research organization (CERN) in 2011 can realize sub-nanosecond clock signal transmission accuracy. All of the above technologies require high cost to upgrade the data transmission network equipment, and are difficult to popularize.
Disclosure of Invention
The invention aims to: in view of the problems and deficiencies of the prior art, the present invention provides an accurate and low cost system and method for delivering clock signals to a computer cluster.
The technical scheme is as follows: a system for transmitting clock signals in a computer cluster comprises a clock source, an access device, 0 or a plurality of taps, 0 or a plurality of pass-through devices, a terminal card and a line.
The access device, the 0 or a plurality of tapping devices, the 0 or a plurality of penetrating sensors, the terminal card and the circuit form a tree-shaped clock signal transmission network. The access device is used as a root node; a plurality of terminal cards are used as leaf nodes; taking 0 or a plurality of tapping devices and 0 or a plurality of penetrating sensors as intermediate nodes; the clock signal output by the clock source is accessed to the clock signal transmission network by the access device and is transmitted to the terminal card of the leaf node through 0 or a plurality of tapping devices and 0 or a plurality of sensor intermediate nodes.
The tree clock signal transfer network uses separate time loops, time code loops and frequency loops to jointly transfer the complete clock signal.
The access device amplifies or converts the time signal, the time code signal and the frequency signal output by the clock source.
The tapping device amplifies or processes clock signals transmitted by upstream equipment and taps the clock signals to a plurality of downstream equipment; during the low level of the time signal, the tap device measures the round trip path delay of the nearest other upstream tap device or the access device by using a foldback method, and the round trip path delay and the time code are transmitted to downstream equipment together; during the low level of the time signal, the tap returns a delay measurement signal sent by downstream equipment; the number of downstream devices to which the tap outputs can be connected is limited only by the number of tap output ports, which can be extended by cascading taps.
The transparent sensor amplifies clock signals transmitted by upstream equipment and is connected to a plurality of downstream equipment in a tapping way; during a low level of the time signal, the pass-through sensor amplifies a delay measurement signal transmitted from the downstream device to the upstream device in a time-sharing manner and amplifies the delay measurement signal returned from the upstream device; the number of downstream devices to which the pass-through sensor output can be connected is limited by the number of time slots of the measured path delay, and the downstream device number limit cannot be extended by cascading only pass-through sensors.
The transparent sensor structure is simpler than a tapping device, and the transparent sensor structure and the tapping device are combined to be used for expanding the scale of the tree clock signal transmission network.
The terminal cards receive clock signals transmitted by upstream equipment; during the low level of the time signal, the terminal card measures the round trip path delay of the nearest upstream tapping device or the access device by using a foldback method, compensates the total path delay by numerical calculation, outputs a clock count value, and finally realizes clock signal transmission.
The clock signal output port of the clock source is composed of loop terminals of a time signal, a time code signal and a frequency signal which are separated.
The access device comprises a time signal amplifying module, M short-circuit switches (M is a positive integer representing the number of output ports), M output ports, a time sequence control module, a time code signal converting module and a frequency signal amplifying module; the input clock signal of the accessor is from the output port of the clock source.
The input of the time signal amplifying module is connected with the time loop of the input clock signal, the output of the time signal amplifying module is tapped into M paths, and the M paths are respectively output to the time loop terminals of M output ports through M shorting switches; the lines from the time signal amplifying module to the M short-circuit switches are equal in length; and the control signals of the M shorting switches are all from the time sequence control module.
And the input of the time code signal conversion module is connected with a time code loop of the input clock signal, and the time code loop is tapped and output to the time code loop terminals of the M output ports.
And the input of the frequency signal amplifying module is connected with the frequency loop of the input clock signal, and the frequency loop is tapped and output to the frequency loop terminals of the M output ports.
The M output ports comprise three separated loop output terminals of a time loop, a time code loop and a frequency loop, and M complete clock signals are formed; the downstream device of each output port of the access device may be any of a tap, a pass-through or a terminal card.
The tapping device comprises a time signal amplifying module, N short-circuit switches (N is a positive integer representing the number of output ports), N output ports, a time sequence control module, a time code signal processing module, a frequency signal amplifying module, a time interval measuring module, a delay signal generating module, a selection switch and an isolating switch; the input clock signal of the tap may come from any output port of the access, pass-through or other tap.
The input of the time signal amplifying module is connected with a time loop of the input clock signal through a selection switch, the output of the time signal amplifying module is tapped into N paths, and the N paths are respectively output to time loop terminals of N output ports through N shorting switches; the lines from the time signal amplifying module to the N short-circuit switches are equal in length; and control signals of the selection switch and the N short-circuit switches are all from the time sequence control module.
And the input of the time code signal processing module is connected with a time code loop of the input clock signal, and the time code loop is tapped and output to the time code loop terminals of the N output ports.
And the input of the frequency signal amplifying module is connected with the frequency loop of the input clock signal, and the frequency loop is tapped and output to the frequency loop terminals of the N output ports.
The input of the time interval measuring module is connected with the time loop of the input clock signal through the isolating switch and then through the selecting switch, and the time loop is output to the time code signal processing module.
The output of the delay measurement signal generation module is connected with the time loop of the input clock signal through an isolating switch and a selecting switch.
The control signal of the isolating switch is from the delay measurement signal generating module.
The N output ports comprise three separated loop output terminals of a time loop, a time code loop and a frequency loop, and form N complete clock signals; the downstream device of each output port of the tap may be any one of a pass-through, termination card or other tap.
The transmission sensor comprises a time signal bidirectional amplifying module, P output ports (P is a positive integer representing the number of the output ports), a time code signal amplifying module and a frequency signal amplifying module; the input clock signal of the pass-through sensor may come from any output port of an access, tap or other pass-through sensor.
And the input of the time signal bidirectional amplifying module is connected with the time loop of the input clock signal, and the time loop terminal of the P output ports is tapped and output.
And the input of the time code signal amplifying module is connected with a time code loop of the input clock signal, and the time code loop is tapped and output to the time code loop terminals of the P output ports.
And the input of the frequency signal amplifying module is connected with the frequency loop of the input clock signal, and the frequency loop is tapped and output to the frequency loop terminals of the P output ports.
The P output ports comprise three separated loop output terminals of a time loop, a time code loop and a frequency loop, and P complete clock signals are formed; the downstream device of each output port of the pass-through sensor may be any tap, termination card or other pass-through sensor.
The terminal card comprises a time signal amplifying module, a counting correction module, a time code signal processing module, a frequency signal doubling module, a high-speed counter, a time interval measuring module, a delay signal generating module, a time sequence control module, a selection switch, an isolating switch, a reset counting sign output port, a counting deviation output port, a path delay output port, a clock counting output port and a disconnection sign output port; the input clock signal of the terminal card may come from any output port of an access, tap or pass-through.
The input of the time signal amplifying module is connected with a time loop of the input clock signal through a selection switch and is output to the counting correcting module; the control signal of the selection switch comes from the time sequence control module.
The input of the time code signal processing module is connected with the time code loop of the input clock signal, the time code value and the path delay value are output to the counting correction module, and the path delay value is output to the outside through the path delay output port.
The input of the frequency signal doubling module is connected with the frequency loop of the input clock signal and outputs the frequency loop to the high-speed counter; the frequency signal frequency multiplication module also outputs a disconnection warning sign to the outside through a disconnection sign output port.
The high-speed counter counts the frequency multiplication signals, outputs the frequency multiplication signals to the count correction module, receives the set value of the count correction module, and outputs the final clock count to the outside through the clock count output port.
The input of the time interval measuring module is connected with the time loop of the input clock signal through the isolating switch and then through the selecting switch, and the time loop is output to the time code signal processing module.
The output of the delay measurement signal generation module is connected with the time loop of the input clock signal through an isolating switch and a selecting switch.
The control signal of the isolating switch is from the delay measurement signal generating module.
The counting correction module receives the time signal output by the time signal amplification module, the time code value and the path delay value output by the time code signal processing module and the frequency multiplication signal count value output by the high-speed counter, and the offset value of the time code value and the frequency multiplication signal count value after compensating the path delay is output to the outside through the counting offset output port; when the deviation exceeds a preset limit value, a set value is output to the high-speed counter, and a reset count alarm flag is output to the outside through a reset count flag output port.
The number M of the output ports of the access device, the number N of the output ports of the tapping device and the number P of the output ports of the transmission device are only used for distinguishing the number of the output ports of three devices, and the number M, N and the number P of the output ports of the three devices can be the same or different; the same equipment can be provided with different output port numbers for the access device, the tapping device and the transmission device.
The invention also provides a method for transmitting clock signals in a computer cluster, which comprises the following steps:
1) Delivering clock signals
1.1 Timing control module of access device, leading the time signal pulse front edge t A Duration (0 < t) A ＜T L ) Controlling M shorting switches to be switched to a conducting state; the time signal amplifying module of the access device amplifies the time signal input by the clock source and adjusts the duty ratio of the time signal pulse (without changing the leading edge of the pulse) to make the duration of the high level be T H The duration of the low level is T L Wherein T is H +T L T is the period of the time signal; the output of the time signal amplifying module is divided into M paths, and the M paths are respectively output to the time loop terminals of M output ports through M short-circuit switches, so that the time signals are transmitted to downstream equipment.
1.2 Timing control module of tapping device, leading time signal pulse front edge t A The time length controls the time signal amplifying module of the selection switch to the branch circuit of the tapping device, and controls N short-circuit switches to switch to a conducting state; the time signal amplifying module amplifies an upstream input time signal, the output is tapped into N paths, the N paths are respectively output to the time loop terminals of N output ports through N short-circuit switches, and the time signal is transmitted to downstream equipment.
1.3 A time signal bidirectional amplifying module of the transmission sensor amplifies an upstream input time signal, and the time signal is tapped and output to a time loop terminal of the P output ports to be transmitted to downstream equipment.
1.4 Timing control module of terminal card, leading time signal pulse front edge t A The duration controls the selection switch to the branch where the time signal amplifying module is located; the time signal amplifying module amplifies the time signal input from the upstream and outputs the time signal to the counting correcting module, and the counting correcting module is triggered by the pulse leading edge.
1.5 The time code signal conversion module of the access device decodes the time code signal input by the clock source, recodes the time code signal, taps the time code loop terminals output to M output ports and transmits the time code loop terminals to downstream equipment; for ease of computation, the time code format of the clock source is converted into an integer number.
1.6 A time code signal processing module of the tapping device decodes the time code signal input from upstream and reads the time code value t N And a series of path delay values D k ，D k-1 ...D 1 Where k is the number of other taps in the path from the current tap to the access; d (D) j Is the total path delay of the j-th tap in the path to the access, j e {1,2,., k }; the number j starts from a tap directly connected with the access device to be 1 st, and the number j of a downstream tap is increased step by step; the number j is used only to describe the series of path delay values D k ，D k-1 ...D 1 Is a sequence of (2); if no tap is arranged in the upstream path, k=0, and the series of path delay values in the time code signal are all 0;
The time code signal processing module of the tapping device reads the round trip path delay value d output by the time interval measuring module; based on the assumption of round-trip path symmetry, the path delay is half the round-trip path delay value d; the time code signal processing module calculates the total path delay value D from the current tapping device to the access device k+1 ＝d/2+D k Time code value t N And a series of path delay values D k+1 ，D k ，D k-1 ...D 1 Is a processed time code signal, is tapped to the time code loop terminals of N output ports and is transmittedTo downstream equipment.
1.7 The time code signal amplifying module of the transmission sensor amplifies the time code signals input from the upstream, and the time code signals are tapped and output to the time code loop terminals of the P output ports and transmitted to downstream equipment.
1.8 A time code signal processing module of the terminal card decodes the upstream input time code signal and reads the time code value t N And a series of path delay values D k′ ，D k′-1 ...D 1 Where k' is the number of taps in the path from the current terminal card to the access; d (D) j Is the total path delay of the j-th tap in the path to the access device, j e {1,2,., k' }; the number j starts from a tap directly connected with the access device to be 1 st, and the number j of a downstream tap is increased step by step; the number j is used only to describe the series of path delay values D k′ ，D k′-1 ...D 1 Is a sequence of (2); if no tap is arranged in the upstream path, k' =0, and the series of path delay values in the time code signal are all 0;
the time code signal processing module of the terminal card reads the round trip path delay value d' output by the time interval measuring module; based on the assumption of round-trip path symmetry, the path delay is half the round-trip path delay value d'; the time code signal processing module calculates the total path delay value D from the current terminal card to the access device k′+1 ＝d′/2+D k′ The time code value t N And total path delay D k′+1 Outputting to a count correction module; outputting a series of path delay values D from the path delay output port to the outside k′+1 ，D k′ ，D k′-1 ...D 1 。
1.9 The frequency signal amplifying module of the access device amplifies the frequency signal input by the clock source, and the frequency signal is tapped and output to the frequency loop terminals of the M output ports and transmitted to downstream equipment.
1.10 The frequency signal amplifying module of the tapping device amplifies the frequency signal input from the upstream, taps and outputs the frequency signal to the frequency loop terminals of the N output ports, and transmits the frequency signal to downstream equipment.
1.11 The frequency signal amplifying module of the transmission sensor amplifies the frequency signal input from the upstream, and the frequency signal is tapped and output to the frequency loop terminals of the P output ports and transmitted to downstream equipment.
1.12 The frequency signal frequency multiplication module of the terminal card multiplies the frequency signal input upstream and outputs the frequency signal to the high-speed counter; if the frequency signal doubling module can not detect the upstream input frequency signal for a period of time, the disconnection warning sign is output to the outside through the disconnection sign output port.
2) Measuring path delay
2.1 Time sequence control module of the access device, at the time signal pulse front edge t B After a period of time (T H ＜t B Less than T), controlling M shorting switches to be converted into a shorting state, and waiting for turning back a delay measurement signal sent by downstream equipment; the duration time of the M short-circuit switches in the on state is t A +t B Duration of time in short circuit state is T D ＝T-t A -t B 。
2.2 A time sequence control module of the tapping device, at the front edge t of the time signal pulse B After the duration, controlling the selection switch to a branch where the isolating switch is located, controlling the N short-circuit switches to switch to a short-circuit state, and waiting for turning back a delay measurement signal sent by downstream equipment; the duration time of the N short-circuit switches in the on state is t A +t B Duration of time in short circuit state is T D ＝T-t A -t B 。
2.3 Duration T of time the shorting switch of the access and tap is in the shorted state D Equally divided into V time slots, wherein the sizes of the time slots are delta; lower limit delta of slot size delta min The delay signal may be allowed to round trip with a path length R; if the transmission rate of the time signal in the line is c', Δ min =2·r/c', and Δ min ≤Δ＜T D ，Wherein->Is taken downwardsPerforming integer operation;
delay signal generating module of tapping device and terminal card, at time signal pulse front edge t X After the duration, respectively controlling the isolating switches of the tapping device or the terminal card to be in a conducting state, respectively sending delay measurement signals, and triggering to start measuring time intervals along the time loop of the tapping device or the terminal card, through the isolating switches, and then through the selecting switches, transmitting to the upstream, and simultaneously respectively reaching the time interval measuring modules of the tapping device or the terminal card; wherein t is X ＝t B +i.delta, i e {0,1,..v-1 } represents the slot number assigned to the tap or termination card;
if multiple taps and/or terminal cards are connected to different output ports of the same pass-through sensor or to different output ports of several pass-through sensors in cascade, the multiple taps and/or terminal cards need to be provided with different t X The value (corresponding to different time slot numbers i) respectively occupies different time slots, and transmits a delay measurement signal to the upstream in a time-sharing way;
if multiple taps and/or terminal cards are each directly connected to a different output port of the access, or to a different output port of the same or different other taps, or to a different output port of the access or other taps via different pass-through sensors, then t of the multiple taps and/or terminal cards X The values are not associated.
2.4 The delay signal is transmitted upstream along the time loop (possibly through 0 or a plurality of through sensors), finally reaches the short-circuit switch of the corresponding output port of the nearest upstream tapping device or the access device, and the short-circuit switch is in a short-circuit state at the moment, so that the delay signal is folded back to the time interval measuring module (possibly through 0 or a plurality of through sensors) of the tapping device or the terminal card, the end measuring time interval is triggered, the round trip path delay is measured, and the round trip delay is output to the time code signal processing module of the tapping device or the terminal card.
2.5 The delay signal generating module of the tapping device and the terminal card controls the duration of the on state of the isolating switch to be a time slot delta, and controls the isolating switch to be in the off state in other periods.
2.6 The time signal bidirectional amplifying module of the sensor amplifies both the delay measurement signal sent by the downstream equipment to the upstream equipment and the delay measurement signal returned by the upstream equipment to the downstream equipment.
3) Output clock count and status flags
3.1 The high-speed counter of the terminal card counts the frequency multiplication signals input by the frequency signal multiplication module, and the count value t C Stored in its internal register, each frequency doubling signal period triggers a count value t C 1 is added. The high-speed counter counts the value t C Output to the count correction module and output to the outside through the clock count output port, which is the digitized clock count value finally output by the terminal card.
3.2 Inputs to the count correction module of the terminal card include:
i) A time signal output by the time signal amplifying module;
ii) a time code value t which is output by the time code signal processing module and indicates UTC seconds or TAI seconds of the current international coordination time or international atomic time N ；
iii) A path delay value D output by the time code signal processing module, which is the total path delay from the terminal card to the access device;
iv) the clock count value t output by the high-speed counter C ；
The leading edge trigger count correction module of the time signal pulse calculates the time signal value t after compensating the total path delay N′ And frequency multiplication signal clock count t C Deviation epsilon=t N′ -t C Wherein t is N′ ＝t N +D+T is the time code value corresponding to the next period of the time signal pulse after compensating the total path delay; the counting correction module outputs a deviation value epsilon from a counting deviation output port to the outside; if ε exceeds a predetermined limit and t N′ ＞t C The count value t of the internal register of the high-speed counter is calculated C Reset to t N′ And the reset count alert flag is output to the outside by the reset count flag output port.
The beneficial effects are that: compared with the prior art, the invention uses the special network to transmit clock signals in the computer cluster, and does not need to upgrade data transmission network equipment; the invention generates the signal for measuring the path delay by the special module, measures the path delay in the low level period of the time signal, and divides different time slots for measurement by a plurality of slave ends if necessary, thereby being more flexible; the invention adopts the tapping device and the transmission device, and is suitable for being expanded to large-scale computer clusters; the invention encodes the path delay value, transmits the path delay value together with the code at any time, and finally compensates the delay of the time signal through numerical calculation, thereby simplifying the system; in addition, the historical change trend of the path delay can be used as a reference for analyzing the path reliability, and the reliability of the system is improved.
Drawings
FIG. 1 is a schematic diagram of a system for transferring clock signals in a computer cluster according to the present invention;
FIG. 2 is a schematic diagram of an access device of the present invention;
FIG. 3 is a schematic view of a tap of the present invention;
FIG. 4 is a schematic diagram of a permeant sensor of the present invention;
FIG. 5 is a schematic diagram of a terminal card of the present invention;
FIG. 6 is a schematic diagram of the timing of the frequency signal, time code signal and shorting switch operation of the present invention;
fig. 7 is a schematic diagram of a shorting switch according to an embodiment of the invention.
Detailed Description
The present invention is further illustrated below in conjunction with specific embodiments, it being understood that these embodiments are meant to be illustrative of the invention only and not limiting the scope of the invention, and that modifications of the invention, which are equivalent to those skilled in the art to which the invention pertains, will fall within the scope of the invention as defined in the claims appended hereto.
In this embodiment, a system for transmitting clock signals in a computer cluster, as shown in fig. 1, includes a clock source 1, an access unit 2, a tap unit 3, a pass-through unit 4, a terminal card 5 and a cable line.
The access unit 2, the tapping unit 3, the pass-through unit 4, the terminal card 5 and the cable lines form a tree-shaped clock signal transmission network. An access device 2 as a root node; a plurality of terminal cards 5 are used as leaf nodes; using 0 or a plurality of taps 3 and 0 or a plurality of pass-through sensors 4 as intermediate nodes; the clock signal output by the clock source 1 is accessed into a network by an access device, and is transmitted to a terminal card 5 of a leaf node through 0 or a plurality of tapping devices 3 and 0 or a plurality of intermediate nodes of a transmission device 4;
the tree clock signal transmission network uses a separated time loop, a time code loop and a frequency loop to jointly transmit a complete clock signal;
(1) The clock source 1 is an atomic clock that is driven by a GNSS signal, and the output clock signal includes a 1 PPS Time signal, a Time code signal in a coding format of Day (ToD) format, IRIG-B format, or NTP format, and a 10MHz sinusoidal frequency signal.
(2) As shown in fig. 2, the access device 2 includes a time signal amplifying module 2-1, M shorting switches 2-2 (M is a positive integer representing the number of output ports), M output ports 2-3, a timing control module 2-4, a time code signal converting module 2-5, and a frequency signal amplifying module 2-6; the input clock signal of the access device 2 comes from the output port of the clock source 1;
the input of the time signal amplifying module 2-1 is connected with a time loop of an input clock signal, the output of the time signal amplifying module is tapped into M paths, and the M paths are respectively output to time loop terminals of M output ports 2-3 through M shorting switches 2-2; the lines of the time signal amplifying modules 2-1 to M shorting switches 2-2 are equal in length; the control signals of the M shorting switches 2-2 are all from the time sequence control module 2-4;
the input of the time code signal conversion module 2-5 is connected with a time code loop of an input clock signal, and the time code loop is tapped and output to the time code loop terminals of the M output ports 2-3;
the input of the frequency signal amplifying module 2-5 is connected with a frequency loop of an input clock signal, and the frequency loop is tapped and output to the frequency loop terminals of the M output ports 2-3;
The M output ports 2-3 comprise three separated loop output terminals of a time loop, a time code loop and a frequency loop, so as to form M complete clock signals; the downstream device of each output port 2-3 of the access 2 may be any of the tap 3, pass through sensor 4 or end card 5.
(3) As shown in fig. 3, the tap 3 includes a time signal amplifying module 3-1, N shorting switches 3-2 (N is a positive integer indicating the number of output ports), N output ports 3-3, a timing control module 3-4, a time code signal processing module 3-5, a frequency signal amplifying module 3-6, a time interval measuring module 3-7, a delay signal generating module 3-8, a selection switch 3-9 and an isolating switch 3-10; the input clock signal of the tap 3 may come from any output port of the access 2, pass-through 4 or other tap 3;
the input of the time signal amplifying module 3-1 is connected with a time loop of an input clock signal through the selection switch 3-9, the output is tapped into N paths, and the N paths are respectively output to the time loop terminals of N output ports 3-3 through N short-circuit switches 3-2; the lines of the time signal amplifying modules 3-1 to N short-circuit switches 3-2 are equal in length; the control signals of the selection switch 3-9 and the N shorting switches 3-2 are all from the time sequence control module 3-4;
The input of the time code signal processing module 3-5 is connected with a time code loop of an input clock signal, and the time code loop is tapped and output to the time code loop terminals of the N output ports 3-3;
the input of the frequency signal amplifying module 3-6 is connected with a frequency loop of an input clock signal, and the frequency loop is tapped and output to the frequency loop terminals of the N output ports 3-3;
the input of the time interval measuring module 3-7 is connected with a time loop of an input clock signal through the isolating switch 3-10 and then through the selecting switch 3-9, and the time loop is output to the time code signal processing module 3-5;
the output of the delay signal generating module 3-8 is connected with a time loop of an input clock signal through the isolating switch 3-10 and the selecting switch 3-9;
the control signal of the isolating switch 3-10 comes from the delay signal generating module 3-8;
the N output ports 3-3 comprise three separated loop output terminals of a time loop, a time code loop and a frequency loop, so as to form N complete clock signals; the downstream device of each output port 3-3 of tap 3 may be any one of the pass through sensors 4, end cards 5 or other taps 3.
(4) As shown in fig. 4, the transmission device 4 includes a time signal bidirectional amplifying module 4-1, P output ports 4-2 (P is a positive integer indicating the number of output ports), a time code signal amplifying module 4-3, and a frequency signal amplifying module 4-4; the input clock signal of the pass-through device 4 may come from any output port of the access device 2, the tap device 3 or other pass-through devices 4;
The input of the time signal bidirectional amplifying module 4-1 is connected with a time loop of an input clock signal, and the time loop is tapped and output to the time loop terminals of the P output ports 4-2;
the input of the time code signal amplifying module 4-3 is connected with a time code loop of an input clock signal, and the time code loop is tapped and output to the time code loop terminals of the P output ports 4-2;
the input of the frequency signal amplifying module 4-4 is connected with a frequency loop of an input clock signal, and the frequency loop is tapped and output to the frequency loop terminals of the P output ports 4-2;
the P output ports 4-2 comprise three separated loop output terminals of a time loop, a time code loop and a frequency loop, so that P complete clock signals are formed; the downstream device of each output port 4-2 of the pass-through sensor 4 may be any one of the tap 3, the termination card 5 or other pass-through sensor 4.
(5) As shown in fig. 5, the terminal card 5 includes a time signal amplifying module 5-1, a count correcting module 5-3, a time code signal processing module 5-4, a frequency signal multiplying module 5-5, a high-speed counter 5-7, a time interval measuring module 5-6, a delay signal generating module 5-2, a timing control module 5-8, a selection switch 5-9, a disconnecting switch 5-10, a reset count flag output port 5-11, a count deviation output port 5-12, a path delay output port 5-13, a clock count output port 5-14, and a disconnection flag output port 5-15; the input clock signal of the terminal card 5 may come from any one of the output ports of the access device 2, the tap device 3 or the pass-through device 4;
The input of the time signal amplifying module 5-1 is connected with a time loop of an input clock signal through the selection switch 5-9 and is output to the counting correcting module 5-3; the control signal of the selection switch 5-9 comes from the time sequence control module 5-8;
the input of the time code signal processing module 5-4 is connected with a time code loop of an input clock signal, outputs a time code value and a path delay value to the counting correction module 5-3, and outputs the path delay value to the outside through the path delay output port 5-13;
the input of the frequency signal doubling module 5-5 is connected with a frequency loop of an input clock signal and outputs the frequency loop to the high-speed counter 5-7; the frequency signal doubling module 5-5 also outputs a disconnection warning sign to the outside through the disconnection sign output port 5-15;
the high-speed counter 5-7 counts the frequency multiplication signal, outputs the frequency multiplication signal to the count correction module 5-3, receives the set value of the count correction module 5-3, and outputs the final clock count to the outside through the clock count output port 5-14;
the input of the time interval measuring module 5-6 is connected with a time loop of an input clock signal through the isolating switch 5-10 and then through the selecting switch 5-9, and the time loop is output to the time code signal processing module 5-4;
the output of the delay signal generating module 5-2 is connected with a time loop of an input clock signal through an isolating switch 5-10 and a selecting switch 5-9;
The control signal of the isolating switch 5-10 comes from the delay signal generating module 5-8;
the counting correction module 5-3 receives the time signal output by the time signal amplification module 5-1, the time code value and the path delay value output by the time code signal processing module 5-4 and the frequency multiplication signal count value output by the high-speed counter 5-7, and the offset value of the time code value and the frequency multiplication signal count value after the compensation path delay is output to the outside through the counting offset output port 5-12; when the deviation exceeds a predetermined limit value, a set value is output to the high-speed counter 5-7, and a reset count alarm flag is output to the outside through the reset count flag output port 5-11.
(6) The number M of output ports of the access unit 2, the number N of output ports of the tapping unit 3, and the number P of output ports of the pass-through unit 4 are used only for distinguishing the three types of equipment, and the number M, N and P may be the same or different; the docking unit 2, tapping unit 3 and pass-through unit 4 may all be configured with different numbers of output ports for the same device.
A method of delivering a clock signal in a computer cluster, comprising the steps of:
1) Delivering clock signals
1.1 Timing control module 2-4 of the access device 2, leading the time signal pulse leading edge t A Duration (0 < t) A ＜T L ) Controlling M shorting switches 2-2 to be switched to a conducting state; the time signal amplifying module 2-4 of the access device 2 amplifies the time signal input by the clock source and adjusts the duty ratio of the time signal pulse (without changing the leading edge of the pulse) to make the duration of the high level be T H The duration of the low level is T L Wherein T is H +T L =1s, i.e. the period of the time signal; the output of the time signal amplifying module 2-1 is tapped into M paths, and the M paths are respectively output to the time loop terminals of the M output ports 2-3 through M short-circuit switches 2-2, so that time signals are transmitted to downstream equipment;
1.2 Timing control module 3-4 of tap 3, leading the time signal pulse front t A The duration controls the selection switch 3-9 to switch to the branch where the time signal amplifying module 3-1 is located, and controls the N short-circuit switches 3-2 to switch to the conducting state; the time signal amplifying module 3-1 amplifies the time signal input from the upstream, the output is tapped into N paths, and the N paths are respectively output to the time loop terminals of the N output ports 3-3 through the N short-circuit switches 3-2, so that the time signal is transmitted to downstream equipment;
1.3 A time signal bidirectional amplifying module 4-1 of the transmission sensor 4 amplifies an upstream input time signal, and the time signal is tapped and output to a time loop terminal of the P output ports 4-2 and transmitted to downstream equipment;
1.4 Timing control module 5-8 of the terminal card 5, leading the time signal pulse leading edge t A The duration controls the selection switch 5-9 to switch to the branch where the time signal amplifying module 5-1 is located; the time signal amplifying module 5-1 amplifies the time signal input upstream and outputs the time signal to the counting correcting module 5-3, and the counting correcting module is triggered by the pulse leading edge;
1.5 The time code signal conversion module 2-5 of the access device 2 decodes the time code signal input by the clock source, recodes the time code signal into the coding format adopted by the invention, and outputs the code signal to the time code loop terminals of the M output ports 2-3 in a tapping way to be transmitted to downstream equipment; for the convenience of calculation, the invention converts the time code format of the clock source into an integer number;
1.6 Divided into (a) partsThe time code signal processing module 3-5 of the connector 3 decodes the time code signal input upstream and reads the time code value t N And a series of path delay values D k ，D k-1 ...D 1 Where k is the number of other taps 3 in the path from the current tap 3 to the access 2; d (D) i Is the total path delay of the j-th tap 3 to the access 2 in the path, j e {1,2,., k }; the number j starts from the tap 3 directly connected with the access device 2 to be 1 st, and the number j of the downstream tap 3 is increased step by step; the number j is used only to describe the series of path delay values D k ，D k-1 ...D 1 Is a sequence of (2); if there is no tap 3 in the upstream path, k=0, and the series path delay values in the time code signal are all 0;
the time code signal processing module 3-5 reads the round trip path delay value d output by the time interval measuring module 3-7; based on the assumption of round-trip path symmetry, the path delay is half the round-trip path delay value d; the time code signal processing module 3-5 calculates the total path delay value D of the current tap 3 to the access device 2 k+1 ＝d/2+D k Time code value t N And a series of path delay values D k+1 ，D k ，D k-1 ...D 1 The processed time code signal is tapped to the time code loop terminals of the N output ports 3-3 and transmitted to downstream equipment;
1.7 The time code signal amplifying module 4-3 of the transmission sensor 4 amplifies the time code signal input from the upstream, and the time code signal is tapped and output to the time code loop terminals of the P output ports 4-2 and transmitted to downstream equipment;
1.8 A time code signal processing module 5-4 of the terminal card 5 decodes the time code signal inputted upstream, reads the time code value t N And a series of path delay values D k′ ，D k′-1 ...D 1 Where k' is the number of taps 3 in the path from the current terminal card 5 to the access 2; d (D) j Is the total path delay of the j-th tap 3 to the access 2 in the path, j e {1,2,., k' }; the number j starts from the tap 3 directly connected with the access device 2 to be 1 st, and the number j of the downstream tap 3 is increased step by step; the number j is used only to describe the series of path delay values D k′ ，D k′-1 ...D 1 Is a sequence of (2);if there is no tap 3 in the upstream path, k' =0, and the serial path delay values in the time code signal are all 0;
the time code signal processing module 5-4 reads the round trip path delay value d' of the time interval measuring module output 5-6; based on the assumption of round-trip path symmetry, the path delay is half the round-trip path delay value d'; the time code signal processing module 5-6 calculates the total path delay value D from the current terminal card 5 to the access device 2 k′+1 ＝d′/2+D k′ The time code value t N And total path delay D k′+1 Output to the count correction module 5-3; outputting a series of path delay values D from the path delay output ports 5-13 to the outside k′+1 ，D k′ ，D k′-1 ...D 1 ；
1.9 The frequency signal amplifying module 2-6 of the access device 2 amplifies the frequency signal input by the clock source, and the frequency signal is tapped and output to the frequency loop terminals of the M output ports 2-3 and transmitted to downstream equipment;
1.10 The frequency signal amplifying module 3-6 of the tapping device 3 amplifies the frequency signal input from upstream, taps and outputs the frequency signal to the frequency loop terminals of the N output ports 3-3, and transmits the frequency signal to downstream equipment;
1.11 The frequency signal amplifying module 4-4 of the transmission sensor 4 amplifies the frequency signal input from upstream, and the frequency signal is tapped and output to the frequency loop terminals of the P output ports 4-2 and transmitted to downstream equipment;
1.12 The frequency signal frequency multiplication module 5-5 of the terminal card 5 multiplies the frequency signal input upstream and outputs the frequency signal to the high-speed counter 5-7; if the frequency signal doubling module 5-5 can not detect the upstream input frequency signal for a period of time, the disconnection warning sign is output to the outside through the disconnection sign output port 5-15.
2) Measuring path delay
2.1 A timing control module 2-4 of the access device 2, at the time signal pulse leading edge t B After a period of time (T H ＜t B Less than T), controlling M shorting switches 2-2 to be converted into a shorting state, and waiting for turning back a delay measurement signal sent by downstream equipment; the duration of the conduction state of the M shorting switches 2-2 is t A +t B Duration in short-circuited stateCo T D ＝T-t A -t B ；
2.2 A timing control module 3-4 of the tap 3 at the time signal pulse front t B After the duration, controlling the selection switch 3-9 to switch to a branch where the isolation switch 3-10 is located, controlling the N short-circuit switches 3-2 to switch to a short-circuit state, and waiting for turning back a delay measurement signal sent by downstream equipment; the duration of the N shorting switches 3-2 in the conducting state is t A +t B Duration of time in short circuit state is T D ＝T-t A -t B ；
2.3 Duration T of time that shorting switches 2-2 and 3-2 of access device 2 and tap device 3 are in a shorted state D Equally divided into V time slots, wherein the sizes of the time slots are delta; lower limit delta of slot size delta min The delay signal may be allowed to round trip with a path length R; if the transmission rate of the time signal in the line is c', Δ min =2·r/c', and Δ min ≤Δ＜T D ，Wherein->Is a downward rounding operation; for example, if the longest path r=2 km, taking the speed of light in the line c' =2×10 in consideration of the speed of the electrical signal in the wire being slower than the speed of light in the vacuum 8 m/s, then Δ=2·r/c' =20μs, then a time interval of 1ms (1000 μs) may be divided into 50 slots. If T is taken D =900 ms, then v=900×50=45000 slots can be divided;
delay-detection signal generation modules 3-8 and 5-2 of the tap 3 and the terminal card 5 at the time signal pulse leading edge t X After the time length, the isolating switches 3-10 or 5-10 of the tapping device 3 or the terminal card 5 are respectively controlled to be in a conducting state, and respectively send a measurement delay signal, and the signals are transmitted upstream along the time loop of the tapping device 3 or the terminal card 5 through the isolating switches 3-10 or 5-10 and then through the selecting switches 3-9 or 5-9, and simultaneously reach the time interval measuring modules 3-7 or 5-6 of the tapping device 3 or the terminal card 5 respectively, when the measurement is triggered to startAn interval; wherein t is X ＝t B +i·Δ, i e {0,1,..v-1 } represents the slot number assigned to tap 3 or terminal card 5;
if multiple taps 3 and/or terminal cards 5 are connected to different output ports 4-2 of the same through-sensor 4 or to different output ports 4-2 of several through-sensors 4 in cascade, the multiple taps 3 and/or terminal cards 5 need to be set with different t X The value (corresponding to different time slot numbers i) respectively occupies different time slots, and transmits a delay measurement signal to the upstream in a time-sharing way;
if a plurality of taps 3 and/or terminal cards 5 are each connected directly to a different output port 2-3 of the access 2, or to a different output port 3-2 of the same or different other taps 3, or to a different output port 2-3 or 3-3 of the access 2 or other taps 3 via a different pass-through sensor 4, then t of the plurality of taps 3 and/or terminal cards 5 X The values are not associated;
2.4 The delay signal is transmitted upstream along the time loop (possibly through 0 or more through sensors 4), finally reaches the short-circuit switch 3-2 or 2-2 of the corresponding output port 3-3 or 2-3 of the nearest upstream tapping device 3 or the access device 2, at this time, the short-circuit switch 3-2 or 2-2 is in a short-circuit state, the delay signal is folded back to the time interval measuring module 3-7 or 5-6 (possibly through 0 or more through sensors 4) of the tapping device 3 or the terminal card 5, the end measuring time interval is triggered, the round trip path delay is measured, and the delay signal is output to the time code signal processing module 3-5 or 5-4 of the tapping device 3 or the terminal card 5;
2.5 The delay signal generating modules 3-8 and 5-2 of the tap 3 and the terminal card 5 control the time duration of the on state of the disconnectors 3-10 and 5-10 to be a time slot delta, and control the disconnectors 3-10 and 5-10 to be in the off state in other periods;
2.5 The time signal bidirectional amplification module 4-1 of the pass sensor 4 amplifies both the delay measurement signal sent by the downstream device to the upstream device and the delay measurement signal returned by the upstream device to the downstream device.
3) Output clock count and status flags
3.1 A high-speed counter 5-7 of the terminal card 5 inputs to the frequency signal multiplying module 5-5Is counted by the frequency multiplication signal of (1), the count value t C Stored in its internal register, each frequency doubling signal period triggers a count value t C 1 is added. The high-speed counter 5-7 counts the value t C Output to the count correction module 5-3 and output to the outside through the clock count output port 5-14, which is the digitized clock count value finally output by the terminal card 5; the period of the multiplied signal determines the resolution of the output clock count. After 100 times of frequency signals of 10MHz, obtaining frequency-multiplied frequency signals of 1GHz, wherein the period is 1ns, namely the counting resolution of an output clock is 1ns;
3.2 Inputs to the count correction module 5-3 of the terminal card 5 include:
i) A time signal outputted from the time signal amplifying module 5-1;
ii) a time code value t indicating UTC seconds at the current international coordination time or TAI seconds at the international atomic time outputted by the time code signal processing module 5-4 N ；
(5) The path delay value D output by the time code signal processing module 5-4, which is the total path delay from the terminal card 5 to the access device 2;
iv) the clock count value t output by the high-speed counter 5-7 C ；
The leading edge trigger count correction module 5-3 of the time signal pulse calculates the time signal value t after compensating the total path delay N′ And frequency multiplication signal clock count t C Deviation epsilon=t N′ -t C Wherein t is N′ ＝t N +D+T is the time code value corresponding to the next period of the time signal pulse after compensating the total path delay. The count correction module 5-3 outputs a count deviation value epsilon from the count deviation output port 5-12 to the outside; if ε exceeds a predetermined limit and t N′ ＞t C The count value t of the internal register of the high-speed counter 5-7 is counted C Reset to t N′ And outputs a reset count alarm flag to the outside through the reset count flag output ports 5-11.

Claims (9)

1. A system for delivering clock signals in a computer cluster, comprising: the system comprises a clock source, an access device, 0 or a plurality of tapping devices, 0 or a plurality of through sensors, a terminal card and a circuit; the access device, the 0 or a plurality of tapping devices, the 0 or a plurality of through sensors, the terminal card and the circuit form a tree-shaped clock signal transmission network; the access device is used as a root node; a plurality of terminal cards are used as leaf nodes; taking 0 or a plurality of tapping devices and 0 or a plurality of penetrating sensors as intermediate nodes; the clock signal output by the clock source is accessed into the clock signal transmission network by an access device, and is transmitted to a terminal card of a leaf node through 0 or a plurality of tapping devices and 0 or a plurality of sensor intermediate nodes;
the tapping device amplifies or processes clock signals transmitted by upstream equipment and taps the clock signals to a plurality of downstream equipment; during the low level of the time signal, the tap device measures the round trip path delay of the nearest other upstream tap device or the access device by using a foldback method, and the round trip path delay and the time code are transmitted to downstream equipment together; during the low level of the time signal, the tap returns a delay measurement signal sent by downstream equipment; the number of downstream devices to which the tap outputs can be connected is limited only by the number of tap output ports, and the number limitation of the downstream devices is expanded through cascading taps;
The transparent sensor amplifies clock signals transmitted by upstream equipment and is connected to a plurality of downstream equipment in a tapping way; during a low level of the time signal, the pass-through sensor amplifies a delay measurement signal transmitted from the downstream device to the upstream device in a time-sharing manner and amplifies the delay measurement signal returned from the upstream device; the number of downstream devices that can be connected by the pass-through sensor output is limited by the number of time slots of the measured path delay, and the number limitation of the downstream devices cannot be expanded by cascading only the pass-through sensors;
a plurality of terminal cards receive clock signals transmitted by upstream equipment; during the low level of the time signal, the terminal card measures the round trip path delay of the nearest upstream tapping device or the access device by using a foldback method, compensates the total path delay by numerical calculation, outputs a clock count value, and finally realizes clock signal transmission.
2. A system for delivering clock signals in a computer cluster as recited in claim 1, wherein: the tree clock signal transmission network uses a separated time loop, a time code loop and a frequency loop to jointly transmit a complete clock signal; the access device amplifies or converts the time signal, the time code signal and the frequency signal output by the clock source; the clock signal output port of the clock source is composed of loop terminals of a time signal, a time code signal and a frequency signal which are separated.
3. A system for delivering clock signals in a computer cluster as recited in claim 1, wherein: the access device comprises a time signal amplifying module, M short-circuit switches, M output ports, a time sequence control module, a time code signal conversion module and a frequency signal amplifying module; the input clock signal of the access device comes from the output port of the clock source;
the input of the time signal amplifying module is connected with the time loop of the input clock signal, the output of the time signal amplifying module is tapped into M paths, and the M paths are respectively output to the time loop terminals of M output ports through M shorting switches; the lines from the time signal amplifying module to the M short-circuit switches are equal in length; the control signals of the M shorting switches are all from the time sequence control module;
the input of the time code signal conversion module is connected with a time code loop of the input clock signal, and the time code loop is tapped and output to the time code loop terminals of the M output ports;
the input of the frequency signal amplifying module is connected with the frequency loop of the input clock signal, and the frequency loop is tapped and output to the frequency loop terminals of the M output ports;
the M output ports comprise three separated loop output terminals of a time loop, a time code loop and a frequency loop, and M complete clock signals are formed; the downstream device of each output port of the access device is any one of a tap, a pass-through or a terminal card.
4. A system for delivering clock signals in a computer cluster as recited in claim 1, wherein: the tapping device comprises a time signal amplifying module, N short-circuit switches, N output ports, a time sequence control module, a time code signal processing module, a frequency signal amplifying module, a time interval measuring module, a delay signal generating module, a selecting switch and an isolating switch; the input clock signal of the tap-off device is from any output port of the access device, the transmission device or other tap-off devices;
the input of the time signal amplifying module is connected with a time loop of the input clock signal through a selection switch, the output of the time signal amplifying module is tapped into N paths, and the N paths are respectively output to time loop terminals of N output ports through N shorting switches; the lines from the time signal amplifying module to the N short-circuit switches are equal in length; control signals of the selection switch and the N short-circuit switches are all from the time sequence control module;
the input of the time code signal processing module is connected with a time code loop of the input clock signal, and the time code loop terminal of the N output ports is tapped and output;
the input of the frequency signal amplifying module is connected with the frequency loop of the input clock signal, and the frequency loop is tapped and output to the frequency loop terminals of the N output ports;
The input of the time interval measurement module is connected with a time loop of the input clock signal through an isolating switch and then through a selecting switch, and the time loop is output to the time code signal processing module;
the output of the delay signal generating module is connected with the time loop of the input clock signal through an isolating switch and a selecting switch;
the control signal of the isolating switch is from the delay measurement signal generating module;
the N output ports comprise three separated loop output terminals of a time loop, a time code loop and a frequency loop, and form N complete clock signals; the device downstream of each output port of the tap is any one of a pass-through, termination card or other tap.
5. A system for delivering clock signals in a computer cluster as recited in claim 1, wherein: the transmission sensor comprises a time signal bidirectional amplifying module, P output ports, a time code signal amplifying module and a frequency signal amplifying module; the input clock signal of the transsensor is from any output port of an access device, a tapping device or other transsensor;
the input of the time signal bidirectional amplifying module is connected with the time loop of the input clock signal, and the time loop terminal of the P output ports is tapped and output;
The input of the time code signal amplifying module is connected with a time code loop of the input clock signal, and the time code loop terminal of the P output ports is tapped and output;
the input of the frequency signal amplifying module is connected with the frequency loop of the input clock signal, and the frequency loop is tapped and output to the frequency loop terminals of the P output ports;
the P output ports comprise three separated loop output terminals of a time loop, a time code loop and a frequency loop, and P complete clock signals are formed; the downstream device of each output port of the pass-through sensor is any tap, termination card or other pass-through sensor.
6. A system for delivering clock signals in a computer cluster as recited in claim 1, wherein: the terminal card comprises a time signal amplifying module, a counting correction module, a time code signal processing module, a frequency signal doubling module, a high-speed counter, a time interval measuring module, a delay signal generating module, a time sequence control module, a selection switch, an isolating switch, a reset counting sign output port, a counting deviation output port, a path delay output port, a clock counting output port and a disconnection sign output port; the input clock signal of the terminal card comes from any output port of an access device, a tapping device or a transom device;
The input of the time signal amplifying module is connected with a time loop of the input clock signal through a selection switch and is output to the counting correcting module; the control signal of the selection switch comes from the time sequence control module;
the input of the time code signal processing module is connected with a time code loop of the input clock signal, the time code value and the path delay value are output to the counting correction module, and the path delay value is output to the outside through a path delay output port;
the input of the frequency signal doubling module is connected with the frequency loop of the input clock signal and outputs the frequency loop to the high-speed counter; the frequency signal frequency multiplication module also outputs a disconnection warning mark to the outside through a disconnection mark output port;
the high-speed counter counts the frequency multiplication signals, outputs the frequency multiplication signals to the counting correction module, receives the set value of the counting correction module, and outputs the final clock count to the outside through the clock counting output port;
the input of the time interval measurement module is connected with a time loop of the input clock signal through an isolating switch and then through a selecting switch, and the time loop is output to the time code signal processing module;
the output of the delay signal generating module is connected with the time loop of the input clock signal through an isolating switch and a selecting switch;
The control signal of the isolating switch is from the delay measurement signal generating module;
the counting correction module receives the time signal output by the time signal amplification module, the time code value and the path delay value output by the time code signal processing module and the frequency multiplication signal count value output by the high-speed counter, and the offset value of the time code value and the frequency multiplication signal count value after compensating the path delay is output to the outside through the counting offset output port; when the deviation exceeds a preset limit value, outputting a set value to the high-speed counter, and outputting a reset count alarm mark to the outside through a reset count mark output port;
the number M of the output ports of the access device, the number N of the output ports of the tapping device and the number P of the output ports of the transmission device are only used for distinguishing the number of the output ports of three devices, and the number M, N and the number P of the output ports of the three devices can be the same or different; the same equipment has different configurations of the number of output ports for the access device, the tapping device and the pass-through device.
7. A method of delivering a clock signal in a computer cluster, comprising the steps of:
1) Delivering clock signals
1.1 Timing control module of access device, leading the time signal pulse front edge t A Duration (0)<t A <T L ) Controlling M shorting switches to be switched to a conducting state; the time signal amplifying module of the access device amplifies the time signal input by the clock source and adjusts the duty ratio of the time signal pulse to make the duration of the high level be T H The duration of the low level is T L Wherein T is H +T L T is the period of the time signal; the output of the time signal amplifying module is divided into M paths, and the M paths are respectively output to time loop terminals of M output ports through M short-circuit switches, so that time signals are transmitted to downstream equipment;
1.2 Timing control module of tapping device, leading time signal pulse front edge t A The time length controls the time signal amplifying module of the selection switch to the branch circuit of the tapping device, and controls N short-circuit switches to switch to a conducting state; the time signal amplifying module amplifies an upstream input time signal, the output is tapped into N paths, the N paths are respectively output to time loop terminals of N output ports through N short-circuit switches, and the time signal is transmitted to downstream equipment;
1.3 A time signal bidirectional amplifying module of the transmission sensor amplifies an upstream input time signal, and the time signal is tapped and output to a time loop terminal of P output ports and is transmitted to downstream equipment;
1.4 Timing control module of terminal card, leading time signal pulse front edge t A The duration controls the selection switch to the branch where the time signal amplifying module is located; the time signal amplifying module amplifies an upstream input time signal, outputs the time signal to the counting correcting module and triggers counting correction by a pulse front edge;
1.5 The time code signal conversion module of the access device decodes the time code signal input by the clock source, recodes the time code signal, taps the time code loop terminals output to M output ports and transmits the time code loop terminals to downstream equipment;
1.6 A time code signal processing module of the tapping device decodes the time code signal input from the upstream, reads the time code value and a series of path delay values; reading a round trip path delay value output by the time interval measurement module; calculating the total path delay value from the current tapping device to the access device, wherein the time code value and the series path delay value are processed time code signals, and tapping the processed time code signals to the time code loop terminals of N output ports for transmission to downstream equipment;
1.7 A time code signal amplifying module of the transmission sensor amplifies the time code signals input from the upstream, and the time code signals are tapped and output to the time code loop terminals of the P output ports and transmitted to downstream equipment;
1.8 The time code signal processing module of the terminal card decodes the time code signal input from the upstream, reads the time code value and a series of path delay values, and reads the round trip path delay value output by the time interval measuring module; calculating the total path delay value from the current terminal card to the access device, and outputting the time code value and the total path delay to a counting correction module; outputting a series of path delay values from the path delay output port to the outside;
1.9 The frequency signal amplifying module of the access device amplifies the frequency signal input by the clock source, and the frequency signal is tapped and output to the frequency loop terminals of the M output ports and transmitted to downstream equipment;
1.10 The frequency signal amplifying module of the tapping device amplifies the frequency signal input from the upstream, taps and outputs the frequency signal to the frequency loop terminals of the N output ports, and transmits the frequency signal to downstream equipment;
1.11 The frequency signal amplifying module of the transmission sensor amplifies the frequency signal input from the upstream, and the frequency signal is tapped and output to the frequency loop terminals of the P output ports and transmitted to downstream equipment;
1.12 The frequency signal frequency multiplication module of the terminal card multiplies the frequency signal input upstream and outputs the frequency signal to the high-speed counter; if the frequency signal doubling module can not detect the upstream input frequency signal for a period of time, outputting a disconnection warning sign to the outside through a disconnection sign output port;
2) Measuring path delay
2.1 Time sequence control module of the access device, at the time signal pulse front edge t B After a period of time (T H <t B <T), controlling M shorting switches to be converted into a shorting state, and waiting for turning back a delay measurement signal sent by downstream equipment; the duration time of the M short-circuit switches in the on state is t A +t B Duration of time in short circuit state is T D ＝T-t A -t B ；
2.2 A time sequence control module of the tapping device, at the front edge t of the time signal pulse B After the duration, controlling the selection switch to a branch where the isolating switch is located, controlling the N short-circuit switches to switch to a short-circuit state, and waiting for turning back a delay measurement signal sent by downstream equipment; the duration time of the N short-circuit switches in the on state is t A +t B Duration of time in short circuit state is T D ＝T-t A -t B ；
2.3 Duration T of time the shorting switch of the access and tap is in the shorted state D Equally divided into V time slots, wherein the sizes of the time slots are delta; lower limit delta of slot size delta min Allowing the delay signal to round trip under the condition of the path length R; if the transmission rate of the time signal in the line is c', Δ min =2·r/c', and Δ min ≤Δ<T D ，Wherein->Is a downward rounding operation;
delay signal generating module of tapping device and terminal card, at time signal pulse front edge t X After the duration, respectively controlling the isolating switches of the tapping device or the terminal card to be in a conducting state, respectively sending delay measurement signals, and triggering to start measuring time intervals along the time loop of the tapping device or the terminal card, through the isolating switches, and then through the selecting switches, transmitting to the upstream, and simultaneously respectively reaching the time interval measuring modules of the tapping device or the terminal card; wherein t is X ＝t B +i.delta, i e {0,1, … V-1} represents the slot number assigned to the tap or termination card;
if multiple taps and/or terminal cards are connected to different output ports of the same transmission device or to different output ports of several transmission devices in cascadeThe ports are then provided with different t's for the multiple taps and/or termination cards X The value occupies different time slots respectively, and a delay measurement signal is sent to the upstream in a time-sharing way;
if multiple taps and/or terminal cards are each directly connected to a different output port of the access, or to a different output port of the same or different other taps, or to a different output port of the access or other taps via different pass-through sensors, then t of the multiple taps and/or terminal cards X The values are not associated;
2.4 The delay signal is transmitted upstream along a time loop, finally reaches a short-circuit switch of a corresponding output port of the nearest upstream tapping device or the access device, and is in a short-circuit state at the moment, so that the delay signal is folded back to a time interval measuring module of the tapping device or the terminal card, the measuring time interval is triggered to be ended, the round trip path delay is measured, and the round trip path delay is output to a time code signal processing module of the tapping device or the terminal card;
2.5 The delay signal generating module of the tapping device and the terminal card controls the duration of the on state of the isolating switch to be a time slot delta, and controls the isolating switch to be in the off state in other periods;
2.6 The time signal bidirectional amplifying module of the sensor amplifies both a delay measurement signal sent by downstream equipment to upstream equipment and a delay measurement signal returned by the upstream equipment to the downstream equipment;
3) Output clock count and status flags
The high-speed counter of the terminal card counts the frequency multiplication signals input by the frequency signal multiplication module, and the count value t C Stored in its internal register, each frequency doubling signal period triggers a count value t C Adding 1; the high-speed counter counts the value t C Output to the count correction module and output to the outside through the clock count output port, which is the digitized clock count value finally output by the terminal card.
8. The method of claim 7, wherein the input of the count rectification block of the terminal card comprises:
i) A time signal output by the time signal amplifying module;
ii) a time code value t which is output by the time code signal processing module and indicates UTC seconds or TAI seconds of the current international coordination time or international atomic time N ；
iii) A path delay value D output by the time code signal processing module, which is the total path delay from the terminal card to the access device;
iv) the clock count value t output by the high-speed counter C ；
The leading edge trigger count correction module of the time signal pulse calculates the time signal value t after compensating the total path delay N′ And frequency multiplication signal clock count t C Deviation epsilon=t N′ -t C Wherein t is N′ ＝t N +D+T is the time code value corresponding to the next period of the time signal pulse after compensating the total path delay; the counting correction module outputs a deviation value epsilon from a counting deviation output port to the outside; if ε exceeds a predetermined limit and t N′ >t C The count value t of the internal register of the high-speed counter is calculated C Reset to t N′ And the reset count alert flag is output to the outside by the reset count flag output port.
9. The method for transmitting clock signals in a computer cluster according to claim 7, wherein the time code signal processing module of the tap decodes the time code signal input upstream, reads the time code value t N And a series of path delay values D k ,D k-1 …D 1 Where k is the number of other taps in the path from the current tap to the access; d (D) j Is the total path delay of the jth tap in the path to the access, j e {1,2, …, k }; the number j starts from a tap directly connected with the access device to be 1 st, and the number j of a downstream tap is increased step by step; the number j is used only to describe the series of path delay values D k ,D k-1 …D 1 Is a sequence of (2); if there is no tap in the upstream path, k=0, and time code signalThe series of path delay values in the numbers are all 0;
the time code signal processing module of the tapping device reads the round trip path delay value d output by the time interval measuring module; based on the assumption of round-trip path symmetry, the path delay is half the round-trip path delay value d; the time code signal processing module calculates the total path delay value D from the current tapping device to the access device k+1 ＝d/2+D k Time code value t N And a series of path delay values D k+1 ,D k ,D k-1 …D 1 The processed time code signals are tapped to the time code loop terminals of N output ports and transmitted to downstream equipment;
the time code signal processing module of the terminal card decodes the upstream input time code signal and reads the time code value t N And a series of path delay values D k′ ,D k′-1 …D 1 Where k' is the number of taps in the path from the current terminal card to the access; d (D) j Is the total path delay of the jth tap in the path to the access device, j e {1,2, …, k ′ -a }; the number j starts from a tap directly connected with the access device to be 1 st, and the number j of a downstream tap is increased step by step; the number j is used only to describe the series of path delay values D k′ ,D k′-1 …D 1 Is a sequence of (2); if no tap is arranged in the upstream path, k' =0, and the series of path delay values in the time code signal are all 0;
The time code signal processing module of the terminal card reads the round trip path delay value d' output by the time interval measuring module; based on the assumption of round-trip path symmetry, the path delay is half the round-trip path delay value d'; the time code signal processing module calculates the total path delay value D from the current terminal card to the access device k′+1 ＝d ′ /2+D k′ The time code value t N And total path delay D k′+1 Outputting to a count correction module; outputting a series of path delay values D from the path delay output port to the outside k′+1 ,D k′ ,D k′-1 …D 1 。
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11599139B1 (en) * 2021-09-03 2023-03-07 Xepic Corporation Limited Dynamic adjustment of root clock frequency in logic system design during verification

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1168793A (en) * 1997-08-20 1999-03-09 Nec Eng Ltd Data transmission system
CN101183244A (en) * 2007-11-29 2008-05-21 中国人民解放军国防科学技术大学 Accurate trigger signal producing method and producing circuit
CN102007696A (en) * 2008-04-14 2011-04-06 高通股份有限公司 Phase to digital converter in all digital phase locked loop
CN110278048A (en) * 2019-04-24 2019-09-24 南京大学 A kind of classification Ad Hoc network method for synchronizing time based on cluster algorithm
CN110673689A (en) * 2019-09-23 2020-01-10 深圳云天励飞技术有限公司 Clock control circuit and method
CN111954298A (en) * 2020-08-25 2020-11-17 电子科技大学 Clock synchronization device and system suitable for millimeter wave radio frequency remote module
CN112055945A (en) * 2018-05-01 2020-12-08 德吉润股份有限公司 System and method for implementing cascaded clock ring buses

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8264397B2 (en) * 2010-10-26 2012-09-11 The United States Of America, As Represented By The Secretary Of The Navy Time transfer method and system

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1168793A (en) * 1997-08-20 1999-03-09 Nec Eng Ltd Data transmission system
CN101183244A (en) * 2007-11-29 2008-05-21 中国人民解放军国防科学技术大学 Accurate trigger signal producing method and producing circuit
CN102007696A (en) * 2008-04-14 2011-04-06 高通股份有限公司 Phase to digital converter in all digital phase locked loop
CN112055945A (en) * 2018-05-01 2020-12-08 德吉润股份有限公司 System and method for implementing cascaded clock ring buses
CN110278048A (en) * 2019-04-24 2019-09-24 南京大学 A kind of classification Ad Hoc network method for synchronizing time based on cluster algorithm
CN110673689A (en) * 2019-09-23 2020-01-10 深圳云天励飞技术有限公司 Clock control circuit and method
CN111954298A (en) * 2020-08-25 2020-11-17 电子科技大学 Clock synchronization device and system suitable for millimeter wave radio frequency remote module

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
A 25-28Gb/s PLL-based Full-Rate Reference-Less CDR in 0.13um Site BiCMOS;Peng Zhang et al.;《IEEE》;全文 *
基于训练方式的存储器时钟信号的自适应同步;陆辰鸿;胡越黎;周俊;;上海大学学报(自然科学版);20150831(第04期);全文 *
规则驱动的Android应用DFS测试技术;张营等;《计算机科学》;全文 *

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