CN109462525A - Clockwork detection system - Google Patents
Clockwork detection system Download PDFInfo
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- CN109462525A CN109462525A CN201811580735.0A CN201811580735A CN109462525A CN 109462525 A CN109462525 A CN 109462525A CN 201811580735 A CN201811580735 A CN 201811580735A CN 109462525 A CN109462525 A CN 109462525A
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- 238000001514 detection method Methods 0.000 title claims abstract description 32
- 238000005259 measurement Methods 0.000 claims abstract description 90
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 23
- 238000003786 synthesis reaction Methods 0.000 claims abstract description 23
- 230000003750 conditioning effect Effects 0.000 claims description 37
- 229910052701 rubidium Inorganic materials 0.000 claims description 21
- IGLNJRXAVVLDKE-UHFFFAOYSA-N rubidium atom Chemical compound [Rb] IGLNJRXAVVLDKE-UHFFFAOYSA-N 0.000 claims description 21
- 238000012545 processing Methods 0.000 claims description 15
- 230000005611 electricity Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 20
- 238000012360 testing method Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000005070 sampling Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
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- 230000001360 synchronised effect Effects 0.000 description 3
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- 230000003068 static effect Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- DMBHHRLKUKUOEG-UHFFFAOYSA-N diphenylamine Chemical compound C=1C=CC=CC=1NC1=CC=CC=C1 DMBHHRLKUKUOEG-UHFFFAOYSA-N 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
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- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
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Abstract
The invention belongs to clock detection technical fields, and in particular to a kind of clockwork detection system, master control borad；Frequency synthesis plate is electrically connected with the master control borad, and the frequency synthesis plate exports required final time frequency signal according to time and frequency standards；Pinboard, the master control borad electrical connection, for realizing the switching of USB and network interface.Time and frequency measurement plate is electrically connected with the master control borad, the frequency synthesis plate, and the time and frequency measurement plate is for measuring a variety of time frequency signals；Power module is electrically connected with the master control borad, the frequency synthesis plate.The present invention provides a kind of clockwork detection system, realizes the measurement of the time accuracy of a variety of time signals.
Description
Technical field
The invention belongs to clock detection technical fields, are specifically related to a kind of clockwork detection system.
Background technique
Railway high-precision, is a kind of portable high-accuracy frequency time signal integral test system.It is various currently on the market
Time and frequency measurement functions of the equipments are relatively simple, and expensive.As survey E1 signal is dedicated E1 signal-testing apparatus；Survey B
Code signal is dedicated B code test equipment；Survey NTP and PTP signal is also dedicated test equipment；Even if there is integrated set
It is standby, two to three kinds of functions can only be also taken into account, price is higher, moreover, the signal kinds that can be tested are limited, integrated level is not high, other
Time-frequency class integrated equipment be mostly used to carry out time service, measure class is mostly the equipment having a single function or board.
So when encountering the occasion of test multi-signal, it is necessary to use multiple equipment, especially outdoors, carry more
A test equipment brings great inconvenience to user.
To solve the above-mentioned problems, the present invention provides a kind of clockwork detection systems, are intelligent substation, high speed
Detection, verification, the examination at the scene such as railway, rail traffic, telecom operators' transmission network are provided effectively and are easily operated.
Summary of the invention
The present invention provides a kind of clockwork detection system, expensive which solve time and frequency measurement functions of the equipments are single
The problem of.
The present invention provides a kind of clockwork detection system, can test the time accuracy of a variety of time signals.
The present invention provides a kind of clockwork detection system, comprising:
Master control borad；
Frequency synthesis plate is electrically connected with the master control borad, and the frequency synthesis plate exports required according to time and frequency standards
Final time frequency signal；
Pinboard, the master control borad electrical connection, for realizing the switching of USB and network interface.
Time and frequency measurement plate is electrically connected with the master control borad, the frequency synthesis plate, and the time and frequency measurement plate is for measuring
A variety of time frequency signals；
Power module is electrically connected with the master control borad, the frequency synthesis plate.
The invention enables a variety of time frequency signals can use a device measuring, while also can produce multi-frequency signal,
User does not need more exchange device, saves the time, reduces costs.
Preferably, the frequency synthesis plate includes time and frequency standards module, output module and FPGA, the time and frequency standards mould
Block includes rubidium clock, GNSS receiver, DC B code conditioning module, 1PPS+TOD conditioning module, the time and frequency standards module according to
The time-frequency that GNSS receiver, DC B code conditioning module and the conditioning of 1PPS+TOD conditioning module recover is as time and frequency standards；It is described
The 10MHz standard frequency source that output module utilizes the rubidium clock to provide, exports four kinds of frequency signals.
It preferably, further include level translator SN74LV1T34 and 422 electrical level transferring chips, the level translator
SN74LV1T34,422 electrical level transferring chips, FPGA are integrated on the frequency synthesis plate, and the DC B code conditioning module will be straight
Flow B code by the level translator turn, after directly input FPGA and parse；The 1PPS+TOD conditioning module leads to 1PPS signal
It after crossing the level translator, inputs the FPGA and is parsed, by TOD signal by inputting after 422 level translator
The FPGA is parsed, and the time and frequency standards module is improved according to GNSS receiver, DC B code conditioning module and 1PPS+TOD
The time-frequency that module conditioning recovers is as time and frequency standards.
Preferably, the output module includes DDS, STM32F103ZE, level comparable chip LT1719 and E1 chip,
The 10MHz standard frequency source that the output module utilizes the rubidium clock to provide, compares core by STM32F103ZE, DDS, level
After piece LT1719, FPGA and E1 chip processing, four kinds of frequency signals are exported, four kinds of frequency signals are respectively synchronised clock letter
Number, internal clock signal, sinusoidal signal and E1 signal occurs, the synchronizing clock signals are the square-wave signal of 1KHz~50MHz,
The internal clock signal is the sinusoidal signal of 10MHz, and the sinusoidal signal is the sinusoidal signal of 2.048MHz, and the E1 occurs
Signal is 2.048Mbps standard block signal.
Preferably, the rubidium clock is electrically connected the first bnc interface, and the GNSS receiver connects GNSS by TNC interface
Antenna, the DC B code conditioning module are electrically connected the second bnc interface, and the 1PPS+TOD conditioning module is electrically connected DB9 interface,
The synchronizing clock signals and the internal clock signal pass through respectively third bnc interface and the 4th bnc interface output, it is described just
String signal is exported by the 5th bnc interface, and the E1 occurs signal and exported by the 6th bnc interface.
Preferably, the output module is configured the DDS output frequency to by the first SPI interface by the FPGA
The internal clock signal of 10MHz, the output module pass through the second SPI interface for the DDS by the STM32F103ZE
Output frequency is configured to 2.048MHz square-wave signal and the sinusoidal signal of 2.048MHz, and the 2.048MHz square-wave signal is logical
It crosses the FPGA to divide to obtain 2.048MHz standard block signal, 2.048MHz standard block signal described in the E1 chip processing
It generates the E1 and occurs signal, the output module is by the STM32F103ZE by the third SPI interface by the DDS
Output frequency is configured to the synchronizing clock signals.
Preferably, the time and frequency measurement plate includes ADC, DP83640 and STM32F107, described in the ADC electrical connection
FPGA, the FPGA are electrically connected by the 4th SPI serial ports with the STM32F107, the DP83640 and the STM32F107
Electrical connection, the STM32F107 are electrically connected with the master control borad；
Wherein, the time and frequency measurement plate measurement DC B code, alternating-current B code, frequency, the E1 generate signal, 1PPS+TOD letter
Number and NTP/PTP signal.
Preferably, the time and frequency measurement plate electrical connection DCLS measurement interface, alternating-current B code measurement interface, frequency measurement connect
Mouth, E1 signal measurement interface are bnc interface, and 1PPS+TOD measures interface, and NTP/PTP measures interface；
Wherein, DCLS measurement interface be the 7th bnc interface, alternating-current B code measurement interface be the 8th bnc interface,
The frequency measurement interface is the 9th bnc interface, the E1 signal measurement interface is the tenth bnc interface, and the 1PPS+TOD is surveyed
Amount interface is DB9 interface, and the NTP/PTP measurement interface is RJ45 interface.
Preferably, pinboard connection debugging port and USB interface, the debugging port are network test port.
It preferably, further include power supply adaptor and battery, the power supply adaptor is connect with the battery, the battery
It is electrically connected with the power panel, the voltage of the power supply adaptor output is 21V, and error range is ± 5%, the power adaptation
The electric current of device output is 3A.
Beneficial effect of the present invention
1, clockwork detection system provided by the invention realizes various time frequency signal measurements and multi-frequency signal
The Integrated Measurement System as one is exported, cost has been saved.
2, clockwork detection system provided by the invention makes operation become simple, save staff when
Between cost.
3, clockwork detection system provided by the invention makes operator not have to more exchange device, can detect various letters
Number, there is promotion prospect.
4, clockwork detection system provided by the invention, use GPS/ Big Dipper satellite signal, B code signal or other when
Between signal as UTC time benchmark, inside carries out timing and measurement using high-performance clock source, improves the accuracy of measurement.
5, clockwork detection system provided by the invention can be used a variety of Timing Signals as time base source, lead to
It crosses changing interface and measures same signal, obtain the time difference between different Timing Signals.Due to using same equipment, measure same
Signal eliminates the constant error introduced in measurement process, as a result more acurrate.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the structural schematic diagram of clockwork detection system provided by the invention；
Fig. 2 is the structural schematic diagram of first panel provided by the invention；
Fig. 3 is the structural schematic diagram of second panel provided by the invention；
Fig. 4 is the schematic diagram of internal structure of clockwork detection system provided by the invention；
Fig. 5 is time reference module by signal handling principle figure；
The principles of signal processing schematic diagram of Fig. 6 DC B code conditioning module provided by the invention and alternating-current B code conditioning module；
Fig. 7 is the circuit diagram of the signal processing of DC B code conditioning module；
Fig. 8 is the circuit diagram of the signal processing of alternating-current B code；
Fig. 9 is the signal processing schematic diagram of the 1PPS+TOD conditioning module；
Figure 10 is that B code frame head extracts schematic diagram；
Figure 11 is that B code data parse schematic diagram；
Figure 12 is design flow diagram of the B code on FPGA；
Figure 13 is the schematic diagram of sinusoidal signal configuration；
Figure 14 is the 2.048MHz square-wave signal and the schematic diagram that sinusoidal signal configures；
Figure 15 is the schematic diagram of 1KHz-50MHz square-wave signal configuration；
Figure 16 is the circuit diagram of 1KHz-50MHz square-wave signal configuration；
Figure 17 is that E1 signal generates and record principle figure；
Figure 18 is that E1 signal generates and received software design flow chart；
Figure 19 is PTP/NTP principles of signal processing figure；
Figure 20 is the schematic diagram that time and frequency measurement plate measures various waveform signals；
Figure 21 is the circuit diagram that time and frequency measurement plate measures various waveform signals；
Figure 22 is the schematic diagram of the phaselocked loop mensuration；
Figure 23 is time accuracy measuring principle figure；
The process of the measurement of Figure 24 frequency accuracy and the FPGA to time accuracy measurement；
Wherein, 1- master control borad, 2- frequency synthesis plate, 3- pinboard, 4- time and frequency measurement plate, 5- power module, 6- liquid crystal board,
7- power panel, 8- battery, 9- first panel, 10- second panel, the first bnc interface of 11-, 12-TNC interface, the 2nd BNC of 13- connect
Mouthful, 14-DB9 interface, 15- third bnc interface, the 4th bnc interface of 16-, the 5th bnc interface of 17-, the 6th bnc interface of 18-, 19-
DCLS measures interface, and 20- alternating-current B code measures interface, 21- frequency measurement interface, 22-E1 signal measurement interface, 23-1PPS+TOD
Interface is measured, 24-NTP/PTP measures interface, and 25- debugs port, 26-USB interface.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The present invention provides a kind of clockwork detection system, comprising:
Master control borad 1 is arm processor；Frequency synthesis plate 2 is electrically connected, the frequency synthesis with the master control borad 1
Plate includes time and frequency standards module, output module and FPGA, and the time and frequency standards module includes rubidium clock, GNSS receiver, DC B code
Conditioning module, 1PPS+TOD conditioning module, the time and frequency standards module according to GNSS receiver, DC B code conditioning module and
The time-frequency that the conditioning of 1PPS+TOD conditioning module recovers is as time and frequency standards, wherein the rubidium clock is electrically connected the first bnc interface
11, the GNSS receiver connects GNSS antenna by TNC interface 12, and the DC B code conditioning module is electrically connected the 2nd BNC and connects
Mouth 13, the 1PPS+TOD conditioning module are electrically connected DB9 interface 14；The output module includes DDS, STM32F103ZE, level
Comparable chip LT1719 and E1 chip, the 10MHz standard frequency source that the output module utilizes the rubidium clock to provide, passes through
After STM32F103ZE, DDS, level comparable chip LT1719, FPGA and E1 chip processing, four kinds of frequency signals are exported, described four
Kind frequency signal is respectively that signal, the synchronised clock letter occur for synchronizing clock signals, internal clock signal, sinusoidal signal and E1
Number square-wave signal for being 1KHz~50MHz, the internal clock signal is the sinusoidal signal of 10MHz, and the sinusoidal signal is
The sinusoidal signal of 2.048MHz, it is 2.048Mbps standard block signal that signal, which occurs, for the E1, wherein the synchronised clock letter
Number and the internal clock signal pass through third bnc interface 15 and the output of the 4th bnc interface 16 respectively, the sinusoidal signal passes through
The output of 5th bnc interface 17, the E1 occur signal and are exported by the 6th bnc interface 18.
Pinboard 3, the master control borad 1 is electrically connected, for realizing the switching of USB and network interface., wherein the pinboard
Connection debugging port 25 and USB interface 26；
Time and frequency measurement plate 4 is electrically connected with the master control borad 1, the frequency synthesis plate 2, and the time and frequency measurement plate 4 is used for
Measure a variety of time frequency signals；The time and frequency measurement plate includes ADC, DP83640 and STM32F107, described in the ADC electrical connection
FPGA, the FPGA are electrically connected by the 4th SPI serial ports with the STM32F107, the DP83640 and the STM32F107
Electrical connection, the STM32F107 are electrically connected with the master control borad；The time and frequency measurement plate electrical connection DCLS measurement interface 19 is handed over
It flows B code and measures interface 20, frequency measurement interface 21, E1 signal measurement interface 22,1PPS+TOD measures interface 23, and NTP/PTP is surveyed
Interface 24 is measured, i.e., the described time and frequency measurement plate measurement DC B code, alternating-current B code, frequency, the E1 generate signal, 1PPS+TOD signal
And NTP/PTP signal, more particularly, the DCLS measurement interface is the 7th bnc interface, alternating-current B code measurement interface is
8th bnc interface, the frequency measurement interface are the 9th bnc interface, the E1 signal measurement interface is the tenth bnc interface, institute
Stating 1PPS+TOD measurement interface is DB9 interface, and the NTP/PTP measurement interface is RJ45 interface.
Power module 5 is electrically connected with the master control borad 1, the frequency synthesis plate 2；The power module includes power supply
Adapter, power panel 7 and battery 8, the power supply adaptor are connect with the battery 8, the battery 8 and 7 electricity of power panel
Connection, the voltage of the power supply adaptor output are 21V, and error range is ± 5%, and the electric current of the power supply adaptor output is
3A.It is powered using special power source adapter, built-in high capacity cell, the power blackout situation lower retention time is greater than 2 hours, facilitates strange land
Line.
Liquid Crystal Module, is liquid crystal board 6, and the liquid crystal board 6 is electrically connected with the master control borad 1；
Wherein, the EP4CE115F23I7 in hardware FPGA selection CycloneIVE series that the present invention uses.It is a total of
110000 logic units, and built-in phase-locked loop pll, facilitate software to be encoded.And encapsulation is smaller, facilitates cloth version.Supply voltage
3.3V and 1.2V；Level translator SN74LV1T34 be it is a have compared with wide-voltage range gate logic, output level with
It, being capable of branch 3.3V/1.8V/2.5V/5V level on the basis of supply voltage；That DDS chip is selected is the AD9912 of ADI company, interior
Portion's clock speed may be up to 1GSPS, and be integrated with 14 digit mode converters.AD9912 uses 48 bit frequency control words, output frequency
Rate resolution ratio is less than 4uHz.There are two prominent features for AD9912 tool, on the one hand, and AD9912 work is in numeric field, once it updates
Frequency control word, the frequency of output is just corresponding to be changed, and chirp rate is high；On the other hand, since the range of frequency control word is wide,
Frequency resolution is relatively high；Level comparable chip LT1719 selects the high speed voltage comparator LT1719 of Ling Lite company, transmission
Time delay 4.5ns, the chip are used to convert sine, triangular wave, square wave and pulse signal to the square-wave signal of LVTTL level, use
LT1719 makees zero passage detection (Zero crossing level is adjustable): VCCMeet 5V, VEE- 5V is met, the amplitude peak that can input original signal is
10Vpp；- IN connects comparative level (adjustable, initial 0V), and+IN inputs original signal, and OUT exports square-wave signal.If original signal is electric
It is flat to be greater than comparative level, it exports high level 1 (+VS-0.4), if original signal level is less than comparative level, exports low level 0
(0.4V)；E1 chip selects DS26502, and special clock restores device.It its receiving end can be from T1, E1,64kHz composite clock
Clock is recovered with 6312kHz synchronization timing interface, under T1 and E1 mode, moreover it is possible to restore Synchronication status message (SSM).It sends
Part can be directly connected to T1, E1 or 64kHz composite clock sync cap.SSM is also capable of providing under T1 and E1 mode.?
In terms of physical characteristic, DS26502 can be arranged by software, at the same support it is long away from and short distance, without change hardware can
With the different line interfaces such as 75/100/110/120；The Jitter Attenuation device of chip interior can both be placed on sending side or be placed on
Receiving side, and there is bypass mode；When the states such as LOS, AIS and LOF occurs in route, there is hardware pins output instruction；Control
Mode multiplicity processed can be written and read, when using 8 parallel-by-bit control port by parallel, serial or hardware control port
It can choose two kinds of mode bus of Intel or Motorola, using general SPI interface when serial mode, DS26502 chip is total
There are 100 pins, wherein the common network interface pin for line interface unit, clock pins, receiving end and transmitting terminal
The control pin of synchronization signal pin and serial data pin and some other configuration pins and parallel control mouth；Alternating-current B
The ADC chip of code uses the LTC1412 of Ling Lite company.It is higher with sampling rate fast (3M), parallel data output, digit
The advantages that (12), encapsulation is smaller, and peripheral circuit configuration is simple；DC B code level conversion uses the logic of Texas Instruments
Level translator SN74LV1T34.SN74LV1T34 be it is a have compared with wide-voltage range gate logic, output level with
It, being capable of branch 3.3V/1.8V/2.5V/5V level on the basis of supply voltage；422 electrical level transferring chips (MAX3077E) be 3.3V, ±
The RS-485/RS-422 transceiver of 1.5KVESD protection, has a driver and a receiver, these devices include failure
Protect circuit.Suitable for full duplex communication, SOIC-8pin encapsulation；PTP/NTP signal processing module is mainly that utilization can be supported
The special chip of IEEE1588 standard realizes clock synchronizing function.Special chip (DP83640) register is configured by single-chip microcontroller, it is right
1PPS is unpacked and exported by the standard PTP/NTP signal that network interface obtains, DP83640 is that a have the function of 1588
EthernetPHY chip, DP83640 may be implemented 1588 precision time protocols (PTP) and the clock key component of NTP, have
Following functions: two versions of IEEE1588V1 and V2 are supported；UDP/IPv4, the Ethernet packet function of UDP/IPv6 are provided；It can be with
Setting output PTP or NTP timestamp, the resolution ratio of timestamp can achieve 8ns；It provides 12 and meets IEEE1588 agreement
GPIO can use the output that trigger signal realizes 1PPS；Support adaptive 10/100M Ethernet；GNSS antenna is mainly completed
The acquisition of GPS and BDS satellite-signal and low noise amplification function, in order to improve time service precision, it is desirable that GNSS antenna phase center misses
Difference is the smaller the better, while must have enough sensitivity and gain, by comparing and set GNSSOEM plate actual test pair
Than we select high-precision GGB017IA measurement type antenna, and the GNSS receiver mainly completes connecing for GNSS satellite signal
It receives and processing, performance indicator directly determines the positioning that is capable of providing of positioning feed system of the synthesis time service based on Beidou and award
Shi Jingdu, while to be also supplied to calibrating frequency foundation of the rubidium clock as rubidium clock module.This system has selected LEA-M8T conduct
The nucleus module of GNSSOEM plate, for the dedicated GNSS time service module of a new generation of UBLOX company exploitation, can for need compared with
The application of high location requirement provides accurate GNSS time service service, has the function of time mode, can by being manually entered or just
Automatic measurement is that the static state position 3D is arranged in GNSS receiver when beginningization.It, can be visible in an only satellite during static state operation
In the case where carry out GNSS time service；And time service error is eliminated, to avoid causing to position mistake.By using quantization error compensation
The granularity error of time pulse, precision may be up to 15ns.This means that even if signal conditioning is unfavorable or sky visibility not
Also time output can be obtained under good environment.The module enables user be able to use configuration rate-adaptive pacemaker and time pulse.Built-in
Markers and counter device, which can input external event, carries out accurate time measurement；Clock base of the rubidium clock as whole equipment
Standard, phase noise and frequency stabilization seem most important to equipment performance, select by comparing and testing this programme
The QuantunTMSA.45sCSAC chip-scale atomic clock of Microsemi company, the rubidium clock have Low phase noise, low drifting, stability
The features such as high.
Working principle about the time and frequency standards module in frequency synthesis plate is as follows:
Time reference selecting module is mainly to be recovered using GNSS receiver, DC B code signal or 1PPS+TOD
Time and frequency standards of the high-precision Time-Frequency Information as all signal sources of this equipment are realized as shown in Figure 5, wherein as shown in fig. 6, straight
B code is flowed mainly by comparator, level conversion is directly carried out to DC B code signal, i.e., converts LVTTL electricity for Transistor-Transistor Logic level
FPGA is given after flat to be decoded, and is entered back into time and frequency measurement plate and is measured；Alternating-current B code is sampled using ADC, after sampling
Data be sent into FPGA carry out text parsing and 1PPS signal generate, be re-fed into time and frequency measurement plate carry out time measurement；
As shown in figure 9, respectively enteing FPGA and STM32F107 solution after 1PPS+TOD passes through level conversion into LVTTL level
Code and measurement；Fig. 7 is the circuit diagram of the signal processing of DC B code conditioning module；Fig. 8 is the signal processing of alternating-current B code
Circuit diagram.
The specific software design process of B code conditioning are as follows:
1) B code frame head extracts, and B code frame head is made of the pulse of continuous 2 8ms wide, as shown in Figure 10, using every in FPGA
A B code rising edge is zeroed out a counter when arriving, and the mode that other moment are counted counts each code first
The width of member.Since each code element width is 10ms, then 10 1ms are divided into according to counter, but due to code in practice
First pulsewidth has swing, so each more original pulsewidth of 1ms pulsewidth shifts to an earlier date 10us, generates 1ms and interrupts, arrives further according to 1ms interruption
Whether B code is 1 to be sampled when coming.Data head is finally found using sliding relevant way in all sampled points
111111110011111111。
2) B code data parse, and after finding frame head, the position of all symbols can be found according to the frame structure of B code.Due to
The particularity of B code, i.e., 1 is 5ms pulsewidth, and 0 is 2ms pulsewidth, then carries out judging whether it is 1 at 4ms.Following Figure 11 institute
Show: finally according to the data after demodulation, being spliced into temporal information and externally send.
It for alternating-current B code, is sampled first with A/D, sample rate 3MHz.FPGA is entered data into after sampling,
FPGA used 0 detection, after finding 0 point of all mistakes, maximizing and minimum point after the 1ms period for postponing 1/4.To extensive
Again it is DC B code waveform, only postpones the period of original waveform about 1/4.It is parsed according to DC B code again.
Actually the time 250us will be postponed due to using the method to be parsed, so in the pulse per second (PPS) of final output
The upper time for needing the 1PPS restored to postpone 250us, such as the flow chart that Figure 12 is FPGA design.
Course of work principle about the output module in frequency synthesis plate is as follows:
(present invention is defeated as the standard frequency source (10MHz) of equipment using rubidium clock for the clock source of the 10MHz provided by rubidium clock
Out, have the features such as phase noise is small, stability is high, while rubidium clock module work state information can be exported in real time) generate 1 tunnel
The sinusoidal signal of 10MHz, 7dBm ± 1dBm；The principle that 10MHz sinusoidal signal generates is as shown in figure 13, passes through SPI mouthfuls by FPGA
10MHz sinusoidal signal is configured by AD9912 output frequency.
The clock source of the 10MHz provided by rubidium clock generates 1 road 2.048MHz square-wave signal and the sinusoidal letter of 1 road 2.048MHz
Number；The principle of 2.048MHz square-wave signal configuration is as shown in figure 14, and AD9912 is exported frequency by SPI mouthfuls by STM32F103ZE
Rate is configured to 2.048MHz square-wave signal (CMOS output and DAC output respectively), divides to obtain 2.048MHz square wave by FPGA.
The clock source of the 10MHz provided by rubidium clock generates 1KHz-50MHz, the square-wave signal of stepping 1KHz；1KHz-50MHz
The principle of square-wave signal is as shown in Figure 15 and Figure 16；
1KHz-50MHz square-wave signal is divided into three frequency ranges and individually generates, three frequency ranges be respectively 1KHz-45KHz,
45KHz-400KHz,400KHz-50MHz.The signal of three frequency ranges is gated by FPGA and is exported, and the signal message of three frequency ranges is shown in
Table 1:
| fset | fDDSFrequency | FPGA divider ratio | F range after frequency multiplication |
| 1K-45K | *1000 | 1000 | 1M-45M |
| 45K-400K | *100 | 100 | 4.5M-40M |
| 400K-50M | *1 | 1 | 400K-50M |
STM32F103ZE completes the configuration of DDS1 (AD9912) chip according to required output frequency, exports 1KHz-50MHz
Sinusoidal signal (part is D/A difference output).Difference sinusoidal signal synthesizes sinusoidal signal all the way after combiner, by logical
Band is to enter high-speed level comparable chip LT1719 after 50MHz low-pass filter filters, and is produced by the way that suitable comparative level is arranged
The square-wave signal of raw 1KHz-50MHz, is gated by FPGA and is exported.
E1 signal is the E1 signal that the 2.048MHz standard block generated according to frequency synthesizer generates standard, is protected through oversampling circuit
After shield, isolation, impedance matching, exported by 75 ohm of BNC sockets；The reception of E1 signal is the BNC by 75 ohms impedance match
Socket inputs the E1 signal of standard, the clock signal of 2.048MHz is decoded and recovered to the signal, and give time and frequency measurement plate
Carry out frequency measurement.
Wherein EP4CE115F23I7 mainly completes the conversion of APB bus Yu x86 bus protocol.Its principle is as shown in figure 17,
Software design process such as Figure 18.
Wherein, the hardware FPGA in the time and frequency measurement plate also selects the EP4CE115F23I7 in CycloneIVE series.
Wherein, the working principle description below of the time and frequency measurement plate:
Alternating-current B code is sampled using ADC, and the data after sampling are sent into FPGA and carry out text parsing and the life of 1PPS signal
At, be re-fed into time and frequency measurement plate carry out time measurement.
PTP/NTP module mainly utilizes control of the single-chip microcontroller to PTP special chip, realizes the reception of PTP signal and solution
Code configures special chip (DP83640) register by single-chip microcontroller, unpacks simultaneously to the standard PTP/NTP signal obtained by network interface
1PPS is exported, while exporting 1PPS and being sent into time and frequency measurement plate realization PTP accuracy measurement, as shown in figure 19.
The time and frequency measurement plate measures lower column signal:
Various waveform signal frequencies are measured, measured signal is converted to by square wave by comparator, it is real to be sent into FPGA
Existing frequency and precision measure.FPGA gives the frequency of calculating to STM32107, STM32107 according to respective formula calculate TIE,
MTIE and TDEV information, as shown in figure 20, circuit design principle is as shown in figure 21；
E1 signal is measured, gives the 2.048MHz clock signal that E1 receiving module recovers to FPGA, by (1) side
Formula realizes signal measurement, and calculates TIE, MTIE and TDEV information；
Time accuracy measurement to various timing signals (1PPS+TOD, DCLS, IRIG-B, NTP, PTP).Wherein,
1PPS+TOD Measurement Resolution 10ns；DCLS Measurement Resolution 10ns；IRIG-B resolution ratio 1us；NTP resolution ratio 1us；PTP points
Resolution 10ns；
Various time signal processing circuits have been discussed in detail in other modules.It is right using the 1pps of reference source as standard
The 1pps interruption of measured signal time system measures, and measures the spacing between the two rising edge, is then the accuracy of time.
Wherein, for the measurement of frequency accuracy, using phaselocked loop mensuration, basic principle is as shown in figure 22, uses
Phaselocked loop inside FPGA respectively on the basis of benchmark frequency-doubled signal respectively to phase delay 1.04ns, 2.08ns, 2.91ns,
3.95ns generates 4 groups of new 200M signals.Then 5 groups of 200M including benchmark frequency-doubled signal are latched simultaneously at the T10 moment
Signal.If certain road signal is latched first, the retardation on the road Ze Qugai carries out error correction.T01-T11 sections of mistakes can similarly be obtained
Difference amendment.Then period (ns) of measured signal=(counter 5ns+T00-T10 sections of 3 value *+T01-T11 sections of error correction error is repaired
Just)/2 value of counter.It is again frequency by periodic conversion.Measurement process is completed by FPGA, and measurement data is supplied to by FPGA
MCU, master control borad calculate frequency measurement by MCU and show as a result, being sent to master control borad.After having extracted data every time, MCU carries out FPGA
It resets, starting measures next time.
Wherein, time accuracy is measured, it is as shown in figure 23, upper as 1PPS using the 1PPS of reference signal as standard
It rises along when arriving, the counter inside FPGA is zeroed out, other moment add up.Then by the 1PPS period of reference source with
FPGA internal clocking is split for unit.When measured signal rising edge arrive when latch the Counter Value, then the value multiplied by
FPGA internal clock cycles are the time accuracy deviation of the two.Measurement to frequency accuracy and to time accuracy measurement
FPGA process it is as shown in figure 24.
Since the atomic clock of satellite navigation system carries out real-time monitoring and amendment by ground clock, have good long-term steady
Therefore qualitative energy makes it possible that satellite navigation system is utilized to design high-precision time-frequency equipment.
This project tame and correct in real time to rubidium clock built in equipment using GNSS receiver, using receiver, DC B
The high-precision Time-Frequency Information that code signal or 1PPS+TOD are recovered, as the time and frequency standards of all signal sources of this equipment, then
Frequency source when being generated needed for each module by DDS technology, then respectively by final signal needed for signal modulation and conditioning output
(synchronizing clock signals and E1 signal), and this system by sine wave, square wave and triangular wave waveform improve after, how all use is
Phase leggy Synchronos method realizes the measurement of various frequency signals；The time accuracy test of a variety of time frequency signals is realized by FPGA
(including: AC/DC B code signal, PTP signal, NTP signal and 1PPS+TOD signal).
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of clockwork detection system characterized by comprising
Master control borad；
Frequency synthesis plate is electrically connected with the master control borad, and the frequency synthesis plate exports required final according to time and frequency standards
Time frequency signal；
Pinboard, the master control borad electrical connection.
Time and frequency measurement plate is electrically connected with the master control borad, the frequency synthesis plate, and the time and frequency measurement plate is a variety of for measuring
Time frequency signal；
Power panel is electrically connected with the master control borad, the frequency synthesis plate.
2. clockwork detection system as described in claim 1, which is characterized in that the frequency synthesis plate includes time and frequency standards
Module, output module and FPGA, the time and frequency standards module include rubidium clock, GNSS receiver, DC B code conditioning module, 1PPS+
TOD conditioning module, the time and frequency standards module is according to GNSS receiver, DC B code conditioning module and 1PPS+TOD conditioning module
The time-frequency recovered is improved as time and frequency standards；The 10MHz standard frequency source that the output module utilizes the rubidium clock to provide, it is defeated
Four kinds of frequency signals out.
3. clockwork detection system as claimed in claim 2, which is characterized in that further include level translator SN74LV1T34
With 422 electrical level transferring chips, the level translator SN74LV1T34,422 electrical level transferring chips, FPGA are integrated in the frequency
On comprehensive plate, the DC B code conditioning module turns DC B code by the level translator, after directly input FPGA and parse；
The 1PPS+TOD conditioning module is by 1PPS signal by inputting the FPGA and being parsed, by TOD after the level translator
After signal passes through 422 level translator, inputs the FPGA and parsed, the time and frequency standards module is received according to GNSS
The time-frequency that machine, DC B code conditioning module and the conditioning of 1PPS+TOD conditioning module recover is as time and frequency standards.
4. clockwork detection system as claimed in claim 2, which is characterized in that the output module include DDS,
STM32F103ZE, level comparable chip LT1719 and E1 chip, the output module are marked using the 10MHz that the rubidium clock provides
Quasi- frequency source exports four kinds of frequencies after STM32F103ZE, DDS, level comparable chip LT1719, FPGA and E1 chip processing
Rate signal, four kinds of frequency signals are respectively that signal occurs for synchronizing clock signals, internal clock signal, sinusoidal signal and E1,
The synchronizing clock signals are the square-wave signal of 1KHz~50MHz, and the internal clock signal is the sinusoidal signal of 10MHz, institute
The sinusoidal signal that sinusoidal signal is 2.048MHz is stated, it is 2.048Mbps standard block signal that signal, which occurs, for the E1.
5. clockwork detection system as claimed in claim 4, which is characterized in that the rubidium clock is electrically connected the first bnc interface,
The GNSS receiver connects GNSS antenna by TNC interface, and the DC B code conditioning module is electrically connected the second bnc interface, institute
State 1PPS+TOD conditioning module electrical connection DB9 interface, the synchronizing clock signals and the internal clock signal pass through the respectively
Three bnc interfaces and the output of the 4th bnc interface, the sinusoidal signal are exported by the 5th bnc interface, and the E1 occurs signal and passes through
The output of 6th bnc interface.
6. clockwork detection system as claimed in claim 4, which is characterized in that the output module is passed through by the FPGA
First SPI interface configures the DDS output frequency to the internal clock signal of 10MHz, and the output module is by described
STM32F103ZE configures 2.048MHz square-wave signal and 2.048MHz for the DDS output frequency by the second SPI interface
The sinusoidal signal, the 2.048MHz square-wave signal divide to obtain 2.048MHz standard block signal, institute by the FPGA
It states 2.048MHz standard block signal described in E1 chip processing and generates the E1 generation signal, the output module is by described
STM32F103ZE configures the synchronizing clock signals for the DDS output frequency by the third SPI interface.
7. clockwork detection system as claimed in claim 4, which is characterized in that the time and frequency measurement plate include ADC,
DP83640 and STM32F107, the ADC are electrically connected the FPGA, the FPGA by the 4th SPI serial ports with it is described
STM32F107 electrical connection, the DP83640 are electrically connected with the STM32F107, the STM32F107 and master control borad electricity
Connection；
Wherein, time and frequency measurement plate measurement DC B code, alternating-current B code, frequency, the E1 generate signal, 1PPS+TOD signal and
NTP/PTP signal.
8. clockwork detection system as claimed in claim 7, which is characterized in that the time and frequency measurement plate electrical connection DCLS is surveyed
Measuring interface, alternating-current B code measurement interface, frequency measurement interface, E1 signal measurement interface is bnc interface, and 1PPS+TOD measurement connects
Mouthful, NTP/PTP measures interface；
Wherein, the DCLS measurement interface is the 7th bnc interface, alternating-current B code measurement interface is the 8th bnc interface, described
Frequency measurement interface is the 9th bnc interface, the E1 signal measurement interface is the tenth bnc interface, and the 1PPS+TOD measurement connects
Mouth is DB9 interface, and the NTP/PTP measurement interface is RJ45 interface.
9. clockwork detection system as claimed in claim 8, which is characterized in that pinboard connection debugging port and
USB interface.
10. clockwork detection system as claimed in claim 2, which is characterized in that further include power supply adaptor and battery, institute
It states power supply adaptor to connect with the battery, the battery is electrically connected with the power panel, the electricity of the power supply adaptor output
Pressure is 21V, and error range is ± 5%, and the electric current of the power supply adaptor output is 3A.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113240062A (en) * | 2021-06-11 | 2021-08-10 | 江苏帝一集团有限公司 | Optical cable accurate positioning and searching system based on radio frequency identification label |
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