CN112882971A

CN112882971A - Serial port communication system and method, storage medium and processor

Info

Publication number: CN112882971A
Application number: CN201911204617.4A
Authority: CN
Inventors: 方斌
Original assignee: Zhejiang Shaoxing Supor Domestic Electrical Appliance Co Ltd
Current assignee: Zhejiang Shaoxing Supor Domestic Electrical Appliance Co Ltd
Priority date: 2019-11-29
Filing date: 2019-11-29
Publication date: 2021-06-01

Abstract

The invention discloses a serial port communication system and method, a storage medium and a processor. Wherein, this system includes: the first chip comprises at least one first port, and the at least one first port is connected with a communication line; the second chip comprises at least one second port, and the at least one second port is connected with the communication line; the states of the first chip and the second chip are switched circularly between a sending state and a receiving state, and the states of the first chip and the second chip are different. The invention solves the technical problem of higher serial port communication cost in the related technology.

Description

Serial port communication system and method, storage medium and processor

Technical Field

The invention relates to the field of cooking appliances, in particular to a serial port communication system and method, a storage medium and a processor.

Background

At present, multi-core development is a common development scheme of household electrical appliances, particularly IH (induction Heating) products are basically dual-core development, a display panel and a power panel communicate through four wires, and the four wires are two power wires and two communication wires respectively. However, in the home appliance, the length of the wire from the display panel to the power panel is relatively long, and the four-wire communication cost is relatively high.

Aiming at the problem of high serial port communication cost in the related technology, an effective solution is not provided at present.

Disclosure of Invention

The embodiment of the invention provides a serial communication system and method, a storage medium and a processor, which at least solve the technical problem of high cost of serial communication in the related technology.

According to an aspect of an embodiment of the present invention, there is provided a serial communication system including: the first chip comprises at least one first port, and the at least one first port is connected with a communication line; the second chip comprises at least one second port, and the at least one second port is connected with the communication line; the states of the first chip and the second chip are switched circularly between a sending state and a receiving state, and the states of the first chip and the second chip are different.

In the embodiment of the invention, all the first ports of the first chip and all the second ports of the second chip are connected through one communication wire, and the serial communication is completed by switching the states of the first chip and the second chip.

Further, the first chip includes two first ports, or the second chip includes two second ports, where the two first ports are a transmitting port and a receiving port of the first chip, respectively, and the two second ports are a transmitting port and a receiving port of the second chip, respectively. Aiming at a chip comprising a sending port and a receiving port, the two ports are connected in parallel, so that the effect of saving the serial port communication cost is achieved.

Furthermore, each first port is connected with the communication line through a first resistor, and each second port is connected with the communication line through a second resistor. The effects of avoiding burning out of the chip port and avoiding impact of factors such as static electricity on the port are achieved by arranging the current-limiting resistor.

Further, the above system further comprises: a first terminal comprising: the first power line interface, the first communication line interface and the first ground wire interface, wherein at least one first port is connected to the first communication line interface through a corresponding first resistor; a second terminal comprising: the second power line interface, the second communication line interface and the second ground interface, wherein at least one second port is connected to the second communication line interface through a corresponding second resistor; the first power line interface is connected with the second power line interface through a power line, the first communication line interface is connected with the second communication line interface through a communication line, and the first ground line interface is connected with the second ground line interface through a ground line. The first chip and the second chip are connected through the terminals, and the effect of facilitating maintenance and replacement of the chips and the communication lines is achieved.

Furthermore, the first chip is in a sending state after being powered on, and the second chip is in a receiving state after being powered on. By presetting the states of the first chip and the second chip, the first chip and the second chip can be ensured to be communicated in time after being electrified.

According to another aspect of the embodiments of the present invention, there is also provided a serial communication method, which is applied to the serial communication system, wherein the serial communication method includes: when the first chip is in a sending state, the first chip sends data to the second chip through the communication line, wherein the second chip is in a receiving state; after the data transmission is finished, the state of the first chip is switched to a receiving state; the first chip receives a response signal corresponding to data returned by the second chip through a communication line, wherein the second chip is in a sending state; after the reception of the response signal is completed, the state of the first chip is switched to the transmission state.

In the embodiment of the invention, all the first ports of the first chip and all the second ports of the second chip are connected through one communication wire, and the state of the first chip is switched based on the data sending and receiving conditions, so that the serial port communication is completed.

Further, after the state of the first chip is switched to the receiving state, the method further includes: acquiring the waiting time of the first chip, wherein the waiting time is the time from the state of the first chip being switched to the receiving state to the response signal being received; judging whether the waiting time reaches a preset time or not; and under the condition that the waiting time reaches the preset time, the state of the first chip is switched to a sending state. By setting the preset time and automatically switching the state after the waiting time exceeds the preset time, the situation that the first chip cannot receive the response signal and is always in the receiving state, and the whole household appliance cannot normally work is avoided.

Further, when the state of the first chip is switched to the receiving state, the timer is controlled to start timing, and when the first chip receives the response signal, the timer is controlled to stop timing, wherein the obtaining of the waiting time of the first chip includes: and acquiring the timing time of the timer. The aim of determining the waiting time of the first chip is achieved by controlling the timer to time.

Further, after the data reception is completed, the state of the second chip is switched to a transmission state; after the transmission of the response signal is completed, the state of the second chip is switched to the receiving state. And switching the state of the second chip based on the data sending and receiving conditions, thereby completing serial port communication.

Further, after the first chip and the second chip are powered on, the first chip is controlled to enter a sending state, and the second chip is controlled to enter a receiving state. By presetting the states of the first chip and the second chip, the first chip and the second chip can be ensured to be communicated in time after being electrified.

Further, under the condition that the first chip comprises a first port, the state of the first chip is switched by configuring the mapping function of the first chip; under the condition that the first chip comprises two first ports, the states of the first chip are switched by respectively configuring modes of the two first ports, wherein the modes of the two first ports are different, and the modes comprise one of the following modes: an operating mode and a high impedance state mode. For the first chips of different types, the modes of the ports are set in different modes, and the purpose of switching the states is achieved.

Further, under the condition that the second chip comprises a second port, the state of the second chip is switched by configuring a port mapping function of the second chip; under the condition that the second chip comprises two second ports, the states of the second chip are switched by respectively configuring the modes of the two second ports, and the modes of the two second ports are different, wherein the modes comprise one of the following modes: an operating mode and a high impedance state mode. And aiming at the second chips of different types, the modes of the ports are set in different modes, so that the purpose of switching the states is achieved.

According to another aspect of the embodiments of the present invention, there is also provided a storage medium including a stored program, wherein the program executes the above-mentioned serial port communication method.

According to another aspect of the embodiments of the present invention, there is also provided a processor, where the processor is configured to execute a program, where the program executes the serial communication method described above.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:

FIG. 1 is a schematic diagram of a serial communication system according to an embodiment of the present invention;

FIG. 2a is a schematic diagram of an alternative communication between two B-type singlechips according to an embodiment of the present invention;

FIG. 2B is a schematic diagram of an alternative type A and type B single-chip microcomputer communication according to an embodiment of the present invention;

FIG. 2c is a schematic diagram of an alternative communication between two single-chip computers of type A according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an alternative serial communication system according to an embodiment of the present invention;

FIG. 4 is a flow chart of a serial communication method according to an embodiment of the present invention;

FIG. 5 is a flow diagram of an alternative host workflow according to an embodiment of the present invention; and

fig. 6 is a flow chart of an alternative slave workflow according to an embodiment of the present invention.

Wherein the figures include the following reference numerals:

10. a first chip; 11. a first port; 12. a first resistor; 20. a communication line; 30. a second chip; 31. a second port; 32. a second resistor; 40. a first terminal; 41. a first power line interface; 42. a first communication line interface; 43. a first ground wire interface; 50. a second terminal; 51. a second power line interface; 52. a second communication line interface; 53. a second ground interface.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

According to an embodiment of the invention, a serial communication system is provided.

Optionally, the serial port communication system may be applied to household appliances, and in the embodiment of the present application, the electric pressure cooker is taken as an example for description.

Fig. 1 is a schematic diagram of a serial communication system according to an embodiment of the present invention, and as shown in fig. 1, the system includes: a first chip 10, a second chip 30 and a communication line 20, wherein the first chip 10 includes at least one first port 11, and the second chip 30 includes at least one second port 31. Only the case where the first chip 10 includes two first ports 11 and the second chip 30 includes two second ports 31 is shown in fig. 1.

The at least one first port 11 is connected with the at least one second port 31 through the communication line 20, the states of the first chip 10 and the second chip 30 are switched cyclically between a transmitting state and a receiving state, and the states of the first chip 10 and the second chip 30 are different.

Specifically, the first chip 10 and the second chip 30 may be single-chip microcomputers in the electric pressure cooker, and respectively serve as a display panel and a power panel. In the embodiment of the present invention, the first chip 10 is taken as a display panel, and the second chip 30 is taken as a power panel.

At present, the chip has two types, and the A type singlechip only comprises an IO (Input/Output) port, which can be used as a transmitting port (TXD) and a receiving port (RXD); the type B singlechip comprises two IO ports, namely a TXD port and an RXD port. In the electric pressure cooker, the display panel and the power panel can adopt various combination modes, for example, two B-type single-chip microcomputers are communicated; the type A singlechip is communicated with the type B singlechip; and the two A-type singlechips are communicated.

Aiming at the different combination modes, a half-duplex serial port communication mode can be adopted, and the purpose of reducing the communication quantity is achieved on the basis of ensuring normal communication by connecting all IO ports of the chip with one communication line 20. That is, the scheme that this embodiment provided can be applicable to various types of chips, and application scope is wider, and the limitation is less. For example, for the communication form of two B-type singlechips, as shown in fig. 2a, the first chip 10 and the second chip 30 both adopt B-type singlechips, and the TXD port and the RXD port of each chip are connected in parallel and then connected to the communication line 20; as shown in fig. 2B, the first chip 10 is a B-type single chip, the second chip 30 is an a-type single chip, the TXD port and the RXD port of the first chip 10 are connected in parallel and then connected to the communication line 20, and the IO port of the second chip 30 is directly connected to the communication line 20; as shown in fig. 2c, the first chip 10 and the second chip 30 both adopt a type a single chip, and the IO ports of both the two chips are directly connected to the communication line 20.

In the embodiment of the present invention, two types B of singlechips are used for communication, and a type a of singlechips and a type B of singlechips are used for communication. In an alternative, the first chip 10 includes two first ports 11, which are a transmitting port and a receiving port of the first chip 10, in this case, the second chip 30 may include one second port 31, and may further include two second ports 31, which are a transmitting port and a receiving port of the second chip 30. In another alternative, the second chip 30 includes two second ports 31, which are a transmitting port and a receiving port of the second chip 30, in this case, the first chip 10 may include one first port 11, and may further include two first ports 11, which are a transmitting port and a receiving port of the first chip 10.

Since the first chip 10 and the second chip 30 are connected by one communication line 20, that is, the same communication line 20 is occupied by sending and receiving data, in order to ensure normal data transmission, the states of the two chips can be switched cyclically, and the states of the two chips at the same time are different. That is, the first chip 10 is in a transmitting state, and the second chip 30 is in a receiving state, so that the first chip 10 can transmit data to the second chip 30; the first chip 10 is in a receiving state and the second chip 30 is in a transmitting state, so that the second chip 30 can transmit data to the first chip 10.

In the embodiment of the present invention, the first ports 11 of the first chip 10 and the second ports 31 of the second chip 30 are connected by one communication line 20, and serial communication is completed by switching the states of the first chip 10 and the second chip 30.

Alternatively, in the above embodiment of the present invention, as shown in fig. 3, each first port 11 is connected to the communication line 20 through a first resistor 12, and each second port 31 is connected to the communication line 20 through a second resistor 32.

Specifically, the first resistor 12 and the second resistor 32 may be current limiting resistors, and the resistance value of the current limiting resistor may be 1K Ω.

In an optional scheme, a current-limiting resistor can be arranged for each port of the chip, so that the problem that the ports of the single chip microcomputer are burnt out due to the fact that common time sequences are disordered, namely, level differences exist among the ports on a single wire is solved. And meanwhile, the resistor also prevents the impact of factors such as static electricity on the port.

For example, as shown in fig. 2a, a current limiting resistor R1 is disposed on the RXD port of the first chip 10, and a current limiting resistor R3 is disposed on the TXD port; the RXD port of the first chip 10 is provided with a current limiting resistor R2, and the TXD port is provided with a current limiting resistor R4. As shown in fig. 2b, a current limiting resistor R5 is disposed on the RXD port of the first chip 10, and a current limiting resistor R7 is disposed on the TXD port; a current limiting resistor R6 is provided on the IO port of the second chip 30. As shown in fig. 2c, a current limiting resistor R8 is disposed on the IO port of the first chip 10; a current limiting resistor R9 is provided on the IO port of the second chip 30.

Optionally, in the above embodiment of the present invention, as shown in fig. 3, the system further includes: a first terminal 40 and a second terminal 50, wherein the first terminal 40 includes: a first power line interface 41, a first communication line interface 42, and a first ground line interface 43, and the second terminal 50 includes: a second power line interface 51, a second communication line interface 52 and a second ground interface 53.

At least one first port 11 is connected to the first communication line interface 42 through a corresponding first resistor 12; at least one second port 31 is connected to the second communication line interface 52 through a corresponding second resistor 32; the first power line interface 41 and the second power line interface 51 are connected by a power line, the first communication line interface 42 and the second communication line interface 52 are connected by a communication line 20, and the first ground line interface 43 and the second ground line interface 53 are connected by a ground line.

In an alternative, as shown in fig. 2a to 2c, the first chip 10 and the second chip 30 may be connected through terminals without being directly connected through the communication line 20, so that when one chip fails, the chip may be directly repaired or replaced without disassembling the other chip; or, when the communication line 20 is failed, the communication line 20 can be directly replaced without detaching the two chips. The electric pressure cooker can be conveniently maintained by a user through the mode.

Optionally, in the above embodiment of the present invention, the first chip 10 is in a transmitting state after being powered on, and the second chip 30 is in a receiving state after being powered on.

In an alternative, the first chip 10 may be used as a display panel and the second chip 30 may be used as a power panel, wherein the display panel is a host and the power panel is a slave, and thus the first chip 10 may default to a transmitting state and the second chip 30 defaults to a receiving state. By presetting the states of the first chip 10 and the second chip 30, the first chip 10 and the second chip 30 can be ensured to be communicated in time after being electrified.

There is also provided, in accordance with an embodiment of the present invention, a serial communications method, it should be noted that the steps illustrated in the flowchart of the accompanying drawings may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowchart, in some cases, the steps illustrated or described may be performed in an order different than that described herein.

Optionally, the serial communication method may be applied to the serial communication system, and the communication flow of each chip in the serial communication system may refer to the scheme provided in this embodiment.

Fig. 4 is a flowchart of a serial port communication method according to an embodiment of the present invention, as shown in fig. 1 and 4, the method includes the following steps:

step S402, when the first chip 10 is in the sending state, the first chip 10 sends data to the second chip 30 through the communication line 20, wherein the second chip 30 is in the receiving state;

step S404, after the data transmission is completed, the state of the first chip 10 is switched to the receiving state;

step S406, the first chip 10 receives a response signal corresponding to the data returned by the second chip 30 through the communication line 20, wherein the second chip 30 is in a sending state;

in step S408, after the reception of the response signal is completed, the state of the first chip 10 is switched to the transmission state.

In an alternative, the first chip 10 may be used as a display panel and the second chip 30 may be used as a power panel, where the display panel is a master and the power panel is a slave. The working flow of the master is as shown in fig. 5, the master initializes to a Transmission (TX) state, and transmits data cyclically at certain time intervals to broadcast the slave. After the data transmission is completed, the state is switched to a Receiving (RX) state to wait for the response of the slave, and after the response signal transmitted by the slave is received, the state is switched to a TX state again to wait for the next cycle.

In the embodiment of the present invention, a communication line 20 is used to connect all the first ports 11 of the first chip 10 and all the second ports 31 of the second chip 30, and the state of the first chip 10 is switched based on the data transmission and reception conditions, thereby completing serial communication.

Optionally, in the above embodiment of the present invention, after the state of the first chip 10 is switched to the receiving state, the method further includes: acquiring the waiting time of the first chip 10, wherein the waiting time is the time from the state of the first chip 10 being switched to the receiving state to the response signal being received; judging whether the waiting time reaches a preset time or not; in the case where the waiting time reaches the preset time, the state of the first chip 10 is switched to the transmission state.

Specifically, the preset time may be a waiting time for the first chip 10, i.e., the master, to wait for receiving the response of the second chip 30, i.e., the slave, and may be set according to the condition of the transmission bandwidth and the response speed of the driver, which is not limited in this disclosure.

When the second chip 30, i.e., the slave, fails or a transmission failure occurs, the slave cannot respond to the first chip 10, i.e., the master in time, and if the master is always in a receiving state, the whole household appliance cannot work normally. In order to solve the above problem, in an alternative scheme, in the process of waiting for the response of the second chip 30, that is, the slave, the waiting time may be counted, and after the time expires, the timeout processing may be performed to automatically switch to the default TX state.

Optionally, in the foregoing embodiment of the present invention, when the state of the first chip 10 is switched to the receiving state, the timer is controlled to start timing, and when the first chip 10 receives the response signal, the timer is controlled to stop timing, where acquiring the waiting time of the first chip 10 includes: and acquiring the timing time of the timer.

In order to accurately count the waiting time, in an alternative scheme, the timer may be controlled to count when the first chip 10 is switched to the RX state and starts to wait for the response of the slave, and the timer may be controlled to stop counting when receiving the response signal sent by the slave, and the timer may be reset. Therefore, whether the host waiting time is overtime can be judged by reading the timing time of the timer.

Optionally, in the above embodiment of the present invention, after the data reception is completed, the state of the second chip 30 is switched to the transmission state; after the transmission of the response signal is completed, the state of the second chip 30 is switched to the receiving state.

In an alternative scheme, as shown in fig. 6, the working flow of the second chip 30, that is, the slave, is initialized to the RX state, waits for the host to broadcast a signal, switches to the TX state after receiving the broadcast signal, sends a response signal, switches to the RX state again after the transmission is finished, and waits for the next cycle. The state of the second chip 30 is switched based on the data transmission and reception conditions, thereby completing serial communication.

Optionally, in the above embodiment of the present invention, after the first chip 10 and the second chip 30 are powered on, the first chip 10 is controlled to enter the sending state, and the second chip 30 is controlled to enter the receiving state.

In an alternative, the first chip 10 may be used as a display panel and the second chip 30 may be used as a power panel, wherein the display panel is a host and the power panel is a slave, and therefore, the first chip 10 may default to the TX state and the second chip 30 may default to the RX state. By presetting the states of the first chip 10 and the second chip 30, the first chip 10 and the second chip 30 can be ensured to be communicated in time after being electrified.

Optionally, in the above embodiment of the present invention, in a case that the first chip 10 includes one first port 11, the state of the first chip 10 is switched by configuring the mapping function of the first chip 10; in a case where the first chip 10 includes two first ports 11, the state of the first chip 10 is switched by configuring modes of the two first ports 11, respectively, the modes of the two first ports 11 being different, wherein the mode includes one of: an operating mode and a high impedance state mode.

Specifically, for the TXD port, the above-described operation mode may be a Transmission (TX) mode; for the RXD port, the above-described operation mode may be a Receive (RX) mode.

In an optional scheme, for the type a single chip microcomputer, switching between the TX mode and the RX mode in the IO port mode may be achieved by configuring a mapping function built in a chip. For the B-type singlechip, the singlechip can be switched to a TX state by configuring TXD to a TX mode and RXD to a high-impedance state mode; the singlechip may be switched to the RX state by configuring TXD to the high impedance mode and RXD to the RX mode. For the first chips 10 of different types, the mode of the port is set in different ways, so as to achieve the purpose of switching the state.

Optionally, in the above embodiment of the present invention, in a case that the second chip 30 includes one second port 31, the state of the second chip 30 is switched by configuring a port mapping function of the second chip 30; in the case where the second chip 30 includes two second ports 31, the state of the second chip 30 is switched by configuring modes of the two second ports 31, respectively, the modes of the two second ports 31 being different, wherein the mode includes one of: an operating mode and a high impedance state mode.

In an alternative scheme, the state switching manner of the second chip 30 is the same as that of the first chip 10, and is not described herein again.

According to an embodiment of the present invention, there is also provided a storage medium including a stored program, wherein the program executes the serial port communication method described above.

According to the embodiment of the invention, the invention further provides a processor, wherein the processor is used for running the program, and the serial port communication method is executed when the program runs.

In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A serial communication system, comprising:

a first chip (10) comprising at least one first port (11), said at least one first port (11) being connected to a communication line (20);

a second chip (30) comprising at least one second port (31), said at least one second port (31) being connected to said communication line (20);

wherein the states of the first chip (10) and the second chip (30) are switched cyclically between a transmitting state and a receiving state, and the states of the first chip (10) and the second chip (30) are different.

2. The system according to claim 1, characterized in that the first chip (10) comprises two first ports (11) or the second chip (30) comprises two second ports (31), wherein the two first ports (11) are a transmit port and a receive port of the first chip (10), respectively, and the two second ports (31) are a transmit port and a receive port of the second chip (30), respectively.

3. System according to claim 2, characterized in that each first port (11) is connected to the communication line (20) via a first resistor (12) and each second port (31) is connected to the communication line (20) via a second resistor (32).

4. The system of claim 3, further comprising:

a first terminal (40) comprising: the first power line interface (41), the first communication line interface (42) and the first ground line interface (43), wherein the at least one first port (11) is connected to the first communication line interface (42) through a corresponding first resistor (12);

a second terminal (50) comprising: a second power line interface (51), a second communication line interface (52) and a second ground interface (53), wherein the at least one second port (31) is connected to the second communication line interface (52) through a corresponding second resistor (32);

wherein the first power line interface (41) and the second power line interface (51) are connected through a power line, the first communication line interface (42) and the second communication line interface (52) are connected through a communication line, and the first ground line interface (43) and the second ground line interface (53) are connected through a ground line.

5. The system of claim 2, wherein the first chip (10) is powered on and in a transmit state, and the second chip (30) is powered on and in a receive state.

6. A serial communication method applied to the serial communication system according to any one of claims 1 to 5, wherein the serial communication method includes:

when the first chip (10) is in a sending state, the first chip (10) sends data to the second chip (30) through the communication line (20), wherein the second chip (30) is in a receiving state;

after the data transmission is completed, the state of the first chip (10) is switched to a receiving state;

the first chip (10) receives a response signal corresponding to the data returned by the second chip (30) through the communication line (20), wherein the second chip (30) is in a sending state;

after the reception of the response signal is completed, the state of the first chip (10) is switched to a transmission state.

7. The method according to claim 6, characterized in that after the state of the first chip (10) is switched to the receiving state, the method further comprises:

acquiring the waiting time of the first chip (10), wherein the waiting time is the time from the state of the first chip (10) to the state of receiving to the time of receiving the response signal;

judging whether the waiting time reaches a preset time or not;

and under the condition that the waiting time reaches the preset time, the state of the first chip (10) is switched to a sending state.

8. The method according to claim 7, wherein when the state of the first chip (10) is switched to a receiving state, a timer is controlled to start timing, and when the first chip (10) receives the response signal, the timer is controlled to stop timing, wherein acquiring the waiting time of the first chip (10) comprises:

and acquiring the timing time of the timer.

9. The method of claim 6,

after the data reception is completed, the state of the second chip (30) is switched to a transmission state;

after the transmission of the response signal is completed, the state of the second chip (30) is switched to a receiving state.

10. The method according to claim 6, characterized in that after powering up the first chip (10) and the second chip (30), the first chip (10) is controlled to enter a transmitting state and the second chip (30) is controlled to enter a receiving state.

11. The method of claim 6,

switching the state of the first chip (10) by configuring a mapping function of the first chip (10) in case the first chip (10) comprises one first port (11);

in case the first chip (10) comprises two first ports (11), switching the state of the first chip (10) by configuring the modes of the two first ports (11) respectively, the modes of the two first ports (11) being different, wherein the mode comprises one of: an operating mode and a high impedance state mode.

12. The method of claim 6,

in case the second chip (30) comprises a second port (31), switching the state of the second chip (30) by configuring a port mapping function of the second chip (30);

in case that the second chip (30) comprises two second ports (31), switching the state of the second chip (30) by configuring the modes of the two second ports (31) respectively, the modes of the two second ports (31) being different, wherein the mode comprises one of: an operating mode and a high impedance state mode.

13. A storage medium characterized by comprising a stored program, wherein the program executes the serial communication method according to any one of claims 7 to 12.

14. A processor, characterized in that the processor is configured to execute a program, wherein the program executes the serial communication method according to any one of claims 7 to 12.