CN112865809A - ECC (error correction code) super-strong data error correction method - Google Patents

ECC (error correction code) super-strong data error correction method Download PDF

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Publication number
CN112865809A
CN112865809A CN201911178431.6A CN201911178431A CN112865809A CN 112865809 A CN112865809 A CN 112865809A CN 201911178431 A CN201911178431 A CN 201911178431A CN 112865809 A CN112865809 A CN 112865809A
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CN
China
Prior art keywords
error correction
ecc
data
code
correction method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201911178431.6A
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Chinese (zh)
Inventor
许丰
王新军
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Quantum Core Cloud Beijing Microelectronics Technology Co ltd
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Quantum Core Cloud Beijing Microelectronics Technology Co ltd
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Publication date
Application filed by Quantum Core Cloud Beijing Microelectronics Technology Co ltd filed Critical Quantum Core Cloud Beijing Microelectronics Technology Co ltd
Priority to CN201911178431.6A priority Critical patent/CN112865809A/en
Publication of CN112865809A publication Critical patent/CN112865809A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60Protecting data
    • G06F21/602Providing cryptographic facilities or services
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148Structural properties of the code parity-check or generator matrix

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Bioethics (AREA)
  • Health & Medical Sciences (AREA)
  • Mathematical Physics (AREA)
  • General Health & Medical Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Error Detection And Correction (AREA)

Abstract

The invention discloses an ECC (error correction code) ultra-strong data error correction method, which is characterized in that a secondary error correction method is added on the basis of the original hardware ECC error correction data; firstly, under the condition that the length of a check data area is allowed, a compressed ECC (error correction code) is adopted to meet basic error correction, the residual space of the original ECC is used for storing an LDPC (low density parity check) code or an extended verification code, more errors can be corrected, the extended verification code can be placed to verify whether data is illegally tampered, then in a certain range of continuous block composition areas, a small extra storage area is used to carry out secondary error correction on all ECC codes, and the data is subjected to error correction through ECC and/or LDPC (Low Density parity check), so that the stability of data error correction is greatly improved, and the data safety storage is an important guarantee.

Description

ECC (error correction code) super-strong data error correction method
Technical Field
The invention relates to an ECC (error correction code) ultra-strong data error correction method which is characterized in that a two-stage error correction method is added on the basis of compressing the existing ECC error correction data to avoid the problem caused by the error of the error correction data.
Background
The common error correction algorithm can only carry out one-level error correction, and once the error correction data have problems, the data safety is seriously influenced. By adding two-stage error correction, the multi-error repair function is provided, so that the error correction system has robustness and can be widely popularized.
Disclosure of Invention
The invention discloses an ECC (error correction code) ultra-strong data error correction method which is characterized in that a two-stage error correction method is added on the basis of the existing ECC error correction data, firstly, a compressed ECC error correction code is adopted to meet basic error correction under the condition that the length of a check data area is allowed, the residual space of the original ECC error correction code is used for storing an LDPC (low density parity check) code or an extended verification code, more errors can be corrected, the extended verification code is placed to verify whether data is illegally tampered, and then, in a certain range of continuous block composition areas, a small block extra storage area is used for carrying out secondary error correction on all ECC error correction codes.
The secondary error correction adopts more error correction capability for error repair, and ensures good error correction effect of data through more redundant units.
The ECC ultrastrong data error correction method is characterized in that the extended check code uses each part of two hash values of data to carry out data integrity check.
The ECC ultra-strong data error correction method is characterized in that the error correction code and the extended check code can be encrypted, and can be activated and identified only under the authorization condition.
Detailed Description
The specific implementation mode of the ECC ultra-strong data error correction method is that firstly, a compressed LDPC error correction algorithm is selected as a basic error correction algorithm to ensure less data redundancy and more data error correction capability, a small amount of data check codes are added after the LDPC error correction algorithm, the ECC is adopted as a secondary error correction algorithm to carry out high redundancy setting of multi-error bit repair on all redundant data and carry out encryption protection on the secondary redundant data, and the ECC can be used under specific authorization.

Claims (3)

1. An ECC ultra-strong data error correction method is characterized in that a two-stage error correction method is added on the basis of existing ECC error correction data, firstly, a compressed ECC is adopted to meet basic error correction under the condition that the length of a check data area is allowed, the original error correction code residual space is used for storing an LDPC low-density parity check code or an extended verification code, more errors can be corrected, the extended verification code is placed to verify whether data is illegally tampered, and then, in a certain range of continuous block composition areas, a small extra storage area is used for carrying out secondary error correction on all ECC error correction codes.
2. The ECC ultrastrong data error correction method of claim 1, wherein said extended check code uses a portion of each of two hash values of the data to perform a data integrity check.
3. The ECC super-strong data error correction method according to claim 2, wherein the ECC and the EDC are encrypted and identification is activated only under authorized conditions.
CN201911178431.6A 2019-11-27 2019-11-27 ECC (error correction code) super-strong data error correction method Pending CN112865809A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911178431.6A CN112865809A (en) 2019-11-27 2019-11-27 ECC (error correction code) super-strong data error correction method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911178431.6A CN112865809A (en) 2019-11-27 2019-11-27 ECC (error correction code) super-strong data error correction method

Publications (1)

Publication Number Publication Date
CN112865809A true CN112865809A (en) 2021-05-28

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CN201911178431.6A Pending CN112865809A (en) 2019-11-27 2019-11-27 ECC (error correction code) super-strong data error correction method

Country Status (1)

Country Link
CN (1) CN112865809A (en)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005093038A (en) * 2003-09-19 2005-04-07 Fujitsu Ltd Device and circuit for recording/reproducing
JP2007288721A (en) * 2006-04-20 2007-11-01 Mitsubishi Electric Corp Communication apparatus and error detecting method
US20090144598A1 (en) * 2007-11-30 2009-06-04 Tony Yoon Error correcting code predication system and method
CN101499806A (en) * 2008-01-31 2009-08-05 富士通株式会社 Encoding devices, decoding devices, encoding/decoding devices, and recording/reproduction devices
US20130055050A1 (en) * 2011-08-24 2013-02-28 Kabushiki Kaisha Toshiba Error correction encoding apparatus, error correction decoding apparatus, nonvolatile semiconductor memory system, and parity check matrix generation method
US9021336B1 (en) * 2012-05-22 2015-04-28 Pmc-Sierra, Inc. Systems and methods for redundantly storing error correction codes in a flash drive with secondary parity information spread out across each page of a group of pages
US20180205396A1 (en) * 2017-01-13 2018-07-19 Everspin Technologies Inc. Preprogrammed data recovery
US20190171518A1 (en) * 2017-12-01 2019-06-06 Burlywood, LLC Enhanced data storage with concatenated inner and outer error correction codes
CN110457160A (en) * 2019-07-02 2019-11-15 深圳市金泰克半导体有限公司 A kind of error correction method and device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005093038A (en) * 2003-09-19 2005-04-07 Fujitsu Ltd Device and circuit for recording/reproducing
JP2007288721A (en) * 2006-04-20 2007-11-01 Mitsubishi Electric Corp Communication apparatus and error detecting method
US20090144598A1 (en) * 2007-11-30 2009-06-04 Tony Yoon Error correcting code predication system and method
CN101499806A (en) * 2008-01-31 2009-08-05 富士通株式会社 Encoding devices, decoding devices, encoding/decoding devices, and recording/reproduction devices
US20130055050A1 (en) * 2011-08-24 2013-02-28 Kabushiki Kaisha Toshiba Error correction encoding apparatus, error correction decoding apparatus, nonvolatile semiconductor memory system, and parity check matrix generation method
US9021336B1 (en) * 2012-05-22 2015-04-28 Pmc-Sierra, Inc. Systems and methods for redundantly storing error correction codes in a flash drive with secondary parity information spread out across each page of a group of pages
US20180205396A1 (en) * 2017-01-13 2018-07-19 Everspin Technologies Inc. Preprogrammed data recovery
US20190171518A1 (en) * 2017-12-01 2019-06-06 Burlywood, LLC Enhanced data storage with concatenated inner and outer error correction codes
CN110457160A (en) * 2019-07-02 2019-11-15 深圳市金泰克半导体有限公司 A kind of error correction method and device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
黄勤龙 等: "《云计算数据安全》", 31 March 2018 *

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Application publication date: 20210528

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